Ordering number : EN7256A LB11870 Monolithic Digital IC For Polygonal Mirror Motors http://onsemi.com Three-Phase Brushless Motor Driver Overview The LB11870 is a three-phase brushless motor driver developed for driving the motors used with the polygonal mirror in laser printers and plain paper copiers. It can implement, with a single IC chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. The LB11870 can implement motor drive with minimal power loss due to its use of direct PWM drive. Functions • Three-phase bipolar drive • Direct PWM drive • Includes six high and low side diodes on chip. • Output current control circuit • PLL speed control circuit • Phase lock detection output (with masking function) • Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip. • Deceleration type switching circuit (free running or reverse torque) • PWM oscillator • Power saving circuit Semiconductor Components Industries, LLC, 2013 May, 2013 62707 MS IM B8-9164 / 80102 AS (OT) No.7256-1/14 LB11870 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Supply voltage VCC max Output current IO max Conditions Ratings Unit 30 T ≤ 500ms *1 Allowable power dissipation 1 Pd max1 Independent IC Allowable power dissipation 2 Pd max2 Mounted on a circuit board *2 V 2.3 A 0.85 W 1.72 W Operating temperature Topr -20 to +80 °C Storage temperature Tstg -55 to +150 °C Note *1: Be sure to perform derating from the standard value by 20% or more before use. Note *2: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage range VCC 9.5 to 28 V 5V constant voltage output current IREG 0 to -20 mA LD pin applied voltage VLD 0 to 28 V LD pin output current ILD 0 to 15 mA FGS pin applied voltage VFG 0 to 28 V FGS pin output current IFG 0 to 10 mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Parameter Symbol Supply current 1 ICC1 Supply current 2 ICC2 Conditions Ratings min typ In stop mode unit max 16 21 mA 3.5 5.0 mA 5.0 5.35 V 80 130 mV 10 60 [5V constant voltage output circuit] Output voltage VREG 4.65 Voltage regulation ΔVREG1 Load regulation ΔVREG2 VCC=9.5 to 28V IO=-5 to -20mA Temperature coefficient ΔVREG3 Design target value* VO sat1 VO sat2 IO leak IO=0.5A, VO(SINK)+VO(SOURCE) 1.9 2.4 IO=1.2A, VO(SINK)+VO(SOURCE) 2.6 3.2 V 100 μA 0 mV mV/°C [Output Block] Output saturation voltage 1 Output saturation voltage 2 Output leakage current V Lower diode forward voltage 1 VD1-1 ID=-0.5A 1.0 1.3 V Lower diode forward voltage 2 VD1-2 ID=-1.2A 1.4 1.8 V Upper diode forward voltage 1 VD2-1 ID=0.5A 1.2 1.6 V Upper diode forward voltage 2 VD2-2 ID=1.2A 1.9 2.4 V [Hall Amplifier Block] Input bias current Common-mode input voltage range IHB -2 VICM 0 VREG-2.0 80 Hall input sensitivity Input voltage: Low to high ΔVIN(HA) VSLH Input voltage: High to low VSHL Hysteresis width μA -0.5 15 V mVp-p 24 42 mV 12 mV -12 mV [FG Schmitt Block] μA IB(FGS) -2 Common-mode input voltage range VICM(FGS) 0 Input sensitivity 80 Hysteresis width VIN(FGS) ΔVIN(FGS) Input voltage: Low to high VSLH(FGS) 12 mV Input voltage: High to low VSHL(FGS) -12 mV Input bias current *: These value are design guarantee values, and are not tested. 15 -0.5 VREG-2.0 V mVp-p 24 42 mV Continued on next page. No.7256-2/14 LB11870 Continued from preceding page. Parameter Symbol Ratings Conditions min unit typ max [PWM Oscillator] High-level output voltage VOH(PWM) 2.65 2.95 3.25 V Low-level output voltage VOL(PWM) 0.9 1.2 1.5 V External capacitor charge ICHG -60 -45 -30 μA VPWM=2V current Oscillator frequency f(PWM) Amplitude V(PWM) C=680pF 34 1.45 kHz 1.75 2.05 Vp-p 0.15 0.5 V 10 μA 3.8 V [FGS Output] Output saturation voltage VOL(FGS) IFGS=7mA Output leakage current IL(FGS) VO=VCC [CSD Oscillator Circuit] High-level output voltage VOH(CSD) Low-level output voltage 3.2 3.5 VOL(CSD) 0.9 1.1 1.3 V Amplitude V(CSD) 2.15 2.4 2.65 Vp-p External capacitor charge ICHG1 -13.5 -9.5 -5.5 μA ICHG2 6 10 14 μA current External capacitor charge current f(CSD) C=0.068μF High-level output voltage VPDH IOH=-100μA Low-level output voltage VPDL IOL=100μA Output source current IPD+ VPD=VREG/2 Output sink current IPD- VPD=VREG/2 Oscillator frequency 29 Hz [Phase Comparator Output] VREG-0.2 VREG-0.1 0.2 V 0.3 -0.5 1.5 V mA mA [Lock Detection Output] Output saturation voltage Output leakage current VOL(LD) IL(LD) 0.15 0.5 V 10 μA -10 10 mV -1 1 μA 0.9 1.2 V -5% VREG/2 5% V 0.4 0.5 0.6 deg ILD=10mA VO=VCC [Error Amplifier Block] Input offset voltage Input bias current VIO(ER) Output H level voltage VOH(ER) Output L level current VOL(ER) DC bias level Design target value* IB(ER) IOH=-500μA VREG-1.2 IOL=500μA VB(ER) VREG-0.9 V [Current limiter Circuit] Drive gain 1 GDF1 Drive gain 2 GDF2 Limiter voltage VRF When the phase is locked 0.8 1.0 1.2 deg VCC-VM 0.45 0.5 0.55 V Design target value* 150 175 °C 40 °C When not locked [Thermal Shutdown Operation] Thermal shutdown operating TSD temperature Hysteresis width (junction temperature) ΔTSD Design target value* (junction temperature) [Low-Voltage Protection] Operating voltage Hysteresis width VSD 8.1 8.45 8.9 V ΔVSD 0.2 0.35 0.5 V *: These value are design guarantee values, and are not tested. Continued on next page. No.7256-3/14 LB11870 Continued from preceding page. Parameter Symbol Ratings Conditions min unit typ max [CLD Circuit] -6 -4.3 -3 μA VH(CLD) 3.25 3.5 3.75 V External input frequency fI(CLK) 0.1 10 High-level input voltage VIH(CLK) 3.5 VREG V Low-level input voltage VIL(CLK) 0 1.5 V Input open voltage VIO(CLK) VREG-0.5 VREG V Hysteresis width VIS(CLK) High-level input current IIH(CLK) VCLK=VREG Low-level input current IIL(CLK) VCLK=0V External capacitor charge ICLD current Operating voltage [CLK Pin] kHz 0.35 0.5 0.65 V -10 0 10 μA -280 -210 μA [S/S Pin] High-level input voltage VIH(SS) 3.5 VREG V Low-level input voltage VIL(SS) 0 1.5 V Input open voltage VIO(SS) VREG-0.5 VREG V Hysteresis width VIS(SS) High-level input current IIH(SS) VS/S=VREG Low-level input current IIL(SS) VS/S=0V 0.35 0.5 0.65 V -10 0 10 μA -280 -210 μA [BRSEL Pin] High-level input voltage VIH(BRSEL) 3.5 VREG V Low-level input voltage VIL(BRSEL) 0 1.5 V Input open voltage VIO(BRSEL) High-level input current IIH(BRSEL) VBRSEL=VREG Low-level input current IIL(BRSEL) VBRSEL=0V VREG-0.5 -10 0 -220 -160 VREG V 10 μA μA Package Dimensions unit : mm (typ) 3278 Pd max - Ta 17.8 2.0 (6.2) 48 24 1.3 0.65 0.2 0.2 1.6 1.2 Independent IC 0.85W 0.963W 0.8 0.476W 0.4 2.4 max (2.2) (0.45) Power dissipation, Pd max - W 0.65 7.9 10.5 (4.9) 25 1 Mounted on a board (114.3 × 76.1 × 1.6mm, glass epoxy) 1.72W 0 -20 0 20 40 60 1.5 80 100 ILB01545 0.1 Ambient temperature, Ta - °C SANYO : HSSOP48(375mil) No.7256-4/14 LB11870 NC NC LD FGS CLD CSD FGFIL 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 FC NC PD EI EO TOC 37 NC VM1 38 S/S VM2 39 PWM VCC2 40 CLK VCC1 41 GND2 NC 42 BRSEL NC 43 GND1 NC 44 PH GND3 45 FGIN– NC 46 VREG OUT3 47 FGIN+ NC 48 FRAME NC Pin Assignment 7 NC OUT1 NC NC IN3+ NC 8 9 10 11 12 FRAME 6 IN1– 5 IN1+ 4 IN2– 3 IN2+ 2 IN3– 1 OUT2 LB11870 Three-Phase Logic Truth Table (IN = [H] indicates a condition in which: IN+ > IN–) IN1 IN2 IN3 OUT1 OUT2 OUT3 H L H H L L L H M L M H H L M H L H M L H L H L L H H H M L L L H M H L No.7256-5/14 LB11870 Block Diagram and Application Circuit Example VREG FGFIL VREG FGS CLD LD PD FGIN– FGIN+ LD – LDMASK FG FILTER + EI VREG – EO + CLK PLL CLK TOC TSD VREG PWM PWM S/S CONT COMP OSC VREG FC AMP S/S PH PEAK HOLD VCC VCC2 BRSEL BRSEL CURR LOGIC LIM CSD CSD OSC VCC1 VM2 Rf VM1 COUNT OUT1 HALL LOGIC DRIVER OUT2 HALL HYS AMP IN1+ IN1– IN2+ IN2– IN3+ IN3– OUT3 GND1 GND2 GND3 VREG No.7256-6/14 LB11870 Pin Functions Pin No. Symbol 3 OUT1 1 OUT2 46 OUT3 44 GND3 Pin Description Equivalent Circuit Motor drive output 39 VCC1 38 300Ω Output block ground 37 37 VM1 Output block power supply and current 38 VM2 detection. Insert the resistor Rf between this pin and 1 VCC1. The output current will be limited to the current 3 46 value IOUT = VRF/Rf. 39 VCC2 Upper diode cathode connection. Short this pin 44 to VCC1. 11 IN1+ 12 IN1- Hall element inputs. The high state is when IN+ is greater than IN-, 9 IN2+ and the low state is the reverse. 10 IN2- An amplitude of at least 100mVp-p (differential) 6 IN3+ is desirable for the Hall element signal inputs. If 8 IN3- noise on the Hall signals is a problem, insert capacitors between the IN+ and IN- inputs. 13 14 FGIN+ FGIN- VREG 300Ω 300Ω 6 9 11 FG input. 8 10 12 VREG If noise on the FG signal input is a problem, connect a filter consisting of either a capacitor or a capacitor and a resistor. 300Ω 300Ω 13 15 GND1 Control circuit block ground 16 GND2 SUBGND pin 17 PWM Sets the PWM oscillator frequency. 14 VREG Insert a capacitor between this pin and ground. The PWM oscillator frequency is set to about 34kHz when a 680pF capacitor is used. 200Ω 2kΩ 17 Continued on next page. No.7256-7/14 LB11870 Continued from preceding page. Pin No. Symbol 19 FC Pin Description Frequency characteristics correction for the Equivalent Circuit VREG current control circuit. Insert a capacitor (about 0.01 to 0.1μF) between this pin and ground. The output duty is determined by comparing the voltage on this pin to the PWM oscillator waveform. 300Ω 19 21 PD Phase comparator output. VREG The phase error is converted to a pulse duty and output from this pin. 300Ω 21 22 EI Error amplifier input. VREG 300Ω 22 23 EO Error amplifier output. VREG 40kΩ 23 24 TOC Torque command voltage input. VREG This pin is normally connected to the EO pin. When the TOC voltage falls, the lower output transistor on duty is increased. 300Ω 24 Continued on next page. No.7256-8/14 LB11870 Continued from preceding page. Pin No. Symbol 25 FGFIL Pin Description Equivalent Circuit FG filter connection. VREG If noise on the FG signal input is a problem, insert a capacitor (up to about 2200pF) between this pin and ground. 25 26 CSD Sets the rotor constraint protection circuit VREG operating time and the initial reset pulse. A protection operating time of about 8 seconds can be set by insert a capacitor of about 0.068μF between this pin and ground. If the rotor constraint protection circuit is not used, insert a resistor and a capacitor in parallel 300Ω between this pin and ground. (Values: about 26 220kΩ and 4700pF) 27 CLD Sets the phase lock state signal mask time. VREG A mask time of about 90ms can be set by inserting a capacitor of about 0.1μF between this pin and ground. Leave this pin open if masking is not required. 300Ω 27 28 FGS FG Schmitt output. VREG 28 29 LD Phase lock state detection output. VREG This output goes to the on state (low level) when the phase is locked. 29 Continued on next page. No.7256-9/14 LB11870 Continued from preceding page. Pin No. Symbol 32 S/S Pin Description Start/stop control input. Equivalent Circuit VREG Low: 0 to 1.5V High: 3.5V to VREG Hysteresis: 0.5V 22kΩ Low: start. This pin goes to the high level when open. 2kΩ 32 33 CLK Clock input. VREG Low: 0 to 1.5V High: 3.5V to VREG Hysteresis: 0.5V 22kΩ fCLK = 10kHz (maximum) If noise is a problem, use a capacitor to remove that noise at this input. 2kΩ 33 34 BRSEL Deceleration switching control input. VREG Low: 0 to 1.5V High: 3.5V to VREG This pin goes to the high level when open. 30kΩ Low: reverse torque control, High: free running. An external Schottky barrier diode is required on the output low side if reverse torque control 2kΩ is used. 34 35 PH RF waveform smoothing. VREG If noise on the RF waveform is a problem, insert a capacitor between this pin and ground. 500Ω 35 Continued on next page. No.7256-10/14 LB11870 Continued from preceding page. Pin No. Symbol 36 VREG Pin Description Stabilized power supply output (5V output). Equivalent Circuit VCC Insert a capacitor of about 0.1μF between this pin and ground for stabilization. 36 40 VCC1 Power supply. Insert a capacitor of at least 10µF between this pin and ground to prevent noise from entering the IC. 2, 4, 5 NC Since these pins are not connected to the IC 7, 18 internally, they can be used for wiring 20, 30 connections. 31, 41 42, 43 45, 47 48 FRAME Connect this pin to ground. Overview of the LB11870 1. Speed Control Circuit This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter. This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (falling edges on the FGIN+ and FGS signals), and the IC uses the detected error to control motor speed. During this control operation, the FG servo frequency will be the same as the CLK frequency. fFG (servo) = fCLK 2. Output Drive Circuit To minimize power loss in the output circuits, this IC adopts a direct PWM drive technique. The output transistors are always saturated when on, and the IC adjusts the motor drive output by changing the output on duty. The low side output transistor is used for the output PWM switching. Both the high and low side output diodes are integrated in the IC. However, if reverse torque control mode is selected for use during deceleration, or if a large output current is used and problems occur (such as incorrect operation or waveform disruption due to low side kickback), a Schottky diode should be inserted between OUT and ground. Also, if it is necessary to reduce IC heating during steady-state (constant speed) operation, it may be effective to insert a Schottky diode between VCC and OUT. (This is effective because the load associated with the regenerative current during PWM switching is born not by the on-chip diode but by the external diode.) 3. Current Limiter Circuit The current limiter circuit limits the peak level of the current to a level determined by I = VRF/Rf (where VRF = 0.5V (typical) and Rf is the value of the current detection resistor). The current limiter operates by reducing the output on duty to suppress the current. The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the current limiting function does not malfunction, its operation has a delay of about 2μs. If the motor coils have a low resistance or a low inductance, current fluctuations at startup (when there is no reactive power in the motor) will be rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above the set current. Designers must take this increase in the current due to the delay into account when setting the current limiter value. No.7256-11/14 LB11870 4. Power Saving Circuit This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is implemented by removing the bias current from most of the circuits in the IC. However, the 5V regulator output is provided in the power saving state. 5. Reference Clock Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. If the IC is set to the start state when the reference clock signal is not present, if the rotor constraint protection circuit is used, the motor will turn somewhat and then motor drive will be shut off. However, if the rotor constraint protection circuit is not used, and furthermore reverse torque control mode is selected for deceleration, the motor will be driven at ever increasing speed in the reverse direction. (This is because the rotor constraint protection circuit oscillator signal is used for clock cutoff protection.) Applications must implement a workaround for this problem if there is any possibility whatsoever for it to occur. 6. Notes on the PWM Frequency The PWM frequency is determined by the value of the capacitor C (in F) connected to the PWM pin. fPWM ≈ 1 / (43000 × C) If a 680pF capacitor is used, the circuit will oscillate at about 34kHz. If the PWM frequency is too low, the motor will emit switching noise, and if it is too high, the power loss in the output will be excessive. A PWM frequency in the range 15 to 50kHz is desirable. To minimize the influence of the output on this circuit, the ground lead of this capacitor should be connected as close as possible to the IC control system ground (the GND1 pin). 7. Hall Input Signals Signals with an amplitude in excess of the hysteresis (42mV maximum) must be provided as the Hall input signals. However, an amplitude of over 100mV is desirable to minimize the influence of noise. If the output waveforms are disturbed (at phase switching) due to noise on the Hall inputs, insert capacitors across these inputs. 8. FG Input Signal Normally, one phase of the Hall signals is input as the FG signal. If noise is a problem the input must be filtered with either a capacitor or an RC filter circuit. Although it is also possible to remove FG signal noise by inserting a capacitor between the FGFIL pin and ground, the IC may not be able to operate correctly if this signal is damped excessively. If this capacitor is used, its value must be less than about 2200pF. If the location of this capacitor's ground lead is inappropriate, it may, inversely, make noise problems even more likely to occur. Thus the ground lead location must be chosen carefully. 9. Rotor Constraint Protection Circuit This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained. If the LD output is high (unlocked) for over a certain fixed period with the IC in the start state, the low side transistor will be turned off. The time constant is determined by the capacitor connected to the CSD pin. <time constant (in seconds)> ≈ 120 × C (μF) If a 0.068μF capacitor is used, the protection time will be about 8 seconds. The set time must be selected to have an adequate margin with respect to the motor startup time. This protection circuit will not operate during deceleration when the clock frequency is switched. To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and reapplied. Since the CSD pin also functions as the initial reset pulse generation pin at startup, the logic circuit will go to the reset state and the IC will not be able to function if this pin is connected to ground. Therefore, both a 220kΩ resistor and a 4700pF capacitor must be inserted between this pin and ground if the rotor constraint protection circuit is not used. No.7256-12/14 LB11870 10. Phase Lock Signal (1) Phase lock range Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) Masking function for the phase lock state signal A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pullin. However, this results in the lock state signal output being delayed by the masking time. The masking time is determined by the capacitor inserted between the CLD pin and ground. <masking time (seconds)> ≈ 0.9 × C (μF) When a 0.1μF capacitor is used, the masking time will be about 90ms. In cases where complete masking is required, a masking time with fully adequate margin must be used. If no masking is required, leave the CLD pin open. 11. Power Supply Stabilization Since this IC provides a large output current and adopts a switching drive technique, the power supply line level can be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the VCC pins and ground. The ground leads of these capacitors must be connected to the three pins that are the power grounds, and they must be connected as close as possible to the pins themselves. If these capacitors (electrolytic capacitors) cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1μF must be connected near these pins. If reverse torque control mode is selected for use during deceleration, since there are states where power is returned to the power supply system, the power supply line levels will be particularly easily disrupted. Since the power line level is most easily disrupted during lock pull-in at high motor speeds, this state needs extra attention; in particular, capacitors that are adequately large to handle this situation must be selected. If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. 12. VREG Stabilization A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply. The ground lead of that capacitor must be connected as close as possible to the IC control system ground (GND1). 13. Error Amplifier External Component Values To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as possible. In particular, they must be located as far from the motor as possible. 14. FRAME Pin and the IC Metallic Rear Surface The FRAME pin must be connected to the GND1 and GND2 pins, and the ground side of the electrolytic capacitor must be connected to GND3. The IC's metallic rear surface is connected to the FRAME pin internally to the IC. Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package to the PCB with, for example, a solder with good thermal conductivity. No.7256-13/14 LB11870 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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