LV8112VB D

LV8112VB
Bi-CMOS LSI
3-phase Brushless Motor Driver
for Polygon Mirror Motor
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Overview
The LV8112VB is a 3-phase brushless motor driver for polygon mirror
motor driving of LBP.
A circuit needed to drive of polygon mirror motor can be composed of
a single-chip. Also, the output transistor is made DMOS by using
BiDC process, and by adopting the synchronous rectification method,
the lower power consumption (Heat generation) is achieved.
Feature
 3-phase bipolar drive
 Direct PWM drive + synchronous rectification
 IO max1 = 2.5A
 IO max2 = 3.0A (t  0.1ms)
 Output current control circuit
 PLL speed control circuit
 Phase lock detection output
(with mask function)
 Current limiter, constraint protection, thermal
shutdown, under-voltage protection circuit
 Circuit to switch slowing down method while stopped
(Free run or Short-circuit brake)
 Constraint protection detection signal switching circuit (FG or LD)
 Forward / Reverse switching circuit
 Compatible with Hall FG
 Hall bias pin (Bias current cut in a stopped state)
 5V regulator output
 SDCC function (Speed Detection Current Control)
SSOP44K(275mil) Exposed Pad
Typical Applications
 Laser beam printer (LBP)
 Plain paper copier (PPC)
 Multi function printer (MFP)
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. 1
1
Publication Order Number :
LV8112VB/D
LV8112VB
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
VCC max
VCC pin
37
VG max
VG pin
42
V
V
Output current
IO max1
*1
2.5
A
IO max2
t  0.1ms *1
3.0
A
Allowable Power dissipation
Pd max
Mounted on a specified board *2
1.7
W
Operation temperature
Topr
-25 to +80
C
Storage temperature
Tstg
-55 to +150
C
Junction temperature
Tj max
150
C
*1. Tj max = 150C must not be exceeded.
*2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
10 to 35
V
5V constant voltage output current
IREG
0 to -30
mA
LD pin applied voltage
VLD
0 to 5.5
V
LD pin output current
ILD
0 to 15
mA
FG pin applied voltage
VFG
0 to 5.5
V
FG pin output current
IFG
0 to 15
mA
HB pin output current
IHB
0 to -30
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta  25C, VCC = 24V
Ratings
Parameter
Symbol
Conditions
Unit
min
Current drain
ICC1
ICC2
In a stop state
typ
max
5.5
6.5
mA
1.0
1.5
mA
5.0
5.35
V
mV
5V Constant Voltage Output
Output voltage
VREG
4.65
Line regulation
VREG1
VCC = 10 to 35V
20
100
Load regulation
VREG2
IO = -5 to -20mA
25
60
Temperature coefficient
VREG3
Design target value *
RON
IO = 1A , Sum of the lower and upper side
outputs
Output leakage current
IOleak
Design target value *
Lower side Diode forward voltage
VD1
Upper side Diode forward voltage
VD2
0
mV
mV/C
Output Block
Output ON resistance
1.5
1.9

10
A
ID = -1A
1.0
1.35
V
ID = 1A
1.0
1.35
V
Charge Pump Output (VG pin)
Output voltage
VGOUT
VCC+4.9
V
CP1 pin
Output ON resistance (High level)
VOH(CP1)
ICP1 = -2mA, Design target value *
500
700

Output ON resistance (Low level)
VOL(CP1)
ICP1 = 2mA
300
400

* Design target value, Do not measurement.
Continued on next page.
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LV8112VB
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Hall Amplifier Block
Input bias current
IHB(HA)
Common mode input voltage range
VICM
-2
0.5
Hall input sensitivity
Hysteresis
A
-0.5
VREG-2.0
80
VIN(HA)
15
V
mVp-p
24
42
mV
Input voltage L  H
VSLH
12
mV
Input voltage H  L
VSHL
-12
mV
Hall Bias (HB pin) P-channel Output
Output voltage ON resistance
VOL(HB)
IHB = -20mA
Output leakage current
IL(HB)
VO = 0V
20
GFG
Design target value *
Input hysteresis (H  L)
VSHL(FGS)
Input hysteresis (L  H)
VSLH(FGS)
Hysteresis
VFGL
30

10
A
FG Amplifier Schmitt Block (IN1)
Input amplifier gain
5
times
Input referred, Design target value *
0
mV
Input referred, Design target value *
10
mV
Input referred, Design target value *
10
mV
FGFIL pin
High level output voltage
VOH(FGFIL)
2.7
3.0
3.3
V
Low level output voltage
VOL(FGFIL)
0.75
0.85
0.95
V
External capacitor charge current
ICHG1
VCHG1 = 1.5V
-5
-4
-3
A
External capacitor discharge current
ICHG2
VCHG2 = 1.5V
3
4
5
Amplitude
V(FGFIL)
1.95
2.15
2.35
A
Vp-p
FG Output
Output ON resistance
VOL(FG)
IFG = 7mA
Output leakage current
IL(FG)
VO = 5.5V
20
30

10
A
V
PWM Oscillator
High level output voltage
VOH(PWM)
2.95
3.2
3.45
Low level output voltage
VOL(PWM)
1.3
1.5
1.7
V
External capacitor charge current
ICHG(PWM)
VPWM = 2V
-90
-70
-50
A
Oscillation frequency
f(PWM)
C = 150pF
180
225
270
kHz
Amplitude
V(PWM)
1.5
1.7
1.9
Vp-p
Recommended operation frequency
fOPR
15
300
kHz
VOH(CSD)
2.7
3.3
V
range
CSD Oscillation Circuit
High level output voltage
Low level output voltage
VOL(CSD)
Amplitude
V(CSD)
External capacitor charge current
ICHG1(CSD) VCHG1 = 2.0V
3.0
0.8
1.0
1.2
V
1.75
2.0
2.25
Vp-p
-14
-10
-6
A
8
11
14
A
30
40
50
Hz
External capacitor discharge current
ICHG2(CSD) VCHG2 = 2.0V
Oscillation frequency
f(CSD)
C = 0.068F, Design target value *
Output ON resistance (high level)
VPDH
IOH = -100A
500
700

Output ON resistance (low level)
VPDL
IOL = 100A
500
700

Output ON resistance
VOL(LD)
ILD = 10mA
20
30

Output leakage current
IL(LD)
VO = 5.5V
10
A
VIO(ER)
Design target value *
+10
mV
+1
A
Phase comparing output
Phase Lock Detection Output
Error Amplifier Block
Input offset voltage
-10
Input bias current
IB(ER)
High level output voltage
VOH(ER)
IEI = -100A
EI+0.7
-1
EI+0.85
EI+1.0
V
Low level output voltage
VOL(ER)
IEI = 100A
EI-1.75
EI-1.6
EI-1.45
V
DC bias level
VB(ER)
-5%
VREG/2
5%
V
* Design target value, Do not measurement.
Continued on next page.
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LV8112VB
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Current Control Circuit
Drive gain
GDF
While phase locked
0.5
0.55
0.6
0.465
0.515
0.565
times
Current Limiter Circuit (pins RF and RFS)
Limiter voltage
VRF
V
Under-voltage Protection
Operation voltage
VSD
8.3
8.7
9.1
V
Hysteresis
VSD
0.2
0.35
0.5
V
CLD Circuit
External capacitor charge current
ICLD
Operation voltage
VH(CLD)
VCLD = 0V
-4.5
-3.0
-1.5
A
3.25
3.5
3.75
V
150
175
C
30
C
Thermal Shutdown Operation
Thermal shutdown operation
TSD
Design target value (Junction temperature)
TSD
Design target value (Junction temperature)
temperature
Hysteresis
CLK pin
External input frequency
fI(CLK)
0.1
10
High level input voltage
VIH(CLK)
2.0
VREG
kHz
V
Low level input voltage
VIL(CLK)
0
1.0
V
Input open voltage
VIO(CLK)
VREG-0.5
VREG
V
Hysteresis
VIS(CLK)
0.2
0.3
0.4
V
High level input current
IIH(CLK)
VCLK = VREG
-10
0
+10
A
Low level input current
IIL(CLK)
VCLK = 0V
-110
-85
-60
A
VREG
V
V
CSDSEL pin
High level input voltage
VIH(CSD)
2.0
Low level input voltage
VIL(CSD)
0
1.0
Input open voltage
VIO(CSD)
VREG-0.5
VREG
V
High level input current
IIH(CSD)
VCSDSEL = VREG
Low level input current
IIL(CSD)
VCSDSEL = 0V
-10
0
+10
A
-110
-85
-60
A
S/S pin
High level input voltage
VIH(SS)
2.0
VREG
V
Low level input voltage
VIL(SS)
0
1.0
V
Input open voltage
VIO(SS)
VREG-0.5
VREG
V
Hysteresis
VIS(SS)
0.2
0.3
0.4
V
High level input current
IIH(SS)
VS/S = VREG
-10
0
+10
A
Low level input current
IIL(SS)
VS/S =0V
-110
-85
-60
A
VREG
V
V
BRSEL pin
High level input voltage
VIH(BRSEL)
2.0
Low level input voltage
VIL(BRSEL)
0
1.0
Input open voltage
VIO(BRSEL)
VREG-0.5
VREG
V
High level input current
IIH(BRSEL)
VBRSEL = VREG
Low level input current
IIL(BRSEL)
VBRSEL = 0V
-10
0
+10
A
-110
-85
-60
A
F/R pin
High level input voltage
VIH(FR)
2.0
VREG
V
Low level input voltage
VIL(FR)
0
1.0
V
Input open voltage
VIO(FR)
High level input current
IIH(FR)
VF/R = VREG
VREG-0.5
Low level input current
IIL(FR)
VF/R = 0V
VREG
V
-10
0
+10
A
-110
-85
-60
A
* Design target value, Do not measurement.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LV8112VB
Package Dimensions
unit : mm
SSOP44K (275mil) Exposed Pad
CASE 940AF
ISSUE A
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LV8112VB
1.00
SOLDERING FOOTPRINT*
(Unit: mm)
7.00
(3.5)
(4.7)
0.65
0.32
NOTES:
1. The measurements are for reference only, and unable to guarantee.
2. Please take appropriate action to design the actual Exposed Die Pad and Fin portion.
3. After setting, verification on the product must be done.
(Although there are no recommended design for Exposed Die Pad and Fin portion Metal mask and shape
for Through-Hole pitch (Pitch & Via etc), checking the soldered joint condition and reliability verification of
soldered joint will be needed. Void gradient insufficient thickness of soldered joint or bond degradation
could lead IC destruction because thermal conduction to substrate becomes poor.)
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
may or may not be present.
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LV8112VB
Pd max -- Ta
Allowable power dissipation, Pd max -- W
2.0
1.7
1.5
1.0
0.95
0.5
0
-25
0
25
75 80
50
100
Ambient temperature, Ta -- C
IN3+
IN2−
IN2+
IN1−
IN1+
31
30
29
28
27
26
25
24
23
14
15
16
17
18
19
20
21
22
EO
TOC
GND
HB
34
EI
35
IN3−
36
PD
37
SUB
38
PH
RF
39
GND2
RFS
40
FGFIL
VCC2
41
FC
VCC1
42
OUT3
VG
43
OUT2
CP1
44
OUT1
CP2
Pin Assignment
33
32
2
3
4
5
6
7
8
9
10
LD
S/S
VREG
BRSEL
CSDSEL
F/R
CLD
CSD
FG
11
12
13
PWM
1
CLK
LV8111V
LV8112VB
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Top view
LV8112VB
Block Diagram and Application Circuit Example
PWM
CSDSEL
PD
CSDSEL
CSD
CSD
OSC
COUNT
PWM
OSC
LOGIC
EI
VREG
BRSEL
BRSEL
LOGIC
EO
TOC
S/S
S/S
COMP
F/R
FC
PEAK
HOLD
PH
F/R
TSD
LD output
CONT
AMP
LD
LD
CLD
LD
MASK
VREG
VREG
PLL
CLK input
FG output
CLK
VCC
LVSD
VCC1
VCC2
CLK
CONTROL
CIRCUIT
FG
VG
FG
CHARGE
PUMP
CP1
CP2
FGFIL
FILTER
OUT1
DRIVER
OUT2
HALL HYS AMP
IN1+
IN1−
IN2+
IN2−
IN3+
HB
IN3−
HB
CURR
LIM
RFS
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OUT3
SUB
RF
GND
GND2
LV8112VB
Pin Function
Pin No.
1
Pin name
CLK
Function
Equivalent circuit
Clock input pin (10kHz maximum)
VREG
55kΩ
5kΩ
10kΩ
1
2
LD
Phase lock detection output pin.
VREG
Goes ON during PLL-phase lock.
Open drain output.
2
3
S/S
Start/Stop input pin.
VREG
Start with low-level input.
Stop with high-level input or open input
55kΩ
5kΩ
10kΩ
3
4
VREG
5V regulator output pin.
VCC
(the control circuit power supply)
50Ω
Connect a capacitor between this pin and GND for
stabilization.
4
5
BRSEL
Brake selection pin.
VREG
By low-level, short-circuit braking when the S/S pin is in a
stopped state.
(Brake for the inspection process)
55kΩ
5kΩ
5
6
CSDSEL
Motor constraint protection detection signal selection pin.
VREG
Select FG with low,
and LD with high or in an open state.
55kΩ
5kΩ
6
Continued on next page.
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LV8112VB
Continued from preceding page.
Pin No.
7
Pin name
F/R
Function
Equivalent circuit
Forward / Reverse selection pin.
VREG
55kΩ
5kΩ
7
8
CLD
Phase lock signal mask time setting pin.
VREG
Connect a capacitor between this pin and GND.
When it is not necessary to mask, this pin must be left open.
500Ω
8
2kΩ
9
CSD
Pin for both the constraint protection circuit operation time
VREG
setting and the initial reset pulse setting.
Connect a capacitor between this pin and GND.
If the motor constraint protection circuit is not used,
500Ω
a capacitor and a resistor must be connected in parallel
9
between the CSD pin and GND.
10
FG
FG Schmitt output pin.
VREG
Open drain output.
10
12
PWM
Pin to set the oscillation frequency of PWM.
VREG
Connect a capacitor between this pin and GND.
200Ω
12
2kΩ
14
FC
Frequency characteristics correction pin of the current
VREG
control circuit.
Connect a capacitor between this pin and GND.
500Ω
14
110kΩ
Continued on next page.
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LV8112VB
Continued from preceding page.
Pin No.
15
Pin name
FGFIL
Function
Equivalent circuit
FG filter pin.
VREG
When the noise of the FG signal is a problem, connect a
capacitor between this pin and GND.
15
16
PH
Pin to stabilize the RF waveform.
VREG
Connect a capacitor between this pin and GND.
500Ω
16
10kΩ
17
PD
Phase comparison output pin.
VREG
The phase error is output by using the duty changes of the
pulse.
500Ω
17
18
EI
Error amplifier input pin.
VREG
500Ω
18
19
EO
Error amplifier output pin.
VREG
19
100kΩ
20
TOC
Torque command voltage input pin.
VREG
Normally, this pin must be connected with the EO pin.
On-duty of upper-side output Tr increases when the TOC
voltage decreases.
20
21
GND
Ground pin of the control circuit block.
Continued on next page.
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LV8112VB
Continued from preceding page.
Pin No.
22
Pin name
HB
Function
Equivalent circuit
Hall element bias current pin.
VREG
Goes ON when the S/S pin is in a start state.
Goes OFF when the S/S pin is in a stopped state.
22
IN1+
IN1
Hall amplifier input pin.
IN2+
IN2
Reverse case is a low-level state.
desirable in the Hall inputs.
28
IN3+
IN3
29
SUB
Frame ground pin. Connect this pin with the GND2 pin.
30
GND2
Ground pin of the output circuit block.
32
OUT3
Output pin.
34
OUT2
As for PWM, a duty control is executed on the upper side
36
OUT1
FET.
23
24
25
26
27
VREG
A high-level state of logic is recognized when IN+ > IN.
The input amplitude of 100mVp-p or more (differential) is
When the noise of the Hall signal is a problem, connect the
capacitors between IN+ and IN.
500Ω
500Ω
24 26 28
23 25 27
VCC
32 34 36
38
RF
Source pin of output MOSFET (lower).
38
Connect low resister (Rf) between this pin and GND.
39
RFS
Output current detection pin.
VREG
Connect this pin to the RF pin.
5kΩ
39
40
VCC2
Power supply pin for output.
Connect a capacitor between this pin and GND for
stabilization.
41
VCC1
42
VG
Power supply pin for control.
Charge pump output pin (power supply for the upper side
FET gate).
VCC
Connect a capacitor between this pin and VCC.
500Ω
43
100Ω
43
CP1
Pin to connect a capacitor for charge pump.
44
CP2
Connect a capacitor between CP1 and CP2.
42
44
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LV8112VB
3-phase Logic Truth Table
(IN = “H” indicates the state where in IN+ > IN)
F/R = H
F/R = L
IN1
IN2
Output
IN1
IN2
IN3
IN3
OUT1
H
L
H
L
H
L
H
L
L
L
H
H
H
H
L
L
L
H
M
L
H
L
H
L
H
L
H
H
H
L
L
L
L
H
H
H
L
M
S/S Pin
OUT2
OUT3
L
H
M
L
M
H
L
H
H
L
M
H
M
L
H
L
BRSEL Pin
Input state
Mode
Input state
High or Open
Stop
High or Open
Free run
Low
Start
Low
Short-circuit brake
CSDSEL Pin
While stopped
Selection of SDCC function
Input state
Mode
Input state
Mode
High or Open
LD standard
F/R = High or Open
Function ON
Low
FG standard
F/R = Low
Function OFF
LV8112VB Description
1. Speed Control Circuit
This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method.
This PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls by
using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency.
fFG (Servo) = fCLK
2. Output Drive Circuit
This IC adopts the direct PWM drive method to reduce power loss in the output. The driving force of the motor is
adjusted by changing the on-duty of the output transistor. The PWM switching of the output is performed by the
upper-side output transistor.
Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off.
But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification.
3. Current Limiter Circuit
This IC limits the (peak) current at the value
I = VRF / Rf (VRF = 0.515V (typical), Rf : current detection resister).
The current limitation operation consists of reducing the PWM output on duty to suppress the current.
To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the
operation has a delay (approximately 300ns). Since the current change at the motor start-up is fast when the motor coil
is lower resistance or smaller inductance, the current more than the setting value may flow during this delay time.
In this case, it is necessary to set the limiter value considering the current that increased by the delay.
4. Power Saving Circuit
This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the
majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state.
5. Reference Clock
Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis.
But, if noise is a problem, that noise must be excluded by inserting capacitor.
When the IC is switched to the start state if the reference clock is no input, the drive is turned off after a few rotations
if the motor constraint protection circuit is used. (Clock disconnection protection)
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13
LV8112VB
6. PWM Frequency
The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin.
fPWM  1 / (29500  C ) … 150pF or more
fPWM  1 / (32000  C ) … 100pF or more, less than 150pF
The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected.
The GND of a capacitor must be placed as close to the control block GND (GND pin) of the IC as possible to reduce
influence of the output.
7. Hall Effect Sensor Input Signals
The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs.
Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise.
If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting
capacitors across the inputs.
8. FG Signal
The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be
excluded by inserting a capacitor between the FGFIL pin and GND. But note that normal operation becomes
impossible if the value of the capacitor is overlarge. Also, note that the trouble of noise occurs easily when the
position of GND of the capacitor is incorrect.
9. Constraint Protection Circuit
This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. When
the CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed
period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed
period in the start state, this circuit operates. Also, the upper-side output transistor is turned off while the constraint
protection circuit is operating. This time is set by the capacitance of the capacitor connected to the CSD pin.
The set time (in seconds) is 102  C (F)
When a capacitor of 0.068F is connected, the protection time becomes about 7.0 seconds.
The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the
clock frequency, this protection circuit is not operated. To release the constraint protection state, put the S/S pin into
the start again after the stop state, or turn on the power supply again after the turn off state. The CSD pin has a function
as the power-on reset pin also. If the CSD pin is connected to GND, the logic circuit goes to the reset state and the
speed cannot be controlled.
Therefore, if the constraint protection circuit is not used, a resistor of about 220k and a capacitor of about 4700pF
must be connected in parallel between the CSD pin and GND.
10. Phase Lock Signal
(1) Phase lock range
This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the
characteristics of the IC. ( because the accelerations of the change in FG frequency influences.)
When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating
must be measured. Since the speed error is likely to occur when the acceleration of FG is larger, the speed error will
be the largest when the IC goes into the lock state at motor start-up, or the unlock state by switching the clock.
(2) Phase lock signal mask function
This function can mask the short lock signal that occurred by the hunting when it goes into the lock state. Therefore,
the IC will be able to output the stable lock signal. But the mask time causes the delay of the lock signal output. The
mask time is set by the capacitance of the capacitor connected between the CLD pin and GND.
The mask time (seconds) is 1.8  C (F)
When a 0.1F capacitor is connected, the mask time becomes about 180ms.
Set the enough mask time if it must be masked completely.
When there is no need for masking, the CLD pin must be left open.
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LV8112VB
11. Power Supply Stabilization
Since this IC adopts the method of the switching drive for the application that flows large output current, the power
supply line is relatively fluctuated. Therefore, the sufficient capacitors to stabilize the power supply voltage must be
connected between the VCC pin and GND as close to the pin as possible. The ground-side of the capacitors must be
connected to the GND2 pin that is GND of the output circuit block. If it is impossible to connect a capacitor
(electrolytic capacitor) near the pin, the ceramic capacitor of about 0.1F must be connected as close to the pin as
possible.
Since the power supply line is more fluctuated when the diodes are inserted in the power supply line to prevent IC
destruction due to the reverse connection of the power supply, choose even larger capacitors.
12. VREG Stabilization
To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1F or more.
The ground-side of the capacitor must be connected as close to the control block GND (GND pin) of the IC as
possible.
13. Error Amplifier
External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of
noise.
Also, these components must be placed as far as possible from the motor.
14. Metal of IC’s Backside
The heat radiation can be efficiently diffused by soldering the metal of IC’s backside to the printed circuit board.
15. SDCC (Speed Detection Current Control)
The SDCC function controls the current limiter value by sensing the motor speed.
When the rotation speed exceeds 95% of the target speed, this function decreases the current limiter value to 87.5%
and reduces the acceleration of the motor. Therefore, it stabilizes the phase lock pull-in and improves the variance of
the motor start-up time.
The SDCC function becomes as follows:
F/R = High or Open → Function ON
F/R = Low
→ Function OFF
Note: If the rotation direction of the motor does not match the selected state of SDCC, it is necessary to adapt by
reversing the polarity terminal of the Hall bias.
ORDERING INFORMATION
Device
LV8112VB-AH
Package
SSOP44K (275mil) EP
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
2000 / Tape & Reel
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