Ordering number : ENA1702D LV8729V Bi-CMOS IC PWM Constant-Current Control Stepper Motor Driver http://onsemi.com Overview The LV8729V is a PWM current-controlled microstep bipolar stepper motor driver. This driver can perform eight times of excitation of the second phase to 32W1-second phase and can drive simply by the CLK input. Function • Single-channel PWM current control stepper motor driver. • BiCDMOS process IC. • Output on-resistance (upper side : 0.35Ω ; lower side : 0.3Ω ; total of upper and lower : 0.65Ω ; Ta = 25°C, IO = 1.8A) • 2-phase, 1-2 phase, W1-2 phase, 2W1-2 phase, 4W1-2 phase,8W1-2 phase, 16W1-2 phase, 32W1-2 phase excitation are selectable. • Advance the excitation step with the only step signal input. • Available forward reverse control. • Over current protection circuit. • Thermal shutdown circuit. • Input pull down resistance • With reset pin and enable pin. SSOP44K (275mil) Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VM max VM , VM1 , VM2 36 V Maximum output current IO max Per 1ch 1.8 A Maximum logic input voltage VIN max ST , MD1 , MD2 , MD3 , OE , RST , FR , 6 V Maximum VREF input voltage VREF max 6 V Maximum MO input voltage VMO max 6 V Maximum DOWN input voltage VDOWN max 6 V Allowable power dissipation Pd max 3.85 W Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * * Specified circuit board : 90.0mm×90.0mm×1.6mm, glass epoxy 2-layer board, with backside mounting. Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time. Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information on page 21 of this data sheet. Semiconductor Components Industries, LLC, 2014 June, 2014 619114NK/42413NK 20121220-S00010 No.A1702-1/21 LV8729V Allowable Operating Ratings at Ta = 25°C Parameter Symbol Conditions Supply voltage range VM VM , VM1 , VM2 Logic input voltage VIN ST , MD1 , MD2 , MD3 , OE , RST , FR , STEP VREF input voltage range VREF Ratings Unit 9 to 32 V 0 to 5 V 0 to 3 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics at Ta = 25°C, VM = 24V, VREF = 1.5V Parameter Symbol Conditions Ratings min typ Unit max Standby mode current drain IMst ST = “L” , VM+VM1+VM2 70 100 μA Current drain IM ST = “H”, OE = “H”, no load 3.3 4.6 mA Thermal shutdown temperature TSD Design guarantee 180 200 °C Thermal hysteresis width ΔTSD Design guarantee Logic pin input current IINL ST , MD1 , MD2 , MD3 , OE , RST , FR , VM+VM1+VM2 150 °C 40 3 8 15 μA 30 50 70 μA STEP , VIN = 0.8V IINH ST , MD1 , MD2 , MD3 , OE , RST , FR , STEP , VIN = 5V Logic input voltage High VINH ST , MD1 , MD2 , MD3 , OE , RST , FR , Low VINL STEP Fch Cosc1 = 100pF Chopping frequency 2.0 5.0 V 0 0.8 V 130 kHz μA 70 100 OSC1 pin charge/discharge current Iosc1 7 10 13 Chopping oscillation circuit Vtup1 0.8 1 1.2 V threshold voltage Vtdown1 0.3 0.5 0.7 V μA VREF pin input voltage Iref VREF = 1.5V DOWN output residual voltagr VO1DOWN Idown = 1mA -0.5 40 100 mV MO pin residual voltage VO1MO Imo = 1mA 40 100 mV Hold current switching frequency Fdown Cosc2 = 1500pF 1.12 1.6 2.08 Hz Hold current switching frequency Vtup2 0.8 1 1.2 V threshold voltage Vtdown2 0.3 0.5 0.7 V 4.7 5 5.3 V 18 19 20 V Ω VREG1 output voltage Vreg1 VREG2 output voltage Vreg2 VM Output on-resistance Ronu IO = 1.8A, high-side ON resistance 0.35 0.455 Rond IO = 1.8A, low-side ON resistance 0.3 0.39 Ω IOleak VM = 36V 50 μA Output leakage current Diode forward voltage VD ID = -1.8A Current setting reference voltage VRF VREF = 1.5V, Current ratio 100% 0.285 1 1.4 V 0.3 0.315 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.A1702D-2/21 LV8729V Package Dimensions unit : mm (typ) SSOP44K (275mil) Exposed Pad CASE 940AF ISSUE A No.A1702D-3/21 LV8729V 1.00 SOLDERING FOOTPRINT* (Unit: mm) 7.00 (3.5) (4.7) 0.65 0.32 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GENERIC MARKING DIAGRAM* XXXXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data No.A1702D-4/21 LV8729V Pin Assignment VM 1 44 OUT1A NC 2 43 OUT1A VREG2 3 42 PGND1 NC 4 41 NC VREG1 5 40 NC ST 6 39 VM1 MD1 7 38 VM1 MD2 8 37 RF1 MD3 9 36 RF1 OE 10 35 OUT1B RST 11 NC 12 34 OUT1B LV8729V FR 13 33 OUT2A 32 OUT2A STP 14 31 RF2 OSC1 15 30 RF2 OSC2 16 29 VM2 NC 17 28 VM2 EMO 18 27 NC DOWN 19 26 NC MO 20 25 PGND2 VREF 21 24 OUT2B SGND 22 23 OUT2B Top view No.A1702D-5/21 LV8729V Pd max - Ta Allowable power dissipation, Pd max - W 5.0 4.0 3.85 3.0 (1):Exposed Die-Padsubstrate (2):Without Exposed Die-pad (1) (2) 2.70 2.00 2.0 1.40 1.0 0 —30 0 30 60 90 120 Ambient temperature, Ta - C Substrate Specifications (Substrate recommended for operation of LV8729V) Size : 90mm × 90mm × 1.6mm (two-layer substrate [2S0P]) Material : Glass epoxy Copper wiring density : L1 = 85% / L2 = 90% L1 : Copper wiring pattern diagram L2 : Copper wiring pattern diagram Cautions 1) The data for the case with the Exposed Die-Pad substrate mounted shows the values when 90% or more of the Exposed Die-Pad is wet. 2) For the set design, employ the derating design with sufficient margin. Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical stresses such as vibration, impact, and tension. Accordingly, the design must ensure these stresses to be as low or small as possible. The guideline for ordinary derating is shown below : (1)Maximum value 80% or less for the voltage rating (2)Maximum value 80% or less for the current rating (3)Maximum value 80% or less for the temperature rating 3) After the set design, be sure to verify the design with the actual product. Confirm the solder joint state and verify also the reliability of solder joint for the Exposed Die-Pad, etc. Any void or deterioration, if observed in the solder joint of these parts, causes deteriorated thermal conduction, possibly resulting in thermal destruction of IC. No.A1702D-6/21 SGND ISD TSD + Oscllator ST Output pre stage OSC2 OUT1B VM1 VM2 OUT2A + RF2 OSC1 Decay Mode setting circuit Current select circuit OUT2B MD1 MD2 MD3 FR STP RST OE Output control logic Output pre stage Current select circuit + OUT1A Output pre stage VREF Regulator 1 Regulator 2 RF1 Output pre stage VREG1 PGND2 PGND1 + - VM VREG2 EMO DOWN MO LV8729V Block Diagram No.A1702D-7/21 LV8729V Pin Functions Pin No. Pin Name Pin Functtion 7 MD1 Excitation mode switching pin 8 MD2 Excitation mode switching pin 9 MD3 Excitation mode switching pin 10 OE Output enable signal input pin 11 RST Reset signal input pin 13 FR Forward / Reverse signal input pin 14 STP Step clock pulse signal input pin Equivalent Circuit VREG1 GND 6 ST Chip enable pin. VREG1 GND 23, 24 OUT2B Channel 2 OUTB output pin. 25 PGND2 Channel 2 Power system ground 28, 29 VM2 Channel 2 motor power supply 30, 31 RF2 32, 33 OUT2A Channel 2 OUTA output pin. 34, 35 OUT1B Channel 1 OUTB output pin. 36, 37 RF1 Channel 1 current-sense resistor 38, 39 Channel 1 motor power supply pin. 42 VM1 PGND1 43, 44 OUT1A Channel 1 OUTA output pin. 38 39 28 29 connection pin. Channel 2 current-sense resistor connection pin. 34 35 23 24 43 44 32 33 connection pin. Channel 1 Power system ground 25 42 36 37 30 31 GND 21 VREF Constant-current control reference voltage input pin. VREG1 GND Continued on next page. No.A1702D-8/21 LV8729V Continued from preceding page. Pin No. 3 Pin Name VREG2 Pin Functtion Internal regulator capacitor connection pin. Equivalent Circuit VM GND 5 VREG1 Internal regulator capacitor connection pin. VM GND 18 EMO Over-current detection alarm output pin. 19 DOWN Holding current output pin. 20 MO Position detecting monitor pin. VREG1 GND 15 OSC1 Copping frequency setting capacitor connection pin. 16 OSC2 VREG5 Holding current detection time setting capacitor connection pin. GND No.A1702D-9/21 LV8729V Reference describing operation (1) Stand-by function When ST pin is at low levels, the IC enters stand-by mode, all logic is reset and output is turned OFF. When ST pin is at high levels, the stand-by mode is released. (2) STEP pin function Input Operating mode ST STP Low * Standby mode High Excitation step proceeds High Excitation step is kept (3) Input Timing TstepH TstepL STEP Tdh Tds (md1 step) (step md1) MD1 Tdh Tds (md2 step) (step md2) MD2 Tdh Tds (fr step) (step fr) FR TstepH/TstepL : Clock H/L pulse width (min 500ns) Tds : Data set-up time (min 500ns) Tdh : Data hold time (min 500ns) (4) Excitation setting method Set the excitation setting as shown in the following table by setting MD1 pin, MD2 pin and MD3 pin. Input Initial position Mode MD3 MD2 MD1 (Excitation) 1ch current 2ch current Low Low Low 2 phase 100% -100% 0% 0% Low Low High 1-2 phase 100% Low High Low W1-2 phase 100% Low High High 2W1-2 phase 100% 0% High Low Low 4W1-2 phase 100% 0% High Low High 8W1-2 phase 100% 0% High High Low 16W1-2 phase 100% 0% High High High 32W1-2 phase 100% 0% The initial position is also the default state at start-up and excitation position at counter-reset in each excitation mode. (5) Output current setting Output current is set shown below by the VREF pin (applied voltage) and a resistance value between RF1(2) pin and GND. IOUT = ( VREF / 5 ) / RF1 (2) resistance * The setting value above is a 100% output current in each excitation mode. (Example) When VREF = 1.1V and RF1 (2) resistance is 0.22Ω, the setting is shown below. IOUT = ( 1.1V / 5 ) / 0.22Ω = 1.0A No.A1702D-10/21 LV8729V (6) Output enable function When the OE pin is set Low, the output is forced OFF and goes to high impedance. However, the internal logic circuits are operating, so the excitation position proceeds when the STP is input. Therefore, when OE pin is returned to High, the output level conforms to the excitation position proceeded by the STP input. OE Power save mode STEP MONI 1ch output 0% 2ch output Output is high-impedance (7) Reset function When the RST pin is set Low, the output goes to initial mode and excitation position is fixed in the initial position for STP pin and FR pin input. MO pin outputs at low levels at the initial position. (Open drain connection) RST RESET STEP MONI 1ch output 0% 2ch output Initial state No.A1702D-11/21 LV8729V (8) Forward / reverse switching function FR Operating mode Low Clockwise (CW) High Counter-clockwise (CCW) FR CW mode CCW mode CW mode STEP Excitation position (1) (2) (3) (4) (5) (6) (5) (4) (3) (4) (5) 1ch output 2ch output The internal D/A converter proceeds by a bit on the rising edge of the step signal input to the STP pin. In addition, CW and CCW mode are switched by FR pin setting. In CW mode, the channel 2 current phase is delayed by 90° relative to the channel 1 current. In CCW mode, the channel 2 current phase is advanced by 90° relative to the channel 1 current. (9) EMO, DOWN, MO output pin The output pin is open -drain connection. When it becomes prescribed, it turns on, and each pin outputs the Low level. Pin state EMO DOWN MO Low At detection of over-current Holding current state Initial position OFF Normal state Normal state Non initial position (10) Chopping frequency setting function Chopping frequency is set as shown below by a capacitor between OSC1 pin and GND. Fcp = 1 / ( Cosc1 / 10 х 10-6 ) (Hz) (Example) When Cosc1 = 200pF, the chopping frequency is shown below. Fcp = 1 / ( 200 х 10-12 / 10 х 10-6 ) = 50(kHz) No.A1702D-12/21 LV8729V (11) Output current vector locus (one step is normalized to 90 degrees) Channel 1 current ratio (%) 100.0 66.7 33.3 0.0 0.0 33.3 66.7 100.0 Channel 2 current ratio (%) Current setting ratio in each excitation mode STEP θ0 θ1 θ2 θ3 θ4 θ5 θ6 θ7 θ8 θ9 θ10 θ11 θ12 θ13 θ14 θ15 θ16 θ17 θ18 θ19 θ20 θ21 θ22 θ23 θ24 θ25 32W1-2 phase(%) 1ch 2ch 100 0 100 1 100 2 100 4 100 5 100 6 100 7 100 9 100 10 99 11 99 12 99 13 99 15 99 16 99 17 98 18 98 20 98 21 98 22 97 23 97 24 97 25 96 27 96 28 96 29 95 30 16W1-2 phase(%) 1ch 2ch 100 0 100 2 100 5 100 7 100 10 99 12 99 15 99 17 98 20 98 22 97 24 96 27 96 29 8W1-2 phase(%) 1ch 2ch 100 0 100 5 100 10 99 15 98 20 97 24 96 29 4W1-2 phase(%) 1ch 2ch 100 0 100 10 98 20 96 29 2W1-2 phase (%) 1ch 2ch 100 0 98 W1-2 phase (%) 1ch 2ch 100 0 1-2 phase (%) 1ch 2ch 100 0 2 phase (%) 1ch 2ch 20 Continued on next page. No.A1702D-13/21 LV8729V Continued from preceding page. STEP θ26 θ27 θ28 θ29 θ30 θ31 θ32 θ33 θ34 θ35 θ36 θ37 θ38 θ39 θ40 θ41 θ42 θ43 θ44 θ45 θ46 θ47 θ48 θ49 θ50 θ51 θ52 θ53 θ54 θ55 θ56 θ57 θ58 θ59 θ60 θ61 θ62 θ63 θ64 θ65 θ66 θ67 θ68 θ69 θ70 θ71 θ72 θ73 θ74 θ75 θ76 θ77 θ78 θ79 θ80 θ81 θ82 θ83 θ84 θ85 θ86 θ87 θ88 θ89 θ90 32W1-2 phase 1ch 2ch 95 31 95 33 94 34 94 35 93 36 93 37 92 38 92 39 91 41 91 42 90 43 90 44 89 45 89 46 88 47 88 48 87 49 86 50 86 51 85 52 84 53 84 55 83 56 82 57 82 58 81 59 80 60 80 61 79 62 78 62 77 63 77 64 76 65 75 66 74 67 73 68 72 69 72 70 71 71 70 72 69 72 68 73 67 74 66 75 65 76 64 77 63 77 62 78 62 79 61 80 60 80 59 81 58 82 57 82 56 83 55 84 53 84 52 85 51 86 50 86 49 87 48 88 47 88 46 89 45 89 16W1-2 phase 1ch 2ch 95 31 94 34 93 36 92 38 91 41 90 43 89 45 88 47 87 49 86 51 84 53 83 56 82 58 80 60 79 62 77 63 76 65 74 67 72 69 71 71 69 72 67 74 65 76 63 77 62 79 60 80 58 82 56 83 53 84 51 86 49 87 47 88 45 89 8W1-2 phase 1ch 2ch 94 34 92 38 90 43 88 47 86 51 83 56 80 60 77 63 74 67 71 71 67 74 63 77 60 80 56 83 51 86 47 88 4W1-2 phase 1ch 2ch 2W1-2 phase 1ch 2ch 92 38 92 38 88 47 83 56 83 56 77 63 71 71 71 71 63 77 56 83 56 83 47 88 W1-2 phase (%) 1ch 2ch 92 38 71 71 1-2 phase (%) 1ch 2ch 2 phase (%) 1ch 2ch 71 100 71 100 Continued on next page. No.A1702D-14/21 LV8729V Continued from preceding page. STEP θ91 θ92 θ93 θ94 θ95 θ96 θ97 θ98 θ99 θ100 θ101 θ102 θ103 θ104 θ105 θ106 θ107 θ108 θ109 θ110 θ111 θ112 θ113 θ114 θ115 θ116 θ117 θ118 θ119 θ120 θ121 θ122 θ123 θ124 θ125 θ126 θ127 θ128 32W1-2 phase 1ch 2ch 44 90 43 90 42 91 41 91 39 92 38 92 37 93 36 93 35 94 34 94 33 95 31 95 30 95 29 96 28 96 27 96 25 97 24 97 23 97 22 98 21 98 20 98 18 98 17 99 16 99 15 99 13 99 12 99 11 99 10 100 9 100 7 100 6 100 5 100 4 100 2 100 1 100 0 100 16W1-2 phase 1ch 2ch 43 90 41 91 38 92 36 93 34 94 31 95 29 96 27 96 24 97 22 98 20 98 17 99 15 99 12 99 10 100 7 100 5 100 2 100 0 100 8W1-2 phase 1ch 2ch 43 90 38 92 34 94 29 96 24 97 20 98 15 99 10 100 5 100 0 100 4W1-2 phase 1ch 2ch 2W1-2 phase 1ch 2ch 38 92 38 92 29 96 20 98 20 98 10 100 0 100 0 100 W1-2 phase (%) 1ch 2ch 38 92 0 100 1-2 phase (%) 1ch 2ch 0 2 phase (%) 1ch 2ch 100 No.A1702D-15/21 LV8729V (12) Current wave example in each excitation mode ( 2 phase, 1-2 phase, 4W1-2 phase, 32W1-2 phase) 2-phase excitation (CW mode) STP MO (%) 100 l1 0 -100 (%) 100 I2 0 -100 1-2 phase excitation (CW mode) STP MO (%) 100 I1 0 -100 (%) 100 I2 0 -100 No.A1702D-16/21 LV8729V 4W1-2 phase excitation ( CW mode ) STP MO (%) 100 50 I1 0 -50 -100 (%) 100 50 I2 0 -50 -100 32W1-2 phase excitation ( CW mode ) STP MO (%) 100 50 I1 0 -50 -100 (%) 100 50 I2 0 -50 -100 No.A1702D-17/21 LV8729V (13) Current control operation ( Sine-wave increasing direction ) STP Setting current Setting current Coil current Blanking Time fchop Current mode CHARGE SLOW FAST CHARGE SLOW FAST ( Sine-wave decreasing direction ) STP Setting current Coil current Setting current Blanking Time fchop Current mode CHARGE SLOW FAST Blanking Time FAST CHARGE SLOW Each of current modes operates with the follow sequence. · The IC enters CHARGE mode at a rising edge of the chopping oscillation. ( A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1μs, regardless of the current value of the coil current (ICOIL) and set current (IREF)). · In a period of Blanking Time, the coil current (ICOIL) and the setting current (IREF) are compared. If an ICOIL < IREF state exists during the charge period: The IC operates in CHARGE mode until ICOIL ≥ IREF. After that, it switches to SLOW DECAY mode and then switches to FAST DECAY mode in the last approximately 1μs of the period. If no ICOIL < IREF state exists during the charge period: The IC switches to FAST DECAY mode and the coil current is attenuated with the FAST DECAY operation until the end of a chopping period. The above operation is repeated. Normally, in the sine wave increasing direction the IC operates in SLOW (+ FAST) DECAY mode, and in the sine wave decresing direction the IC operates in FAST DECAY mode until the current is attenuated and reaches the set value and the IC operates in SLOW (+ FAST) DECAY mode. No.A1702D-18/21 LV8729V (14) Output short-circuit protection circuit Built-in output short-circuit protection circuit makes output to enter in stand-by mode. This function prevents the IC from damaging when the output shorts circuit by a voltage short or a ground short, etc. When output short state is detected, short-circuit detection circuit state the operating and output is once turned OFF. Subsequently, the output is turned ON again after the timer latch period ( typ. 256μs ). If the output remains in the short-circuit state, turn OFF the output, fix the output to the wait mode, and turn ON the EMO output. When output is fixed in stand-by mode by output short protection circuit, output is released the latch by setting ST = “L”. (15) Open-drain pin for switching holding current The output pin is an open-drain connection. This pin is turned ON when no rising edge of STP between the input signals while a period determined by a capacitor between OSC2 and GND, and outputs at low levels. The open-drain output in once turned ON, is turned OFF at the next rising edge of STP. Holding current switching time ( Tdown ) is set as shown below by a capacitor between OSC2 pin and GND. Tdown = Cosc2 х 0.4 х 109 (s) (Example) When Cosc2 = 1500pF, the holding current switching time is shown below. Tdown = 1500pF х 0.4 х 109 = 0.6 (s) (16) Thermal shutdown function The thermal shutdown circuit is incorporated and the output is turned off when junction temperature Tj exceeds 180°C and the abnormal state warning output is turned on. As the temperature falls by hysteresis, the output turned on again (automatic restoration). The thermal shutdown circuit does not guarantee the protection of the final product because it operates when the temperature exceed the junction temperature of Tjmax=150°C. TSD = 180°C (typ) ∆TSD = 40°C (typ) No.A1702D-19/21 LV8729V Application Circuit Example - + Motor power supply OUT1A 44 2 NC OUT1A 43 3 VREG2 PGND1 42 4 NC NC 41 5 VREG1 NC 40 6 ST VM1 39 7 MD1 VM1 38 8 MD2 RF1 37 9 MD3 RF1 36 10 OE 11 RST 12 NC 13 FR 180pF Short-circuit state detection monitor - + Current setting reference voltage LV8729V Logic input 1 VM OUT1B 35 OUT1B 34 OUT2A 33 OUT2A 32 14 STP RF2 31 15 OSC1 RF2 30 16 OSC2 VM2 29 17 NC VM2 28 18 EMO NC 27 19 DOWN NC 26 20 MO PGND2 25 21 VREF OUT2B 24 22 SGND OUT2B 23 M The above sample application circuit is set to the following conditions: · Output enable function fixed to the output state ( OE = “H” ) · Reset function fixed to the output state ( RST = “H” ) · Chopping frequency : 55.5kHz ( Cosc1 = 180pF ) The set current value is as follows : IOUT = ( Current setting reference voltage / 5 ) / 0.22Ω No.A1702D-20/21 LV8729V ORDERING INFORMATION LV8729V-TLM-H Device Package SSOP44K (275mil) (Pb-Free / Halogen Free) LV8729V-MPB-H SSOP44K (275mil) (Pb-Free / Halogen Free) Shipping (Qty / Packing) 2000 / Tape & Reel 30 / Fan-Fold ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1702-21/21