A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Features and Benefits Description • Automotive AEC-Q100 qualified • Operating voltage range: 2.5 to 5.5 V •UVLO stop threshold: 2.25 V (max) • Adjustable switching frequency (fOSC): 0.25 to 2.45 MHz • Synchronizes to external clock: 1.2× to 1.5× fOSC (typ) • Internal 70 mΩ high-side switching MOSFET • Internal 55 mΩ low-side switching MOSFET • Capable of at least 2.0 A steady-state output current • Sleep mode supply current less than 3 μA •Adjustable output voltage as low as 0.8 V with ±1% accuracy from –40°C to 125°C • Soft start time externally set via the SS pin • Pre-biased startup capable • Externally adjustable compensation The A8650 is an adjustable frequency, high output current, PWM regulator that integrates a high-side, P-channel MOSFET and a low-side, N-channel MOSFET. The A8650 incorporates current-mode control to provide simple compensation, excellent loop stability, and fast transient response. The A8650 utilizes external compensation to accommodate a wide range of power components to optimize transient response without sacrificing stability. The A8650 regulates input voltages from 2.5 to 5.5 V, down to output voltages as low as 0.8 V, and is able to supply at least 2.0 A of load current. A8650 features include an externally adjustable switching frequency, an externally set soft start time to minimize inrush currents, an EN/SYNC input to either enable VOUT and/or synchronize the PWM switching frequency, and a Power OK (POK) output to indicate when VOUT is within regulation. The sleep mode current of the A8650 control circuitry is less than 3 μA. Protection features include VIN undervoltage lockout Continued on the next page… Packages: 10-pin MSOP with exposed thermal pad (suffix LY) 10-pin DFN with exposed thermal pad (suffix EJ) Continued on the next page… Applications: •GPS/Infotainment • Automobile Audio • Home Audio •Network and Telecom Not to scale Typical Application Diagram VIN 10 CIN1 3.3 µF 1206 CIN2 0.1 µF 0805 CIN3 10 nF 0603 9 2 EN/SYNC CSS 10 nF RFSET 10.7 kΩ 3 8 5 6 CP 22 pF VIN SW A8650 GND PGND FB 1 7 LO 1.0 µH COMP CO1 10 µF 1206 RFB1 9.09 kΩ RFB2 7.15 kΩ EN/SYNC SS FSET VOUT CO2 10 µF 1206 3.3V RPU 10 kΩ POK 4 POK RZ 6.65 kΩ CZ 1.5 nF Typical application schematic, configured for VIN = 5 V , VOUT = 1.8 V, IOUT = 2.0 A at 2 MHz A8650-DS, Rev. 8 CO3 0.1 µF 0805 CO4 10 nF 0603 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Features and Benefits (continued) Description (continued) • Stable with ceramic output capacitors • Enable input, and Power OK (POK) output • Cycle-by-cycle current limiting (OCP) • Hiccup mode short circuit protection (HIC) • Overvoltage protection (OVP) • Overtemperature protection (TSD) • Open circuit and adjacent pin short circuit tolerant • Short to ground tolerant at every pin (UVLO), cycle-by-cycle overcurrent protection (OCP), hiccup mode short circuit protection (HIC), overvoltage protection (OVP), and thermal shutdown (TSD). In addition, the A8650 provides open circuit, adjacent pin short circuit, and short to ground protection at every pin to satisfy the most demanding automotive applications. The A8650 is available in both 10-pin MSOP and DFN packages with an exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number Operating Ambient Temperature Range TA, (°C) Package Packing Leadframe Plating A8650KLYTR-T –40 to 125 10-pin MSOP with exposed thermal pad 4000 pieces per 13-in. reel 100% matte tin A8650KEJTR-T -40 to 125 10-pin DFN with exposed thermal pad 1500 pieces per 7-in reel 100% matte tin Absolute Maximum Ratings1 Characteristic VIN Pin to GND SW to GND2 Symbol Notes Rating VIN VSW Continuous t < 50 ns All other pins Unit –0.3 to 6 V –0.3 to VIN + 0.3 V –1.0, VIN + 2.0 V –0.3 to 6.0 V Operating Ambient Temperature TA –40 to 125 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature K temperature range 1Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. 2SW has internal clamp diodes to GND and V . Applications that forward bias these diodes should take care not to exceed the IC package power dissipation limits. IN Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance (LY) RθJA On 4-layer PCB based on JEDEC standard 48 ºC/W Package Thermal Resistance (EJ) RθJA On 4-layer PCB based on JEDEC standard 45 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Table of Contents Specifications 2 Functional Block Diagram 4 5 Pin-out Diagram and Terminal List Characteristic Performance Functional Description Overview Reference Voltage Oscillator/Switching Frequency Transconductance Error Amplifier Slope Compensation Sleep Mode Enable/Synchronization (EN/SYNC) Input Power MOSFETs Pulse Width Modulation (PWM) Current Sense Amplifier Soft Start (Startup) and Inrush Current Control Pre-Biased Startup Power OK (POK) Output 9 11 11 11 11 11 11 12 12 12 13 13 13 13 14 Protection Features Undervoltage Lockout (UVLO) Thermal Shutdown (TSD) Overvoltage Protection (OVP) Cycle-by-Cycle Overcurrent Protection (OCP) Output Short Circuit (Hiccup Mode) Protection Application Information Design and Component Selection Setting the Output Voltage (VOUT, RFB1, RFB2) Base PWM Switching Frequency (RFSET) Output Inductor (LO) Output Capacitors Input Capacitors Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ , CZ , CP ) A Generalized Tuning Procedure Power Dissipation and Thermal Calculations PCB Component Placement and Routing Package Outline Drawing 14 14 14 14 14 15 18 18 18 18 19 20 21 21 22 24 25 27 29 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Functional Block Diagram VIN Current Sense CURRENT fOSC Oscillator FSET PWM_CLK fSYNC ADJ EN/SYNC > 1.2 x fOSC Slope Compensation Reset Dominant PWM Comparator Regulators - ON POR + 10 ns - EN/SYNC Sleep 100 kΩ VIN 0.8V VSSOFFS 200 mV 150 nA + 0.8 V (max) POR Error Amplifier + + - FB EN/SYNC + 1.65 V (typ) 1.25 V (typ) Digital Delay - Q R Q SW VIN 55 mΩ Off PGND CLAMP_ACTIVE COMP POR EN 1.5 kΩ OFF TSD Protection CURRENT CURRENT (OCP) FAULT EN / CLR LATCHED FAULT = 1, if: VIN (UVLO) EN = 0 or FB EN_HICCUP UVLO = 1 CLAMP_ACTIVE OCP COUNT EN HICCUP HIC RST (100 mV) HICCUP HICCUP HICCUP = 1 if: FB < 625 mV and COMP ≈ 1.25 V and 7 OCP events 2 kΩ 10 µA 20 µA POK OFF + 115% x VREF 111% x VREF FB 92% x VREF 88% x VREF OFF UV / OV OV FBOK POK Comparator + 125 ns OVP Comparator - SS Clamp 1.25 V S tOFF(MIN) VPWMOFFS 350 mV VREF 70 mΩ Off GND FBOK VIN Non-Overlap ADJ Falling Delay 7 PWM Cycles PAD Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Pin-out Diagrams and Terminal List Table 10 VIN SW 1 EN/SYNC 3 SW 1 10 VIN PGND 2 9 GND EN/SYNC 3 8 SS POK 4 7 FB FSET 5 6 COMP 9 GND PGND 2 PAD POK 4 FSET 5 8 SS 7 FB 6 COMP Package LY, 10-Pin MSOP Pin-out Diagram PAD Package EJ, 10-Pin DFN Pin-out Diagram Terminal List Table Number Name Function The drain of both the internal high- and low-side MOSFETs. The output inductor (LO) should be connected to this pin. LO should be placed as close as possible to this pin and connected with relatively wide traces. 1 SW 2 PGND 3 EN/SYNC 4 POK Power OK output signal. This pin is an open drain output that transitions from low impedance to high impedance when the output is within the final regulation voltage. 5 FSET Frequency setting pin. A resistor, RFSET , from this pin to GND sets the PWM switching frequency. See figure 10 and/or equation 2 to determine the value of RFSET . 6 COMP Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from this pin to GND for loop compensation. See the Design and Component Selection sections of this datasheet for further details. 7 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output node, VOUT, to this pin to program the output voltage. 8 SS Soft start pin. Connect a capacitor, CSS , from this pin to GND to set the soft start time. This capacitor also determines the hiccup period during overcurrent. 9 GND Ground connection. 10 VIN Power input for the control circuits and the source of the internal high-side P-channel MOSFET. Connect this pin to a power supply of 2.5 to 5.5 V. A high quality ceramic capacitor should be placed very close to this pin. 0 PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad. Power ground connection. Enable and synchronization input. This pin is a logic input that turns the regulator on or off: set this pin to logic high to turn the regulator on or set this pin to logic low to turn the regulator off. This pin also functions as a synchronization input to allow the PWM frequency to be set by an external clock. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 ELECTRICAL CHARACTERISTICS Valid at –40°C ≤ TA = TJ ≤ 125°C, VIN = 5 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit Input Voltage Specifications Operating Input Voltage Range VIN 2.5 − 5.5 V VIN UVLO Start Threshold VINUVSTART VIN rising 2.00 2.22 2.45 V VIN UVLO Stop Threshold VINUVSTOP VIN falling 1.80 2.02 2.25 V VIN UVLO Hysteresis VINUVHYS − 200 − mV VEN/SYNC = 5 V, VFB = 1.0 V, no PWM switching − 2 4 mA VIN = VSW = 5 V, VEN/SYNC ≤ 0.4 V − 1 3 μA 792 800 808 mV – –150 –300 nA Input Currents Input Quiescent Current Input Sleep Supply Current IQ IQSLEEP Reference Voltage Reference (Feedback) Voltage VREF 2.5 < VIN < 5.5 V, VFB = VCOMP Error Amplifier Feedback Input Bias Current1 Open Loop Voltage Gain2 Transconductance Source Current Sink Current Maximum Output Voltage COMP Pull Down Resistance IFB VCOMP = 0.7 V, VFB regulated so that ICOMP = 0 A AVOL gm ICOMP = 0 μA, VSS > 500 mV − 65 − dB 550 750 950 μA/V 0 V < VSS < 500 mV – 250 – μA/V IEA(SRC) VFB < 0.8 V, VCOMP = 0.7 V − –50 − μA IEA(SINK) VFB > 0.8 V, VCOMP = 0.7 V μA − +50 − 1.00 1.25 1.50 V FAULT = 1, HICCUP = 1, or EN/SYNC = low − 1.5 − kΩ VCOMP for 0% duty cycle − 350 − mV − 65 105 ns − 50 100 ns VEAO(MAX) RCOMP Pulse Width Modulation (PWM) PWM Ramp Offset VPWMOFFS High-Side MOSFET Minimum Controllable On-Time tON(MIN) Low-Side MOSFET Minimum On‑Time tOFF(MIN) Gate Driver Non-Overlap Time2 COMP to SW Current Gain Slope Compensation2 Does not include total gate driver non-overlap time, 2 x tNO tNO − 15 − ns gmPOWER − 4.5 − A/V fsw = 2.0 MHz 1.65 2.35 2.85 A/μs fsw = 0.25 MHz 0.21 0.29 0.36 A/μs SE MOSFET Parameters High-Side MOSFET On-Resistance3 SW Node Rise Time2 High-Side MOSFET Leakage4 RDS(ON)HS tR(SW) ILKG(HS) TA = 25°C, IDS = 100 mA − 70 80 mΩ IDS = 100 mA − − 145 mΩ VIN = 5 V − 12 − ns VEN/SYNC ≤ 0.4 V, VSW = 0 V, VIN = 5 V, –40˚C < TA = TJ < 85˚C − − 4 μA TA = TJ = 125˚C − 5 25 μA Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK ELECTRICAL CHARACTERISTICS (Continued) Valid at –40°C ≤ TA = TJ ≤ 125°C, VIN = 5 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit TA = 25°C, IDS = 100 mA − 55 65 mΩ IDS = 100 mA − − 115 mΩ VEN/SYNC ≤ 0.4 V, VSW = 5 V, –40˚C < TA = TJ < 85˚C − − 1 μA VEN/SYNC ≤ 0.4 V, VSW = 5 V, TA = TJ = 125˚C − 4 10 μA RFSET = 8.45 kΩ 2.20 2.45 2.70 MHz RFSET = 23.2 kΩ 0.90 1.00 1.10 MHz RFSET = 100 kΩ − 250 − kHz 1.2 x fOSC − 1.5 x fOSC – − − 2.9 MHz MOSFET Parameters (continued) Low-Side MOSFET On-Resistance3 Low-Side MOSFET Leakage4 RDS(on)LS ILKG(LS) Oscillator Frequency Oscillator Frequency fOSC Synchronization Timing Synchronization Frequency Range Synchronized PWM Frequency fSW(MULT) Relative to fOSC(typ) fSYNC Synchronization Input Duty Cycle DSYNC Synchronization Input Pulse Width tPWSYNC VIN = 3.3 V, VEN/SYNC = 3.3 V pulse input − − 80 % 200 − − ns Synchronization Input Edge Rise Time2 trSYNC − 10 15 ns Synchronization Input Edge Fall Time2 tfSYNC − 10 15 ns Enable/Synchronization Input EN/SYNC High Threshold VEN/SYNC(H) VEN/SYNC rising − − 1.8 V EN/SYNC Low Threshold VEN/SYNC(L) VEN/SYNC falling 0.8 − − V EN/SYNC Hysteresis VEN/SYNC VEN/SYNC(H) – VEN/SYNC(L) − 200 − mV VEN/SYNC transitioning low − 32 − PWM cycles 50 100 − kΩ − 10 − ns EN/SYNC Digital Delay (HYS) tSLEEP EN/SYNC Input Resistance REN/SYNC EN/SYNC Pulse Rejection tEN/SYNCR VIN = 3.3 V, VEN/SYNC = 1.3 V pulse input Overcurrent Protection (OCP) and Hiccup Mode ILIM(5%) Duty Cycle = 5% 3.5 4.1 4.7 A ILIM(90%) Duty Cycle = 90% 2.3 3.1 4.2 A Hiccup Disable Threshold HICDIS VFB rising − 750 − mV Hiccup Enable Threshold HICEN VFB falling − 625 − mV Hiccup enabled, OCP pulses − 7 − counts Pulse-by-Pulse Current Limit OCP / HICCUP Count Limit OCPLIMIT Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 ELECTRICAL CHARACTERISTICS (Continued) Valid at –40°C ≤ TA = TJ ≤ 125°C, VIN = 5 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 120 200 270 mV Soft Start (SS Pin) SS Offset Voltage VSSOFFS VSS rising due to ISSSU SS Fault/Hiccup Reset Voltage VSS_RESET VSS falling due to ISSHIC − 100 120 mV −10 –20 −30 μA VSS = 0.5 V, HICCUP = 1 5 10 20 μA FAULT = 1 or EN/SYNC = low − 2 − KΩ tSS(DELAY) CSS = 22 nF − 175 − μs tSS CSS = 22 nF − 880 − μs VFB = 0 V − fSW / 3 − − VFB ≥ 600 mV − fSW − − SS Startup (Source) Current ISSSU VSS = 1 V, HICCUP = FAULT = 0 SS Hiccup (Sink) Current ISSHIC SS Input Resistance SS to VOUT Delay Time VOUT Soft Start Ramp Time SS Switching Frequency RSS fSW(SS) Power OK (POK Pin) Output POK Output Voltage POK Undervoltage Threshold POK Undervoltage Hysteresis POK Overvoltage Threshold POK Overvoltage Hysteresis VPOK POKUV IPOK = 4 mA − − 0.4 V VFB rising, as a percent of VREF 89 92 95 % POKUVHYS VFB falling, as a percent of VREF POKOV VFB rising, as a percent of VREF POKOVHYS VFB falling, as a percent of VREF − 4 − % 112 115 118 % − 4 − % POK Digital Delay POKDLY VFB rising only − 7 − PWM cycles POK Leakage IPOK(LKG) VPOK = 5 V, VCOMP ≤ 0.3 V − − 1 μA Thermal Shutdown Protection (TSD) Thermal Shutdown Threshold2 Thermal Shutdown Hysteresis2 TTSD Temperature rising 155 170 185 ºC TTSDHYS Temperature falling − 20 − ºC 1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2Ensured by design and characterization, not production tested. 3T = T = 25˚C ensured by design and characterization, not production tested. A J 4T = T = 85˚C ensured by design and characterization, not production tested. A J Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Characteristic Performance Reference Voltage versus Temperature 2.75 806 2.50 804 2.25 802 2.00 fOSC (MHz) V REF (mV) 808 800 798 f OSC = 2.44 MHz 1.75 f OSC = 1.00 MHz 1.50 796 1.25 794 1.00 792 Switching Frequency versus Temperature 0.75 -50 -25 0 25 50 75 100 125 150 -50 -25 0 Temperature (°C) 125 150 Threshold (% of VFB) 110 2.20 VIN (V) 100 115 Stop, VINUVSTOP 2.30 2.10 2.00 1.90 1.80 POKOV, VFB rising 105 POKOV, VFB falling 100 POKUV, VFB rising POKUV, VFB falling 95 90 85 1.70 80 -50 4.5 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Cycle-by-Cycle Current Limit at t ON(MIN) versus Temperature Error Amplifier Transconductance versus Temperature 950 4.4 150 900 4.3 850 4.2 4.1 EA gm (µA/V) ILIM (5%) (A) 75 POKOV and POKUV Thresholds versus Temperature 120 Start, VINUVSTART 2.40 50 Temperature (°C) VIN UVLO Start and Stop Thresholds versus Temperature 2.50 25 4.0 3.9 3.8 800 750 700 650 3.7 600 3.6 3.5 550 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 EN/SYNC High and Low Thresholds versus Temperature 1.8 25 VEN/SYNC(L) 1.7 23 VEN/SYNC(H) SS Pin Current (µA) 1.6 EN/SYNC (V) 1.5 1.4 1.3 1.2 1.1 -25 0 25 50 75 100 125 Hiccup, ISSHIC 13 10 150 -50 -25 0 25 50 75 100 Temperature (°C) POK Low Output Voltage versus Temperature Hiccup Enable and Disable Thresholds versus Temperature 850 VPOK at 4 mA 0.30 125 825 HICEN, VFB falling 800 HICDIS, VFB rising 150 775 0.25 Threshold (mV) (V) Startup, ISSSU 15 Temperature (°C) 0.35 V POK 18 5 -50 0.20 0.15 0.10 750 725 700 675 650 625 600 0.05 575 0.00 550 -50 4.0 -25 0 25 50 75 100 125 150 Temperature (°C) -50 25 50 75 Temperature (°C) VIN Sleep Current versus Temperature High- and Low-Side MOSFETs Leakage versus Temperature 20.0 3.5 17.5 3.0 15.0 Leakage Current (µA) IQSLEEP (µA) 20 8 1.0 0.40 Soft Start Startup and Hiccup Currents versus Temperature 2.5 2.0 1.5 1.0 0.5 -25 0 100 125 150 High-Side, ILKG(HS) Low-Side, ILKG(LS) 12.5 10.0 7.5 5.0 2.5 0.0 0.0 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Functional Description Overview The A8650 is a synchronous PWM regulator that incorporates all the control and protection circuitry necessary to satisfy a wide range of low voltage applications. The A8650 employs current mode control to provide fast transient response, simple compensation, and excellent stability. The features of the A8650 include a ±1% precision reference, an adjustable switching frequency, a transconductance error amplifier, an enable/synchronization input, integrated power MOSFETs, adjustable soft-start time, pre-bias startup capability, low current sleep mode, and a Power OK (POK) output. The protection features of the A8650 include undervoltage lockout (UVLO), cycle-by-cycle overcurrent protection (OCP), hiccup mode short circuit protection (HIC), overvoltage protection (OVP), and thermal shutdown (TSD). In addition, the A8650 provides open circuit, adjacent pin short circuit, and pin-toground short circuit protection. Reference Voltage The A8650 incorporates an internal reference that allows output voltages as low as 0.8 V. The accuracy of the internal reference is ±1% across the entire operating temperature range. The output voltage of the regulator is adjusted by connecting a resistor divider (RFB1 and RFB2 in the typical application schematic) from VOUT to the FB pin of the A8650. Oscillator/Switching Frequency The base PWM switching frequency, fOSC , of the A8650 is adjustable from 250 kHz to 2.45 MHz and has an accuracy of ±12% across the operating temperature range. The base frequency is used to set the device switching frequency, fSW , which can also be further increased by the optional synchronization function (described later in the section on EN/SYNC operation) . Connecting a resistor from the FSET pin to GND, as shown in the typical application schematic, sets the base switching frequency. An FSET resistor with ±1% tolerance is recommended. A graph of fOSC versus RFSET , and an equation to calculate RFSET , are provided in the Component Selection section of this datasheet. Transconductance Error Amplifier The primary function of the transconductance error amplifier is to regulate the A8650 output voltage. The error amplifier is shown in figure 1 as a device with three inputs, two positive and one negative. The negative input simply is connected to the FB pin and is used to sense the feedback voltage for regulation. The two positive inputs are connected to the soft start and reference voltages, and the error amplifier performs an analog OR selection between them. It regulates to either the soft start pin voltage minus the Soft Start Offset (200 mV (typ)) or the A8650 internal reference, whichever is lower. To stabilize the regulator, a series RC compensation network (RZ CZ) must be connected from the error amplifier output (COMP pin) to GND as shown in the typical application schematic. In most applications, an additional, low value capacitor (CP) should be connected in parallel with the RZ CZ compensation network to roll-off the loop gain at higher frequencies. However, if the CP capacitor is too large, the phase margin of the regulator may be reduced. If the regulator is disabled or a fault occurs, the COMP pin is immediately pulled to GND via an internal 1.5 kΩ pull-down and PWM switching is inhibited. Slope Compensation The A8650 incorporates internal slope compensation to allow PWM duty cycles near or above 50% to accommodate a wide range of input/output voltages, switching frequencies, and inductor values. As shown in the functional block diagram, the slope compensation signal is added to the sum of the current sense and PWM Ramp Offset (VPWMOFFS). The amount of slope compensation is scaled directly with the base switching frequency (fOSC , set by RFSET). However, the amount of slope compensation does VSSOFFS 200 mV SS Pin + + - VREF 800 mV Error Amplifier COMP Pin FB Pin Figure 1. A8650 Error Amplifier Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK not change when the synchronization function is used to alter the switching frequency. Sleep Mode If the voltage at the EN/SYNC pin is low for more than 32 PWM clock cycles, the A8650 discharges the soft start capacitor (via a 2 kΩ pulldown) until VSS ≈ 100 mV. At that time the A8650 will enter sleep mode and draw less than IQSLEEP (3 μA (max)) from VIN . However, the total current drawn by the VIN pin will be the sum of the current drawn by the control circuitry plus any leakage due to the high- and low-side MOSFETs ( ILKG(HS), and ILKG(LS) ). Enable/Synchronization (EN/SYNC) Input The enable/synchronization (EN/SYNC) input provides three functions: enabling/disabling the A8650 with system control, enabling/disabling the A8650 automatically, and synchronizing the output PWM frequency synchronization to an external clock signal input. When EN/SYNC is being used as a system controlled enabling/ disabling logic input, when EN/SYNC is kept high, the A8650 turns on and, provided there are no fault conditions, VOUT will ramp to its final voltage in a time set by the soft start capacitor (CSS ). When EN/SYNC is brought low for more than 32 PWM clock cycles (see figure 2) the voltage at the soft start pin is discharged by a 2 kΩ pulldown, and VSS will decay quickly starting from the input voltage level. When VSS drops below ≈ 100 mV, the A8650 will enter sleep mode and draw less than 3 µA from the input. A timing diagram showing startup and shutdown using EN/SYNC is shown in figure 8. The short delay (the 32 PWM clock cycles between when EN/SYNC transitions to low and when PWM switching stops) is necessary because the enable circuitry must distinguish between the relatively constant enabling/ disabling function logic levels and the longest allowed pulses generated when the EN/SYNC frequency synchronization function also is being used. When used in the frequency synchronization function, EN/SYNC accepts an external clock to scale the PWM switching frequency (fSW) from 1.2× to 1.5× above the base frequency (fOSC ) set by the RFSET resistor. The applied clock pulses must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the Electrical Characteristics table in this datasheet. Note that when EN/SYNC is used as a synchronization input, soft start still occurs at the base frequency (fOSC ) and synchronization to the external clock occurs only after soft start is complete (when VFB > POKUV). Finally, when used to automatically enable the A8650, the EN/SYNC input pin is connected to VIN via a resistor, as shown in figure 3. The series resistance is recommended to prevent large VIN capacitors from discharging into the EN/SYNC pin at powerdown. Power MOSFETs The A8650 includes a 70 mΩ, high-side P-channel MOSFET capable of delivering up to 4.1 A at 5% duty cycle. The A8650 also includes a 55 mΩ, low-side N-channel MOSFET to provide synchronous rectification. The low-side MOSFET continues to conduct when the inductor current crosses zero to maintain constant conduction mode (CCM). This helps to minimize EMI/EMC for noise sensitive VEN/SYNC VCOMP VOUT 32 PWM cycles VSS VSS = 100 mV Sleep mode Figure 2. PWM switching stops 32 PWM cycles after EN/SYNC transitions low, and sleep mode begins when VSS decays to VSS_RESET (100 mV) VIN 1 kΩ EN/SYNC PIN Figure 3. External circuit for automatically enabling the A8650 from VIN Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK applications by eliminating the SW output high-frequency ringing associated with discontinuous conduction mode (DCM). When a fault occurs or the A8650 is disabled, the SW pin becomes high impedance by turning off both the upper and lower MOSFETs. Pulse Width Modulation (PWM) A high-speed PWM comparator, capable of pulse widths less than 105 ns, is included in the A8650. The inverting input of the comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation, and the PWM Ramp Offset ( VPWMOFFS ). At the beginning of each PWM cycle, the PWM_CLK signal sets the PWM flip flop and the high-side MOSFET is turned on. When the summation of the current sense signal, the slope compensation, and the DC PWM Ramp Offset rises above the error amplifier voltage, the comparator resets the PWM flip flop and the high-side MOSFET is turned off. After a short delay to prevent cross-conduction (tNO), the low-side MOSFET is turned on. The PWM flip flop is reset dominant so, if the output voltage of the error amplifier drops below the PWM Ramp Offset, then PWM 0% duty cycle (that is, pulse skipping) operation is achieved. Current Sense Amplifier A high-bandwidth current sense amplifier monitors the current in the high-side MOSFET. The current signal is supplied to the PWM comparator, the cycle-by-cycle current limiter, and the hiccup mode counter. Soft Start (Startup) and Inrush Current Control Inrush currents to the regulator are controlled by the soft start function. When the A8650 is enabled, after all faults are cleared the soft start pin will source approximately 20 μA ( ISSSU ) and the voltage on the soft start capacitor (CSS) will ramp upward from 0 V. When the voltage at the soft start pin exceeds the Soft Start Offset (VSSOFFS , 200 mV(typ)), the error amplifier output slews upward and, shortly thereafter, PWM switching will begin. As shown in figure 4, there is a short delay (tSS(DELAY) ) between when the EN/SYNC pin transitions high and when the soft start voltage reaches 200 mV. After the A8650 starts switching, the error amplifier will regulate the voltage at the FB pin to the soft start pin voltage minus the Soft Start Offset voltage. After switching starts, the voltage at the SS pin will rise from 200 mV to 1000 mV, a difference of 800 mV. At the same time, the voltage at the FB pin will rise from 0 V to 800 mV and the regulator output voltage will rise from 0 V to the setpoint determined by the feedback resistor divider (RFB1 and RFB2). When the voltage at the soft start pin reaches approximately 1000 mV, the error amplifier will change mode and begin regulating to the A8650 internal reference, 800 mV. The voltage at the soft start pin will continue to rise to approximately VIN . Complete soft start operation is shown in figure 4. During startup, the PWM switching frequency is scaled linearly from fOSC / 3 to fOSC as the voltage at the FB pin ramps from 0 V to 600 mV. This is done to prevent the output inductor current from climbing to a level that may damage the A8650 when the input voltage is high and the output of the regulator is either shorted or soft starting a relatively high capacitance or very heavy load. Pre-Biased Startup If the output capacitors are pre-biased, the A8650 will shift the startup routine parameters to prevent discharging the output capacitors. Normally, PWM switching starts when the voltage at the soft start pin reaches approximately 200 mV. However, in the case with pre-biasing, the voltage at the FB pin (VFB) is nonzero. Switching will not start until the voltage at the soft-start VEN/SYNC VOUT = 1.8 V Switching starts when VCOMP > 350 mV VOUT VCOMP VSS = 1000 mV tSS VSS IL tSS(DELAY) VSS = 200 mV Figure 4. Startup to VOUT = 1.8 V, at IOUT = 2.0 A with CSS = 10 nF Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 pin increases to approximately VFB + 200 mV. At this voltage, the error amplifier output will slew upward. Shortly thereafter, PWM switching starts and VOUT ramps upward from the prebias level. Figure 5 shows startup when the output voltage is pre‑biased to 0.9 V. Power OK (POK) Output The Power OK (POK) output is an open drain output, so an external pull-up resistor must be connected to it. An internal comparator monitors the voltage at the FB pin and controls the internal open drain N-MOSFET at the POK pin. POK is high when the voltage at the FB pin is within regulation. The POK output is pulled low if any of the following are true: • VFB is rising, and is < 92% of the internal reference voltage, or • VFB is rising, and is > 115% of the internal reference voltage, or • EN/SYNC is low for more than 32 PWM clock cycles, or • VIN pin UVLO occurs, or • Thermal Shutdown (TSD) occurs. If the A8650 is running and EN/SYNC transitions low for more than 32 PWM clock cycles, then POK will transition low and remain low only as long as the internal circuitry is able to enhance the open-drain output device. When VIN fully collapses, POK will return to the high impedance state. The POK comparator incorporates hysteresis to prevent chattering due to voltage ripple at the FB pin. VEN/SYNC VOUT VOUT rises from 0.9 V VOUT = 0.9 V VOUT = 1.8 V Switching starts when VCOMP > 350 mV COMP pin released at VSS > VFB + 200 mV VCOMP VSS IL VSS = 200 mV Figure 5. Startup to VOUT = 1.8 V, VOUT pre-biased to 0.9 V Protection Features Undervoltage Lockout (UVLO) An undervoltage lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the lockout threshold (VINUVSTART). The UVLO comparator incorporates enough hysteresis (VINUVHYS ) to prevent on/off cycling of the regulator due to IR drops in the VIN path during heavy loading or during startup. Figure 8 shows the A8650 operation for a UVLO-initiated startup (EN/SYNC = high, VIN ramps up). Thermal Shutdown (TSD) The A8650 protects itself from overheating by means of an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold (TTSD , 170°C (typ)) the voltages at the soft start and COMP pins will be pulled to GND and both the high-side and low-side MOSFETs will be turned off. The A8650 will automatically restart when the junction temperature decreases more than the thermal shutdown hysteresis (TTSDHYS , 20°C(typ)). Figure 8 shows the A8650 operation during and after a TSD event. Overvoltage Protection (OVP) The A8650 uses the FB pin to provide a basic level of overvoltage protection. An overvoltage condition could occur if the load current decreases very quickly or the regulator output is pulled high by some external voltage. When an overvoltage condition is detected, POK is pulled low and PWM switching stops. The COMP and soft start pins are not directly affected by OVP. If the regulator output decreases back to the allowed operating range, POK will transition to high and PWM switching will resume. Cycle-by-Cycle Overcurrent Protection (OCP) The A8650 monitors the current in the high-side MOSFET and if the current exceeds the cycle-by-cycle overcurrent threshold (ILIM ) then the high-side MOSFET is turned off. Normal PWM operation resumes on the next clock pulse from the oscillator. The A8650 includes leading edge blanking to prevent falsely triggering the cycle-by-cycle current limit when the upper MOSFET is turned on. Because of the addition of the slope compensation ramp to the inductor current, the A8650 delivers more current at lower duty cycles and less current at higher duty cycles. For a given duty cycle, this results in a little more current being available at lower switching frequencies than at higher frequencies. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Figure 6 shows the typical and worst case cycle-by-cycle current limits versus duty cycle, at 2.45 MHz and 250 kHz. so, when hiccup occurs, the voltage at the soft start pin ramps downward. Output Short Circuit (Hiccup Mode) Protection Hiccup mode protects the A8650 when the load is either too high or when the output of the regulator is shorted to ground. When the voltage at the FB pin is below the Hiccup Enable Threshold (HICEN , 625 mV(typ)) hiccup mode protection is enabled. When the voltage at the FB pin is above the Hiccup Disable Threshold (HICDIS , 750 mV(typ)) hiccup mode protection is disabled. When the voltage at the soft start pin decays to a low level (VSS_RESET, 100 mV (typ) ), the hiccup latch is cleared and the 10 µA soft start pin current sink is turned off. Also, the soft start pin begins charging the soft start capacitor with 20 µA, so the voltage at the soft start pin begins to ramp upward. When the voltage at the soft start pin exceeds the Soft Start Offset (VSSOFFS , 200 mV (typ)) the error amplifier will force the voltage at the COMP pin to quickly ramp upward and, shortly thereafter, PWM switching will resume. If the short circuit at the regulator output remains, another hiccup cycle will occur. Hiccup cycles will repeat until the short circuit is removed or the regulator is disabled. If the short circuit is removed, the A8650 will soft start normally and the output voltage will be ramped to the setpoint level. Hiccup mode operation is shown in both figures 7 and 8. Hiccup Mode overcurrent protection monitors the number of overcurrent events using an up/down counter. An overcurrent pulse increments the counter by one and a PWM cycle without an overcurrent pulse decrements the counter by one. If more than seven consecutive overcurrents are detected, then the hiccup latch is set and PWM switching is stopped. The HICCUP signal causes the COMP pin to be pulled low. Hiccup mode also enables a current sink connected to the soft start pin (nominally 10 µA) 4.8 Short removed 4.6 VOUT 4.4 4.2 4.0 3.8 VCOMP ILIM (A) 3.6 3.4 Hiccup latch clears VCOMP ramp accelerates IOUT too high ≈ 4.1 A 3.2 3.0 2.8 MIN_2.45 MHz 2.6 MIN_250 kHz 2.2 2.0 IL MAX_2.45 MHz 2.4 VSS = 200 mV VSS = 100 mV VSS TYP_2.45 MHz TYP_250 kHz MAX_250 kHz 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Duty Cycle (%) Figure 6. Cycle-by-cycle current limiting versus duty cycle; at fSW = 250 kHz (dashed curves) and fSW = 2.45 MHz (solid curves) Figure 7. Hiccup mode operation and recovery Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 TABLE 1. Summary of A8650 Fault Modes and Operation Fault Mode VSS VCOMP High-Side MOSFET and fSW Low-Side MOSFET POK State Reset Condition Output hard short to ground (VOUT = VFB = 0 V) Hiccup after VCOMP ≈ 1.25 V and 7 overcurrent faults Clamped to ≈1.25 V for ILIM , then pulled low during hiccup Controlled by VCOMP . fSW / 3 if 0< VFB<200 mV Active during tOFF(MIN), Off during hiccup Pulled low Auto, if short removed Output overcurrent (heavy load) and VFB < HICDIS Hiccup after VCOMP ≈ 1.25 V and 7 overcurrent faults Clamped to ≈1.25 V for ILIM , then pulled low during hiccup Controlled by VCOMP . fSW / 3 if 0< VFB< 200 mV, fSW / 3 to fSW if 200 mV < VFB < 600 mV Active during tOFF(MIN), Off during hiccup Pulled low Auto, if the load decreases SW hard short to ground Not affected; hiccup may occur when the short is removed Clamped to ≈1.25 V for ILIM , then pulled low if hiccup occurs Controlled by VCOMP . turned off if VSW ≈ 0 V and blanking time expires, fSW / 3 if 0 < VFB < 200 mV Active during tOFF(MIN), Off if hiccup occurs when the short is removed Depends on VOUT Auto, if short removed SW soft short to ground Hiccup after VCOMP ≈ 1.25 V and 7 overcurrent faults Clamped to ≈1.25 V for ILIM , then pulled low during hiccup Controlled by VCOMP . fSW / 3 if 0<VFB< 200 mV, fSW / 3 to fSW if 200 mV < VFB < 600 mV Active during tOFF(MIN), Off during hiccup Depends on VOUT Auto, if short removed Not affected Transitions low via loop response as VFB floats high Off . fSW / 3 if 0< VFB< 200 mV, fSW / 3 to fSW if 200 mV < VFB< 600 mV Off. Disabled if VCOMP < 200 mV (to limit negative SW current) Pulled low Auto, if FB pin connected to VOUT Not affected Transitions low via loop response because VFB > VREF Off . fSW / 3 if 0< VFB< 200 mV, fSW / 3 to fSW if 200 mV < VFB< 600 mV Off. Disabled if VCOMP < 200 mV (to limit negative SW current) Pulled low Auto, if VFB returns to the allowed operating range Output undervoltage (VFB < 92% × VREF) Not affected Transitions high via loop response because VFB < VREF Controlled by VCOMP . fSW / 3 if 0<VFB< 200 mV, fSW / 3 to fSW if 200 mV < VFB < 600 mV Active during tOFF(MIN) Pulled low Auto, if VFB returns to the allowed operating range VIN dropout or EN/SYNC glitches low for > 32 PWM cycles Pulled low and latched until VSS < VSS_RESET Pulled low and latched until VSS > VSSOFFS Off Off Pulled low Auto, if VIN recovers or if EN/SYNC returns high Thermal shutdown (TSD) Pulled low and latched until VSS < VSS_RESET Pulled low and latched until VSS > VSSOFFS Off Off Pulled low Auto, if the junction cools down FB pin open (FB pin floats high due to negative bias current) Output overvoltage (VFB > 115% × VREF) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 COMP SS VOUT SW VIN OC HICCUP HIC_EN TSD EN MODE F/3 to F SS UVLO Startup OFF/UVLO HICDIS Fsw VINUV START PWM F / 3 x7 O C VOUT shorted to GND VPWM OFFS VSS OFFS VSS RESET HICCUP F / 3 x7 S O S C HICCUP F/3 to F SS OFF F/3 to F SS EN glitches low for more than 32 PWM cycles HICEN Fsw VENSYNC(L) PWM 32 Fsw VIN dropout VINUV STOP PWM OFF F/3 to F SS Fsw PWM TSD OFF/TSD F/3 to F SS Fsw PWM 32 OFF A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Figure 8. A8650 timing diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Application Information Design and Component Selection Setting the Output Voltage (VOUT, RFB1, RFB2) The output voltage of the A8650 is determined by connecting a resistor divider from the output node (VOUT) to the FB pin as shown in figure 9. There are trade-offs when choosing the value of the feedback resistors. If the series combination (RFB1+RFB2) is relatively low, then the light-load efficiency of the regulator will be reduced. So, to maximize that efficiency, it is best to choose high-value resistors. On the other hand, if the parallel combination (RFB1 // RFB2 ) is too high, then the regulator may be susceptible to noise coupling into the FB pin. Table 2. Recommended Feedback Resistor Values RFB2 (FB pin to GND) (kΩ) 1.2 6.04 1.5 7.50 8.45 1.8 9.09 7.15 In general, to produce the target output voltage, VOUT : RFB1 = RFB2 RFB1 (VOUT to FB pin) (kΩ) VOUT (V) 12.1 2.5 12.4 5.76 3.3 16.5 5.23 VOUT –1 0.8 (V) (1) Table 2 shows the most common output voltages and recommended feedback resistors, assuming < 0.2% efficiency loss at light load of 100 mA, and a parallel combination of 4 kΩ presented to the FB pin. For optimal system accuracy, it is recommended that the feedback resistors have ≤1% tolerances. 2.25 2.00 1.75 Frequency (MHz) Base PWM Switching Frequency (RFSET) The base PWM switching frequency is set by connecting a resistor from the FSET pin to ground. Figure 10 is a graph showing the relationship between the typical switching frequency (y-axis) and the FSET resistor (x-axis). For a particular base switching 2.50 1.50 1.25 1.00 0.75 0.50 VOUT 0.25 RFB1 FB PIN 0.00 5.0 15.0 25.0 35.0 45.0 55.0 65.0 75.0 85.0 95.0 RFSET (kΩ) RFB2 Figure 10. PWM switching frequency versus RFSET Figure 9. Connecting a feedback resistor divider Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 frequency (fOSC ), the FSET resistor can be calculated as follows: RFSET = 24900 – 1.7 fOSC (2) Equations 5 and 6 can be used to calculate a range of values for the output inductor based on the well known approach of providing slope compensation that matches 50% to 100% of the falling slope of the inductor current: where fOSC is in kHz and RFSET is in kΩ. The oscillator frequency will be the final output switching frequency (unless the synchronization function is applied), so when the oscillator frequency is being chosen, the designer should be aware of the minimum controllable on-time, tON(MIN) , of the A8650. If the system required on-time is less than the A8650 minimum controllable on-time, then switch node jitter will occur and the output voltage will have increased ripple or oscillations. The minimum oscillator frequency required should be calculated as follows: fSWMAX = VOUT tON(MIN) ×VIN(MAX) (3) where tON(MIN) is the minimum controllable on-time of the A8650 (worst case 105 ns), and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). If the A8650 PWM synchronization function is employed, then the oscillator frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency, determined from equation 3: 1.5 × fSW < fSWMAX where LO is in µH. (5) In equation 5, the slope compensation (SE ) is a function of switching frequency, as follows: SE = 1.175 × f OSC(6) where SE is in A/µs and fSW is in MHz. More recently, Dr. Raymond Ridley presented a formula to calculate the amount of slope compensation required to critically damp the double poles at half the PWM switching frequency: LO ≥ VOUT SE 1 – 0.18 × VIN(min) VOUT (7) This formula allows the inclusion of the duty cycle (D), which should be calculated at the minimum input voltage to ensure optimal stability. Also, to avoid dropout (that is, saturation of the buck regulator), VIN(min) must be approximately 0.75 to 1.0 V above VOUT when calculating the inductor value with equation 7. VOUT is the output voltage, VOUT VOUT ≤ LO ≤ 2 × SE SE (4) Output Inductor (LO) When considering a peak current mode regulator, it is common knowledge that, without adequate slope compensation, the system will become unstable when the duty cycle is near or above 50%. However, the slope compensation in the A8650 is a fixed value (SE ). Therefore, it is important to calculate an inductor value so the falling slope of the inductor current (SF) will work well with the A8650 slope compensation. If equations 6 or 7 yield an inductor value that is not a standard value, then the next closest available value should be used. The final inductor value should allow for 10% to 20% of initial tolerance and 10% to 20% of inductor saturation. The saturation current of the inductor should be higher than the peak current capability of the A8650. Ideally, for output short circuit conditions, the inductor should not saturate even at the highest cycle-by-cycle current limit at minimum duty cycle (ILIM(5%) ; 4.7 A(max)). This may be too costly. At the very least, the inductor should not saturate given the peak operating current according to the following equation: IPEAK = 4.1 – SE × (VOUT ) (8) where VIN(max) is the maximum continuous input voltage, such as 5.5 V. 1.15 × fSW × VIN (max) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Starting with equation 8, and subtracting half of the inductor ripple current, provides us with an interesting equation to predict the typical DC load capability of the regulator at a given duty cycle (D): IOUT(DC) = 4.1 – SE× D fSW VOUT × (1– D) 2 × fSW × LO (9) where D is VOUT / VIN. After an inductor is chosen, it should be tested during output short circuit conditions. The inductor current should be monitored using a current probe. A good design would ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. Output Capacitors The output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (ΔVOUT ) is a function of the output capacitor parameters: COUT , ESRCOUT , and ESLCOUT: ∆VOUT = ∆IL × ESRCOUT + VIN –VOUT LO ∆IL + 8 fSW C OUT × ESLCOUT (10) The type of output capacitors will determine which terms of equation 10 are dominant. For ceramic output capacitors the ESRCOUT and ESLCOUT are virtually zero, so the output voltage ripple will be dominated by the third term of equation 10: ∆VOUT = ∆IL 8 fSW C OUT (11) To reduce the voltage ripple of a design using ceramic output capacitors, simply: increase the total capacitance, reduce the inductor current ripple (that is, increase the inductor value), or increase the switching frequency. For electrolytic output capacitors the value of capacitance will be relatively high, so the third term in equation 10 will be very small. The output voltage ripple will be determined primarily by the first two terms of equation 10: ∆VOUT = ∆IL × ESRCOUT + VIN – VOUT × ESLCOUT LO (12) To reduce the voltage ripple of a design using electrolytic output capacitors, simply: decrease the equivalent ESRCOUT and ESLCOUT by using a high(er) quality capacitor, or add more capacitors in parallel, or reduce the inductor current ripple (that is, increase the inductor value). The ESR of some electrolytic capacitors can be quite high so we recommend choosing a quality capacitor that clearly documents the ESR or the total impedance in the data sheet. Also, the ESR of electrolytic capacitors usually increases significantly at cold ambients, as much as 10×, which increases the output voltage ripple and, in most cases, significantly reduces the stability of the system. The transient response of the regulator depends on the number and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (di/dt), the output voltage will change by the amount di (13) ESLCOUT dt After the load transient occurs, the output voltage will deviate from its nominal value for a short time. This time will depend on the system bandwidth, the output inductor value, and output capacitance. Eventually, the error amplifier will bring the output voltage back to its nominal value. ∆VOUT = ∆ILOAD × ESRCOUT + The speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. A higher bandwidth usually results in a shorter time to return to the nominal voltage. However, a higher bandwidth system may be more difficult to obtain acceptable gain and phase margins. Selection of the compensation components (RZ, CZ, CP ) are discussed in more detail in the Compensation Components section of this datasheet. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Input Capacitors Three factors should be considered when choosing the input capacitors. First, they must be chosen to support the maximum expected input voltage with adequate design margin. Second, their rms current rating must be higher than the expected rms input current to the regulator. Third, they must have enough capacitance and a low enough ESR to limit the input voltage dv/dt to something much less than the hysteresis of the VIN pin UVLO circuitry (200 mV (typ)) at maximum loading and minimum input voltage. 90% reduction) so these types should be avoided. The X5R and X7R type capacitors should be the primary choices due to their stability versus both DC bias and temperature. The input capacitor(s) must limit the voltage deviations at the VIN pin to something significantly less than the A8650 VIN pin UVLO hysteresis during maximum load and minimum input voltage. The minimum input capacitance can be calculated as follows: IOUT × D × (1– D) CIN ≥ (14) 0.85 × fSW × ∆VIN(MIN) Soft Start and Hiccup Mode Timing (CSS) The soft start time of the A8650 is determined by the value of the capacitance at the soft start pin, CSS. When the A8650 is enabled the voltage at the soft start pin will start from 0 V and will be charged by the soft start current, ISSSU . However, PWM switching will not begin instantly because the voltage at the soft start pin must rise above 200 mV. The soft start delay (tSS(DELAY)) can be calculated using the following equation: where ΔVIN(MIN) is chosen to be much less than the hysteresis of the VIN pin UVLO comparator (ΔVIN(MIN) ≤ 100 mV is recommended), and fSW is the nominal PWM output frequency. The D × (1–D) term in equation 14 has an absolute maximum value of 0.25 at 50% duty cycle. So, for example, a very conservative design, based on: IOUT = 2.0 A, fSW = 85% of 2 MHz, D × (1–D) = 0.25, and ΔVIN = 100 mV, yields: 2.0 (A) × 0.25 = 2.9 µF 1.7 (MHz) × 100 (mV) The input capacitors must deliver the rms current according to: CIN ≥ where the duty cycle D = VOUT / VIN. tSS(DELAY) = CSS × A good design should consider the DC-bias effect on a ceramic capacitor. As the applied voltage approaches the rated value, the capacitance value decreases. This effect is very pronounced with the Y5V and Z5U temperature characteristic devices (as much as (16) ICO = COUT × VOUT / tSS(17) (15) Figure 11 shows the normalized input capacitor rms current versus duty cycle. To use this graph, simply find the operational duty cycle (D) on the x-axis and determine the input/output current multiplier on the y-axis. For example, at a 20% duty cycle, the input/output current multiplier is 0.40. Therefore, if the regulator is delivering 2.0 A of steady-state load current, the input capacitor(s) must support 0.40 × 2.0 A or 0.8 ARMS . 200 (mV) ISSSU If the A8650 is starting into a very heavy load a very fast soft start time may cause the regulator to exceed the cycle-by-cycle overcurrent threshold. This occurs because the total of the full load current, the inductor ripple current, and the additional current required to charge the output capacitors: 0.55 0.50 0.45 0.40 Irms / IOUT Irms = IOUT D × (1– D) For all ceramic capacitors, the DC bias effect is even more pronounced on smaller case sizes so a good design will use the largest affordable case size (such as 1206 or 1210). Also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst case transient input voltage. 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Figure 11. Input capacitor ripple versus duty cycle Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 is higher than the cycle-by-cycle current threshold, as shown in figure 12. This phenomena is more pronounced when using high value electrolytic type output capacitors. To avoid prematurely triggering hiccup mode the soft start capacitor, CSS , should be calculated according to: CSS ≥ ISSSU × VOUT × COUT 0.8 (V) × ICO (18) where VOUT is the output voltage, COUT is the output capacitance, ICO is the amount of current allowed to charge the output capacitance during soft start (recommend 0.1 A < ICO < 0.3 A). Higher values of ICO result in faster soft start times. However, lower values of ICO ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an ICO of 0.1 A and increasing it only if the soft start time is too slow. If a non-standard capacitor value for CSS is calculated, the next larger value should be used. The output voltage ramp time, tSS , can be calculated by using either of the following methods: C (19) tSS = VOUT × OUT ICO or tSS = 0.8 (V) × CSS (20) ISSSU When the A8650 is in hiccup mode, the soft start capacitor is used as a timing capacitor and sets the hiccup period. The soft start pin charges the soft start capacitor with ISSSU during a startup attempt, and discharges the same capacitor with ISSHIC between startup attempts. Because the ratio ISSSU / ISSHIC is approximately 2:1, the time between hiccups will be about two } I LIM I LOAD Output capacitor current, I CO t SS Figure 12. Output current (ICO) during startup times as long as the startup time. Therefore, the effective dutycycle of the A8650 will be very low and the junction temperature will be kept low. Compensation Components (RZ , CZ , CP ) To compensate the system it is important to understand where the buck power stage, load resistance, and output capacitance form their poles and zeros in frequency. Also, its important to understand not only that the (Type II) compensated error amplifier introduces a zero and two more poles, but also where these should be placed to maximize system stability, provide a high bandwidth, and optimize the transient response. First, consider the power stage of the A8650, the output capacitors, and the load resistance. This circuitry is commonly referred as the control-to-output (CO) transfer function. The low frequency gain of this circuitry depends on the COMP to SW current gain ( gmPOWER ), and the value of the load resistor (RL ). The DC gain (GCO(0HZ)) of the control-to-output is: GCO(0Hz) = gmPOWER × RL(21) The control-to-output transfer function has a pole (fP1), formed by the output capacitance (COUT) and load resistance (RL), located at: fP1 = 1 2� × RL × COUT (22) The control-to-output transfer function also has a zero (fZ1) formed by the output capacitance (COUT) and its associated ESR: fZ1 = 1 2� × ESR × COUT (23) For a design with very low-ESR type output capacitors (such as ceramic capacitors), the ESR zero (fZ1) is usually at a very high frequency, so it can be ignored. On the other hand, if the ESR zero falls below or near the 0 dB crossover frequency of the system (as is the case with electrolytic output capacitors), then it should be cancelled by the pole formed by the CP capacitor and the RZ resistor (discussed and identified later as fP3). A Bode plot of the control-to-output transfer function for the A8650 circuit shown in the typical application schematic on the front page (VOUT = 1.8 V, IOUT = 2.0 A, RL = 0.9 Ω) is shown in figure 13. The pole at fP1 can easily be seen at 8.8 kHz while the ESR zero, fZ1, occurs at a very high frequency, 4 MHz (this is Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 typical for a design using ceramic output capacitors). Note, there is more than 90° of total phase shift because of the double-pole at half the switching frequency. Next, consider the feedback resistor divider, (RFB1 and RFB2 ), the error amplifier (gm), and the compensation network RZ CZ CP . It greatly simplifies the transfer function derivation if RO >> RZ , and CZ >> CP . In most cases, RO > 2 MΩ, 1 kΩ < RZ < 100 kΩ, 220 pF < CZ < 47 nF, and CP < 50 pF, so the following equations are very accurate. The low frequency gain of the control section (GC(0Hz) ) is formed by the feedback resistor divider and the error amplifier. It can be calculated as: = = RFB2 RFB1 +RFB2 VFB VOUT VFB × gm × RO (24) VOUT is the output voltage, VFB is the reference voltage (0.8 V), gm is the error amplifier transconductance (750 µA/V ), and RO is the error amplifier output impedance (AVOL/gm ). 80 0 -20 fZ1 = 4 MHz -40 60 -20 -80 180 -40 180 90 Double Pole at 1 MHz -90 -180 101 102 103 104 Frequency (Hz) Figure 13. Control-to-Output Bode plot 105 (26) 1 2� × RZ × CP (27) 106 107 G C(0Hz) = 58 dB 40 f = 45 Hz P2 20 0 -60 0 1 2� × RZ × CZ A Bode plot of the error amplifier and its compensation network is shown in figure 14, fP2 , fP3 , and fZ2 are indicated on the magnitude plot. Notice that the zero (fZ2 at 16 kHz) has been placed so that it is just above the pole at fP1 previously shown in the control-to-output Bode plot at 8.8 kHz, figure 13. Placing fZ2 just above fP1 will result in excellent phase margin, but relatively slow transient recovery time, as will be shown later. Phase (°) Gain (dB) Phase (°) fZ2 = fP1 = 8.8 kHz 20 G CO(0Hz) = 12 dB (25) The transfer function of the Type-II compensated error amplifier also has frequency zero (fZ2) dominated by the RZ resistor and the CZ capacitor: fP3 = where 40 1 2� × RO × CZ Lastly, the transfer function of the Type-II compensated error amplifier has a (very) high frequency pole (fP3) dominated by the RZ resistor and the CP capacitor: × gm × RO × AVOL VOUT fP2 = Gain (dB) GC(0Hz) = The transfer function of the Type-II compensated error amplifier has a (very) low frequency pole (fP2 ) dominated by the output error amplifier output impedance (RO) and the CZ compensation capacitor: f Z2 = 16 kHz fP3 ≈ 1.1 MHz 135 90 45 0 101 102 103 104 105 106 107 Frequency (Hz) Figure 14. Type-II compensated error amplifier Bode plot Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 Finally, consider the combined Bode plot of both the controlto-output and the compensated error amplifier, the red curve shown in figure 15. Careful examination of this plot shows that the magnitude and phase of the entire system (in red) are simply the sum of the error amplifier response (blue) and the control-tooutput response (green). As shown in figure 15, the bandwidth of this system (fc ) is 72 kHz, the phase margin is 73 degrees, and the gain margin is 27 dB. 3. Determine the frequency of the pole (fP1). This pole is formed by COUT and RL. Use equation 22 (repeated here): fP1 = 1 2� × RL × COUT 4. Calculate a range of values for the CZ capacitor. Use the following: A Generalized Tuning Procedure This section presents a methodology to systematically apply the design considerations provided above. 4 1 < CZ < 2� × RZ × fC 2� × RZ × 1.5 × fP1 (29) 1. Choose the system bandwidth (fC ). This is the frequency at which the magnitude of the gain crosses 0 dB. Recommended values for fC , based on the PWM switching frequency, are in the range fSW / 20 < fC < fSW / 7.5. A higher value of fC generally provides a better transient response, while a lower value of fC generally makes it easier to obtain higher gain and phase margins. To maximize system stability (that is, to have the greatest gain margin), use a higher value of CZ . To optimize transient recovery time, although at the expense of some phase margin, use a lower value of CZ . 2. Calculate the RZ resistor value. This sets the system bandwidth (fC): 2� × COUT RZ = fC × VOUT × (28) VFB gmPOWERx × gm Figure 16 compares the output voltage recovery time due to a 1 A load transient for the system shown in figure 15 (fZ2 = 16 kHz, 73° phase margin) and a system with fZ2 at 50 kHz. The system with fZ2 at 50 kHz has only 51° of phase margin, but recovers to within 0.5% much faster ( ≈ 3×) than the other system. 1.840 fC = 72 kHz fZ2 = 16 kHz 1.800 0 GM= 27 dB -100 180 Phase (°) fZ2 = 50 kHz 1.820 Voltage (V) Gain (dB) 100 1.780 1.760 90 PM =73 deg 0 1.740 -90 -180 101 102 103 104 105 Frequency (Hz) Figure 15. Bode plot of the complete system (red curve) 106 107 1.720 240 250 260 270 280 290 300 310 320 330 Time (µs) Figure 16. Transient recovery comparison for fZ2 at 16 kHz / 73° and 50 kHz /51° Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 5. Calculate the frequency of the ESR zero (fZ1) formed by the output capacitor(s). Use equation 23 (repeated here): fZ1 = 1 2� × ESR × COUT If fZ1 is at least one decade higher than the target crossover frequency (fC) then fZ1 can be ignored. This is usually the case for a design using ceramic output capacitors. Use equation 27 to calculate the value of CP by setting fP3 to either 5 × fC or fSW / 2, whichever is higher. Alternatively, if fZ1 is near or below the target crossover frequency (fC), then use equation 27 to calculate the value of CP by setting fP3 equal to fZ1. This is usually the case for a design using high ESR electrolytic output capacitors. PSW1 = VIN × IOUT × (tr + tf ) × fSW 2 where (31) VIN is the input voltage, IOUT is the output current, fSW is the PWM switching frequency, and tr and tf are the rise and fall times measured at the SW node. Approximate values for tr range from 10 to 15 ns. The fall time is usually about 50% faster than the rise time. The conduction losses dissipated by the high-side MOSFET while it is conducting can be calculated using the following equation: 2 PCOND1 = Irms(FET) × RDS(on)HS Power Dissipation and Thermal Calculations The power dissipated in the A8650 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due to the switching of the internal power high-side MOSFET (PSW1 ), the power dissipated due to the rms current being conducted by the high- and low-side MOSFETs (PCOND1 and PCOND2), the power dissipated by the low-side MOSFET body diode during the non-overlap times, and the power dissipated by the internal gate drivers (PDRIVER1 and PDRIVER2). The power dissipated from the VIN supply current can be calculated using the following equation: = (32) IOUT is the regulator output current, ΔIL is the peak-to-peak inductor ripple current, and RDS(on)HS is the on-resistance of the high-side MOSFET. The conduction losses dissipated by the low-side MOSFET while it is conducting can be calculated using the following equation: 2 PCOND2 = Irms(FET) × RDS(on)LS = 1– where The switching losses dissipated by the internal high-side MOSFET during PWM switching can be calculated using the following equation: where PIN = VIN × IQ + (VIN – VGS ) × (QG1 + QG2 ) × fSW(30) VIN is the input voltage, IQ is the input quiescent current drawn by the A8650 (nominally 2 mA), VGS is the MOSFET gate drive voltage, typically 5.0 V, QG1 and QG2 are the internal high- and low-side MOSFET gate charges (approximately 3.3 nC and 1.4 nC respectively), and fSW is the PWM switching frequency. VOUT ∆IL2 2 × IOUT + 12 × RDS(on)HS VIN VOUT ∆IL2 2 × IOUT + 12 × RDS(on)LS VIN where (33) IOUT is the regulator output current, ΔIL is the peak-to-peak inductor ripple current, and RDS(on)LS is the on-resistance of the low-side MOSFET. The RDS(on)of the MOSFETs has some initial tolerance plus an increase from self-heating and elevated ambient temperatures. A conservative design should accommodate an RDS(on) with at least a 15% initial tolerance plus 0.39%/°C increase due to temperature. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK The power dissipated by the low-side MOSFET body diode during the non-overlap time can be calculated as follows: PNO = VSD × IOUT × 2 × t NO × fSW(34) where TJ = PTOTAL × RθJA + TA (37) where VSD is the source-to-drain voltage of the low-side MOSFET (typically 0.60 V), and tNO is the non-overlap time (15 ns (typ)). The power dissipated by the internal gate drivers can be calculated using the following equation: PDRIVERS = (QG1 + QG2 ) × VGS × fSW The average junction temperature can be calculated with the following equation: (35) where QG1 and QG2 are the internal gate charges to drive the high- and low-side MOSFETs to VGS (approximately 3.3 nC and 1.4 nC at 5 V, respectively), and fSW is the PWM switching frequency. Finally, the total power dissipated by the A8650 (PTOTAL) is the sum of the previous equations: PTOTAL = PIN + PSW1 + PCOND1 + PCOND2 + PNO + PDRIVERS(36) PTOTAL is the total power dissipated as described in equation 36, RθJA is the junction-to-ambient thermal resistance (48°C/W on a 4-layer PCB), and TA is the ambient temperature. The maximum junction temperature will be dependent on how efficiently heat can be transferred from the PCB to ambient air. It is critical that the thermal pad on the bottom of the IC should be connected to a at least one ground plane using multiple vias. As with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. There are trade-offs between: ambient operating temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and other nearby heat sources. Even a small amount of airflow will reduce the junction temperature considerably. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK PCB Component Placement and Routing A good PCB layout is critical if the A8650 is to provide clean, stable output voltages. Follow these guidelines to ensure a good PCB layout. Figure 17 shows a typical synchronous buck regulator schematic with the critical power paths/loops. Figure 18 shows an example PCB component placement and routing with the same critical power paths/loops as shown in the schematic. 1. Place the ceramic input capacitors as close as possible to the VIN pin and ground the capacitors at the PGND pin. The ceramic input capacitors and the A8650 must be on the same layer. Connect the input capacitors, the VIN pin, and the PGND pin with a wide trace. This critical loop is shown as trace 1 in figures 17 and 18. 2. Place the output inductor (LO) as close as possible to the SW pin. The output inductor and the A8650 must be on the same layer. Connect the SW pin to the output inductor with a relatively wide trace or polygon. For EMI/EMC reasons, its best to minimize the area of this trace/polygon. This critical trace is shown as trace 2 in figure 17. Also, keep low-level analog signals (like FB and COMP) away from the SW metal. 3. Place the output capacitors relatively close to the output inductor and the A8650. Ideally, the output capacitors, output inductor and the A8650 should be on the same layer. Connect the output inductor and the output capacitors with a fairly wide trace. The output capacitors must use a ground plane to make a very low-inductance connection back to the PGND pin. These critical connections are shown as trace 3 in figures 17 and 18. 4. Place the feedback resistor divider (RFB1 and RFB2) very close to the FB pin. Orient RFB2 such that the ground side is as close as possible to the A8650. 5. Place the compensation components (RZ , CZ , and CP ) as close as possible to the COMP pin. Orient CZ and CP such that their ground connections are as close as possible to the A8650. 6. Place and ground the FSET resistor as close as possible to the FSET pin. 7. The output voltage sense trace (from VOUT to RFB1 ) should be connected as close as possible to the load to obtain the best load regulation. 8. The thermal pad under the IC should be connected to a ground plane (preferably on the top and bottom layers) with as many vias as possible. Allegro recommends vias with an approximately 0.25 to 0.30 mm hole and a 0.13 to 0.18 mm ring. 9. Place the soft start capacitor (CSS ) as close as possible to the SS pin. Place a via to the GND plane as close as possible to this component. 10. When connecting the input and output ceramic capacitors to a power or ground plane, use multiple vias and place the vias as close as possible to the component pads. Do not use thermal reliefs (spokes) around the pads for the input and output ceramic capacitors. 11. EMI/EMC issues are always a concern. Allegro recommends having locations for an RC snubber from SW to ground. The snubber components can be placed on the back of the PCB and populated only if necessary. The resistor should be 0805 or 1206 size. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 1 RFB1 VIN A8650 FB CIN SS FSET COMP RFB2 RFSET CP 2 RZ CZ 3 COUT GND LOAD Css SW LO PGND 1 3 Figure 17. Typical synchronous buck converter with critical paths/loops shown; a single-point ground is recommended, which could be the exposed thermal pad, under the IC 3 3 2 1 Figure 18. Example PCB component placement and routing Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK For Reference Only – Not for Tooling Use (Reference JEDEC MO-187) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0° to 6° 3.00 ±0.10 10 0.15 ±0.05 3.00 ±0.10 4.88 ±0.20 A 0.53 ±0.10 1 2 1.98 1 0.25 Seating Plane 2 Gauge Plane A Terminal #1 mark area B Exposed thermal pad (bottom surface) B 1.73 10 0.86 ±0.05 SEATING PLANE 0.27 0.18 0.50 REF 0.05 0.15 Package LY, 10-Pin MSOP with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK A8650 For Reference Only – Not for Tooling Use (Reference DWG 2860) Dimensions in millimeters – NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown 0.30 3.00 ±0.15 0.50 10 10 0.85 3.00 ±0.15 1.64 3.10 A 1 2 1 11X D 0.08 C 0.25 C SEATING PLANE +0.05 –0.07 0.05 0.00 0.5 BSC 1 2 0.40 ±0.10 PCB Layout Reference View 0.2 REF A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 1.65 NOM B 2.38 C 0.75 ±0.05 10 2.38 NOM Package EJ, 10-Pin DFN with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 A8650 Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK Revision History Revision Revision Date 6 January 13, 2014 Miscellaneous conforming edits Description of Revision 7 October 27, 2014 Revised equation 7 8 November 20, 2015 Added EJ 10-Pin DFN Package Copyright ©2015, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31