A8654 Datasheet

A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
FEATURES AND BENEFITS
DESCRIPTION
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•
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•
•
•
•
•
The A8654 is a high output current synchronous buck regulator
that integrates low RDSON high-side and low-side N-channel
MOSFETs. The A8654 incorporates PWM current-mode control
to provide simple compensation, excellent loop stability and
fast transient response. The A8654 uses external compensation
to accommodate a wide range of power components to achieve
both excellent loop stability and desirable transient response.
The A8654 regulates nominal input voltages from 4 to
36 V and remains operational when VIN drops as low as
2.6 V. When the input voltage approaches the output voltage,
the duty cycle is maximized to maintain the output voltage.
The A8654 is able to provide 3 A steady-state load current.
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Automotive AEC-Q100 qualified
Operating voltage range: 4 to 36 V
UVLO STOP threshold: 2.6 VTYP
Maximized duty cycle for low-dropout operation
Withstands surge voltages up to 40 V
Capable of 3 A steady-state output current
Integrated high-side and low-side switching MOSFETs
Adjustable switching frequency (fSW): 100 kHz to
2.2 MHz
Synchronization capability to external clock: 100 kHz to
2.2 MHz
Frequency dithering for lower EMI signature
External adjustable compensation network
Soft-start time externally set via the SS pin
Pre-bias startup compatible
Active-low, power-on reset (NPOR) output
The A8654 features externally set soft-start time, external
compensation network, an EN input to enable VOUT, a
SYNC/FSET input to synchronize or set the PWM switching
Continued on next page...
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APPLICATIONS
PACKAGES:
16-Pin eTSSOP (LP) with exposed thermal pad
• Automotive Infotainment •
Systems
□□ Audio, Video Navigation
Systems
□□ Rear Seat Media Display
□□ Instrument Clusters
□□ Telematics
•
Not to scale
VIN
CIN
2 × 4.7 µF
BOOT
VIN
CBOOT
100 nF
GND
LO
SW
CO
EN
SYNC/FSET
A8654
RFSET
SS
RPU
10 kΩ
NPOR
CSS
22 nF
COMP
RFB1
CP
RZ
CZ
FB
RFB2
Typical Application Diagram 1
A8654-DS, Rev. 2
Advanced Driver
Assistance Systems
□□ RADAR, LIDAR,
mmWave systems
□□ Vision and Detection
System
Industrial
□□ General 24 V / 36 V
applications
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
FEATURES AND BENEFITS (continued)
• Overvoltage protection, pulse-by-pulse current limit, hiccup
mode short-circuit and thermal protections
• Open-circuit and adjacent pin short-circuit tolerant
• Short-to-ground tolerant at every pin
• Stable with ceramic output capacitors
DESCRIPTION (continued)
frequency, and a NPOR output validated by the output voltage.
Protection features include VIN undervoltage lockout (UVLO),
pulse-by-pulse overcurrent protection, hiccup mode short-circuit
protection, overvoltage protection, and thermal shutdown. A8654
provides open-circuit, adjacent pin short-circuit and short-to-ground
protection at every pin to satisfy the most demanding automotive
and nonautomotive applications.
The maximum junction temperature is 150°C. The A8654 device
is available in a 16-pin eTSSOP package with exposed pads for
enhanced thermal dissipation. It is lead (Pb) free, with 100% mattetin leadframe plating.
SELECTION GUIDE
Part Number
A8654KLPTR-T
Packing
Package
4000 pieces per 13-inch reel
4.4 mm × 5 mm, 1.2 mm nominal height 16-pin
eTSSOP with exposed thermal pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1
Characteristic
Symbol
Notes
Rating
VIN, EN, SS
SW to GND 2
BOOT Pin Above SW Pin
VSW
VBOOT
Continuous
VIN ≤ 36 V, t < 50 ns
Storage Temperature Range
V
–0.3 to VIN + 0.3
V
–1.0 to VIN + 2.0
V
Continuous
VSW – 0.3 to VSW + 5.5
V
< 1 ms
VSW – 0.3 to VSW + 7.0
V
–0.3 to 5.5
V
All other pins
Maximum Junction Temperature
Unit
–0.3 to 40
TJ(max)
150
°C
Tstg
–55 to 150
°C
1 Stresses
beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability
2 SW has internal clamp diodes to GND and VIN. Applications that forward bias these diodes should take care not to exceed the IC package power dissipation limits.
THERMAL CHARACTERISTICS
Characteristic
Package Thermal Resistance
3 Additional
Symbol
RθJA
Test Conditions 3
LP Package, 4-layer PCB based on JEDEC standard
Value
Unit
34
°C/W
thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
PINOUT DIAGRAM AND TERMINAL LIST TABLE
EN
1
16 BOOT
VIN
2
15 SW
SS
3
14 PGND
TSTGND1
4
13 PGND
FB
5
TSTGND2
6
11 TSTGND3
SGND
7
10 NPOR
COMP
8
9
PAD
12 TSTGND4
SYNC/FSET
Package LP, 16-Pin eTSSOP Pinout Diagram
Terminal List Table
Symbol
Number
Function
EN
1
Enable input. This pin is used to turn the converter on or off; set this pin high to turn the converter on or set this pin low
to turn the converter off. May be connected to VIN.
VIN
2
Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. A high quality ceramic
capacitor should be placed very close to this pin.
SS
3
Soft-Start pin. Connect a capacitor (CSS) from this pin to GND to set the soft-start time. This capacitor also determines
the hiccup period during overcurrent.
FB
5
Feedback (negative) input to the error amplifier. Connect a resistor divider from the converter output node (VOUT) to
this pin to program the output voltage.
SGND
7
Signal (quiet) ground.
COMP
8
Output of the error amplifier and compensation node for the control loop. Connect a series RC network from this pin to
GND for loop compensation.
SYNC/FSET
9
Frequency setting and synchronization pin. A resistor, RFSET, from this pin to GND sets the PWM switching frequency.
NPOR
10
Active-low, power-on reset output signal. This pin is an open-drain output that transitions from low to high impedance
after the output has maintained regulation for tD,NPOR.
TSTGND1-4
4, 6, 11, 12
PGND
13, 14
SW
15
The source of the high-side N-channel MOSFET. The output inductor (LO) should be connected to this pin. LO should
be placed as close as possible to this pin and connected with relatively wide traces.
BOOT
16
High-side gate drive boost input. Connect a 100 nF ceramic capacitor from BOOT to SW
PAD
–
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground
plane(s) of the PCB with at least 6 vias, directly in the pad.
Internal test pins, not for use. Should be connected to ground but do not use as main power ground.
Power ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
VIN
BOOT REG
VIN
VREF
Regulator
VREG
BOOT
UVLO
Current Sense
Amp
EN
TSD
OCP
500 nA
EN
Protection & Fault
OVP
SYNC/FSET
OSC
SW
Adj
5 µs
CLK
80 mΩ
110% VREF
FB
PWM
Control
Logic
PWM
COMP
Error Amp
VREG
55 mΩ
VREF
800 mV
Σ
COMP
Slope
Comp
PGND
Ramp
Offset
20 µA
5 µA
HICCUP
LOGIC
400 mV
2 kΩ
FAULT
SS
NPOR
UV
SGND
OV
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
ELECTRICAL CHARACTERISTICS: Valid at 4.0 V ≤ VIN ≤ 36 V; TA = 25°C; ● indicates specifications guaranteed
‒40°C ≤ TA = TJ ≤ 150°C, unless noted otherwise.
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4.0
–
36.0
V
INPUT VOLTAGE SPECIFICATIONS
Operating Input Voltage Range 2
VIN
●
UVLO Start Threshold
VUVLO(START)
VIN rising
–
3.4
3.7
V
UVLO Stop Threshold
VUVLO(STOP)
VIN falling
–
2.6
2.9
V
UVLO Hysteresis
VUVLO(HYS)
–
800
–
mV
–
3.0
6.5
mA
VIN = 12 V, VEN ≤ 0.4 V, –40˚C < TA = TJ
< 85˚C
–
1
240
µA
VIN = 12 V, VEN ≤ 0.4 V, TA = TJ = 125˚C
–
40
900
µA
INPUT CURRENTS
Input Quiescent Current 1
Input Sleep Supply Current 1
IQ
IQ(SLEEP)
VEN = 5 V, VFB = 1.0 V, no PWM switching
●
VOLTAGE REGULATION
Feedback Voltage Accuracy 3
Output Dropout Voltage 3
VFB
VO(PWM)
VFB = VCOMP, -40˚C < TA = TJ < 125˚C
792
800
808
mV
VFB = VCOMP
●
788
800
812
mV
VIN = 5.9 V, IO = 3 A, fSW = 500 kHz
●
4.9
–
–
V
VIN = 7.5 V, IO = 3 A, fSW = 2 MHz
●
4.9
–
–
V
ERROR AMPLIFIER
Feedback Input Bias Current 1
Open Loop Voltage Gain
IFB
AVOL
Transconductance
gm
Output Current
IEA
–100
–
–8
nA
VCOMP = 1.2 V
–
65
–
dB
400 mV < VFB
550
750
950
0 V < VFB < 400 mV
275
375
475
–
±75
–
VCOMP = 1.2 V
µA/V
µA
INTERNAL MOSFET PARAMETERS
High-Side MOSFET On Resistance 3
SW Node Rising Slew Rate
RDSON(HS)
dV/dt
TA = 25˚C, IDS = 100 mA
–
80
–
mΩ
12 V < VIN < 16 V
–
0.75
–
V/ns
–10
0
10
µA
SW Leakage 1
ISW(LEAK)
VEN ≤ 0.4 V, VSW = 5 V, VIN = 12 V,
TJ = 25˚C
Low-Side MOSFET On Resistance 3
RDSON(LS)
TA = 25˚C, IDS = 100 mA
–
55
–
mΩ
RFSET = 261 kΩ
–
100
–
kHz
RFSET = 61.9 kΩ
375
415
457
kHz
RFSET = 10.5 kΩ
–
2.0
–
MHz
OSCILLATOR
PWM Switching Frequency
fSW
PWM Frequency Dithering
fDITHER
No Dithering with FSET Synchronization
–
±13
–
%
Minimum Controllable On-Time
tON(MIN)
VIN = 12 V, IOUT = 1 A
–
95
135
ns
Minimum Switch Off-Time
tOFF(MIN)
VIN = 12 V, IOUT = 1 A
–
100
135
ns
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
ELECTRICAL CHARACTERISTICS (continued): Valid at 4.0 V ≤ VIN ≤ 36 V; TA = 25°C; ● indicates specifications
guaranteed ‒40°C ≤ TA = TJ ≤ 150°C, unless noted otherwise.
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
FSET SYNCHRONIZATION TIMING
Synchronization Frequency Range
fSW_MULT
100
–
2200
kHz
Synchronization Input Off-Time
tSYNC_OFF
0.2
–
1.3
µs
tr(SYNC)
–
10
15
ns
tf(SYNC)
–
10
15
ns
Synchronization Input Rise
Time 3
Synchronization Input Fall Time 3
Synchronization Rising Threshold
VSYNC(HI)
VSYNC rising
–
–
2.0
V
Synchronization Falling Threshold
VSYNC(LO)
VSYNC falling
0.5
–
0.7
V
IPK_LIM(MINON)
tON = tON(MIN)
4.1
4.7
5.3
A
IPK_LIM(MINOFF)
tON = 1/fSW – tOFF(MIN), no sync
3.0
3.9
4.8
A
–
7.3
–
A/V
RFSET = 261 kΩ, 100 kHz
–
0.056
–
A/µs
RFSET = 61.9 kΩ, 415 kHz
CURRENT LOOP
Peak Inductor (Pulse-by-Pulse) Current Limit
COMP to SW Current Gain
Slope Compensation
gmPOWER
SE
0.09
0.24
0.43
A/µs
RFSET = 10.5 kΩ, 2 MHz
–
1.3
–
A/µs
VSS falling due to RSS(FLT)
–
200
275
mV
SOFT-START
SS FAULT/HICCUP Reset Voltage
VSS(RST)
SS Maximum Charge Voltage
VSS(MAX)
SS Startup (Source) Current 1
ISS(SU)
HICCUP = FAULT = 0
SS Hiccup (Sink) Current 1
ISS(HIC)
SS Pull-Down Resistance
RSS(FLT)
SS Switching Frequency
fSS
–
3.3
–
V
–30
–20
–10
µA
HICCUP = 1
1
2.2
5
µA
FAULT = 1 or EN = 0
–
2
–
kΩ
0 V < VFB < 200 mV
–
fSW/4
–
–
200 mV < VFB < 400 mV
–
fSW/2
–
–
400 mV < VFB
–
fSW
–
–
VHIC(EN)
VSS rising
–
2.3
–
V
Hiccup, OCP Count
OCPLIM
VSS > 2.3 V, OCP pulses
–
240
–
counts
Hiccup, BOOT Shorted Count
BOOTUV
–
64
–
counts
BOOTOPEN
–
7
–
counts
840
880
920
mV
–
10
–
mV
HICCUP MODE
Hiccup OCP Enable Threshold
Hiccup, BOOT Open Count
NPOR OUTPUT
VOUT OV Threshold
VOUT(OV)
VOUT OV Hysteresis
VOUT(OV,HYS)
VOUT UV Threshold
VOUT(UV)
VOUT UV Hysteresis
VOUT(UV,HYS)
NPOR Rising Delay
td(NPOR)
NPOR Low Output Votlage
NPOR
Leakage 1
VFB rising
VFB falling, relative to VOUT(OV)
VFB falling
715
740
760
mV
VFB rising, relative to VOUT(UV)
–
10
–
mV
VFB rising only
–
2500
–
PWM
Cycles
VOL(NPOR)
IPOR = 5 mA
–
185
400
mV
INPOR(LEAK)
VPOR = 5.5 V
–
–
5
µA
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
ELECTRICAL CHARACTERISTICS (continued): Valid at 4.0 V ≤ VIN ≤ 36 V; TA = 25°C; ● indicates specifications
guaranteed ‒40°C ≤ TA = TJ ≤ 150°C, unless noted otherwise.
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
155
170
185
°C
–
20
–
°C
V
THERMAL PROTECTION
TSD Rising Threshold
TSD Hysteresis 3
TSD
PWM stops immediately and COMP is
pulled low and SS is reset
TSDHYS
EN INPUT THRESHOLDS
EN High Threshold
VEN(H)
EN rising
–
1.41
2.0
EN Low Threshold
VEN(L)
EN falling
0.7
1.36
–
V
EN Delay
EN Input Bias Current 1
td(EN)
IEN_BIAS
EN transitioning low, VOUT < 25%
–
60
–
PWM
cycles
EN = 5 V
–
500
–
nA
1 For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin or node.
limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
3 Ensured by design and characterization, not production tested.
2 Thermally
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
TYPICAL PERFORMANCE CHARACTERISTICS
4.85
815
4.80
4.75
805
IPK_LIM(MINON) (A)
Reference Voltage, VREF (mV)
810
800
4.70
4.65
4.60
795
4.55
790
4.50
4.45
785
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Temperature (ºC)
Temperature (ºC)
Pulse-by-pulse Current Limit at tON(MIN) (IPK_LIM(MINON))
versus Temperature
Reference Voltage versus Temperature
1.6
3.50
EN Rising Threshold
3.25
EN Falling Threshold
1.4
START, UVLOSTART
EN Thresholds (V)
VIN UVLO Thresholds (V)
1.5
STOP, UVLOSTART
3.00
2.75
1.3
1.2
1.1
1.0
0.9
2.50
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
VIN UVLO START and STOP Thresholds versus
Temperature
75
100
125
150
175
EN Rising and Falling Thresholds versus Temperature
65.0
925
900
62.5
875
60.0
850
825
NPOR Overvoltage
800
NPOR Undervoltage
AVOL (dB)
NPOR OV & UV Thresholds at FB (mV)
50
Temperature (ºC)
Temperature (ºC)
57.5
55.0
775
750
52.5
725
50.0
700
-50
-25
0
25
50
75
100
125
150
Temperature (ºC)
NPOR Overvoltage and Undervoltage Thresholds
at FB versus Temperature
175
-50
-25
0
25
50
75
100
125
150
175
Temperature (ºC)
Open Loop Voltage Gain (AVOL) of Error Amplifier
versus Temperature
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
900
5.5
VFB > 400 mV
0 < VFB < 400 mV
5.0
Input Quiescent Current (mA)
Transconductance (µA/V)
800
700
600
500
400
4.5
4.0
3.5
3.0
300
200
2.5
-50
0
-25
25
75
50
125
100
150
175
-50
0
-25
25
Temperature (ºC)
Error Amplifier Transconductance versus Temperature
100
125
150
175
Quiescent Current IQ versus Temperature
5.00
96
4.50
94
4.00
92
3.50
90
Efficiency (%)
VOUT (V)
75
50
Temperature (ºC)
3.00
2.50
2.00
1.50
88
86
84
VIN = 8 V
82
VIN = 12 V
1.00
80
0.50
78
VOUT vs. VIN
VIN = 16 V
0
0.5
1.5
1.0
0.00
2.0
2.5
3.0
Load (A)
2.5
3.0
3.5
4.5
4.0
5.0
5.5
6.0
VIN (V)
Low VIN Dropout Operation at 5 Ω Load
Efficiency versus Output Current for Typical Designs
(500 kHz in Table 3)
5.1 V
5.1 V
VOUT
VOUT
5.0 V
5.0 V
4.9 V
4.9 V
25 mA/µs
1 A/div
1 A/div
IOUT
25 mA/µs
IOUT
100 µs/div
100 µs/div
Transient Response 0 A to 1 A Load Step
Transient Response 1 A to 2 A Load Step
(Typical Design - 500 kHz in Table 3)
(Typical Design - 500 kHz in Table 3)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
FUNCTIONAL DESCRIPTION
Overview
The A8654 is a synchronous PWM buck regulator that integrates
low RDSON high-side and low-side N-channel MOSFETs. It is
designed to remain operational when input voltage falls as low as
2.6 V. The A8654 employs peak current-mode control to provide
superior line and load regulation, pulse-by-pulse current limit,
fast transient response, and simple compensation.
The features of the A8654 include an internal precision reference, an adjustable switching frequency, a transconductance error
amplifier, an enable input, integrated top and bottom switching
MOSFETs, adjustable soft-start time, pre-bias startup, and an
NPOR output. Protection features of A8654 include VIN undervoltage lockout, pulse-by-pulse overcurrent protection, BOOT
overvoltage and undervoltage protection, hiccup mode shortcircuit protection, overvoltage protection, and thermal shutdown.
In addition, the A8654 provides open-circuit, adjacent pin shortcircuit, and pin-to-ground short-circuit protection.
Reference Voltage
duty-cycle, and rise/fall time requirements shown in the Electrical
Characteristics table in this datasheet.
Transconductance Error Amplifier
The transconductance error amplifier’s primary function is to
control the regulator’s output voltage. The error amplifier is a
three-terminal input device with two positive inputs and one
negative input, as shown in Figure 1. The negative input is simply
connected to the FB pin and is used to sense the feedback voltage for regulation. The error amplifier performs an “analog OR”
selection between its positive inputs, operating according to the
positive input with the lowest potential. The two positive inputs
are used for soft-start and steady-state regulation. The error
amplifier regulates to the soft-start pin voltage minus 400 mV
during startup or the A8654’s internal reference (VREF) during
normal operation.
400 mV
SS
The A8654 incorporates an internal precision reference that
allows output voltages as low as 0.8 V. The accuracy of the
internal reference is ±1% from –40°C to 125°C and ±1.5% across
from –40°C to 150°C. The output voltage of the regulator is
programmed with a resistor divider between VOUT and the FB pin
of the A8654.
Error Amp
COMP
VREF
800 mV
Oscillator/Switching Frequency and Synchronization
The PWM switching frequency of the A8654 is adjustable from
100 kHz to 2.2 MHz and has an accuracy of about ±10% over
the operating temperature range. Connecting a resistor from the
FSET/SYNC pin to GND, as shown in the Applications Schematic, sets the switching frequency. An FSET resistor with ±1%
tolerance is recommended. A graph of switching frequency versus
FSET resistor value is shown in the Component Selection section
of this datasheet. The A8654 will suspend operation if the FSET
pin is shorted to GND or left open.
The FSET/SYNC pin also can be used as a synchronization input
that accepts an external clock to switch the A8654 from 100 kHz
to 2.2 MHz and scales the slope compensation according to the
synchronization frequency. When being used as a synchronization input, the applied clock pulses must satisfy the pulse width,
FB
Figure 1: A8654 Error Amplifier
Compensation Components
To stabilize the regulator, a series RC compensation network
(RZ and CZ) must be connected from the error amplifier’s output
(COMP pin) to GND as shown in the applications schematic. In
most instances, an additional low value capacitor (CP) should be
connected in parallel with the RZ-CZ compensation network to
reduce the loop gain at very high frequencies. However, if the CP
capacitor is too large, the phase margin of the converter may be
reduced. Calculating RZ, CZ, and CP is covered in the Component
Selection section of this datasheet.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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11
A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
If a fault occurs or the regulator is disabled, the COMP pin is
pulled to GND via the approximately 1 kΩ internal resistor and
PWM switching is inhibited.
will be initiated and VOUT will ramp to its final voltage in a time
set by the soft-start capacitor (CSS). To automatically enable the
A8654, the EN pin may be connected directly to VIN.
Slope Compensation
Power MOSFETs
The A8654 incorporates internal slope compensation to allow
PWM duty cycles above 50% for a wide range of input/output
voltages, switching frequencies, and inductor values. As shown
in the functional block diagram, the slope compensation signal
is added to the sum of the current sense and PWM Ramp Offset.
The amount of slope compensation is scaled with the switching
frequency when programming the frequency with a resistor or
with an external clock.
The A8654 includes an 80 mΩ, high-side N-channel MOSFET.
The A8654 also includes a 55 mΩ, low-side N-channel MOSFET
to provide synchronous rectification.
The value of the output inductor should be chosen such that slope
compensation rate SE is between 0.5× and 1× the falling slope of
the inductor current (SF).
Current Sense Amplifier
The A8654 incorporates a high-bandwidth current sense amplifier to monitor the current through the top MOSFET. This current
signal is used to regulate the peak current when the top MOSFET
is turned on. The current signal is also used by the protection
circuitry for the pulse-by-pulse current limit and hiccup mode
short-circuit protection.
Low-Dropout Operation and Undervoltage
Lockout
The Undervoltage Lockout behavior is described in the following
Protection Features section.
The A8654 is designed to allow operation when input voltage
drops as low as 2.6 V which is the UVLO STOP threshold. When
the input voltage falls towards the nominal output voltage, the
high-side switch can remain on for maximum on-time to keep
regulating the output. This is accomplished by decreasing the fSW
switching frequency. In this way, the dropout from the input to
output voltage is minimized.
Sleep Mode with Enable input
The A8654 provides a shutdown function via the EN pin. When
this pin is low, the A8654 is shut down and the A8654 will enter
a “sleep mode” where the internal control circuits will be shut
off and draw less current from VIN. If EN goes high, the A8654
will turn on and provided there are no fault conditions, soft-start
When the A8654 is disabled via the EN input being low or a fault
condition, the A8654’s output stage is tri-stated by turning off
both the upper and lower MOSFETs.
Pulse-Width Modulation (PWM) Mode
The A8654 employs fixed-frequency, peak current-mode control to provide excellent load and line regulation, fast transient
response, and simple compensation.
A high-speed comparator and control logic is included in the
A8654. The inverting input of the PWM comparator is connected to the output of the error amplifier. The non-inverting
input is connected to the sum of the current sense signal, the
slope compensation signal, and a DC PWM ramp offset voltage
(VPWM(OFFSET)).
At the beginning of each PWM cycle, the CLK signal sets the
PWM flip-flop, the bottom MOSFET is turned off, the top MOSFET is turned on, and the inductor current increases. When the
voltage at the non-inverting of PWM comparator rises above the
error amplifier’s output COMP, the PWM flip flop is reset and the
top MOSFET is turned off, the bottom MOSFET is turned on and
the inductor current decreases.
The PWM flip-flop is reset dominant, so the error amplifier may
override the CLK signal in certain situations.
BOOT Regulator
The A8654 includes a regulator to charge its boot capacitor. The
voltage across the BOOT capacitor is typically 5.0 V. If the boot
capacitor is missing the A8654 will detect a boot overvoltage.
Similarly, if the boot capacitor is shorted the A8654 will detect a
boot undervoltage. Also, the boot regulator has a current limit to
protect itself during a short-circuit condition.
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115 Northeast Cutoff
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12
A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
Soft-Start (Startup) and Inrush Current Control
The soft-start function controls the inrush current at startup. The
soft-start pin (SS) is connected to GND via a capacitor. When
the A8654 is enabled and all faults are cleared, the soft-start pin
will source the charging current ISS(SU) and the voltage on the
soft-start capacitor CSS will ramp upward from 0 V. When the
voltage at the soft-start pin exceeds the Soft-Start COMP Release
Threshold (VSS(RELEASE), typically 400 mV), the error amplifier
will ramp up its output voltage above the PWM Ramp Offset. At
that instant, the top and bottom MOSFETs will begin switching.
There is a small delay (tSS(DELAY)) between the moments of EN
pin transitioning high and the soft-start voltage reaching 400 mV
to initiate PWM switching.
Once the A8654 begins PWM switching, the error amplifier will
regulate the voltage at the FB pin to the soft-start pin voltage
minus approximately 400 mV. During the active portion of softstart, the voltage at the SS pin will rise from 400 mV to 1.2 V (a
difference of 800 mV), the voltage at the FB pin will rise from
0 V to 800 mV, and the regulator’s output voltage will rise from
0 V to the setpoint determined by the feedback resistor divider.
During startup, the PWM switching frequency is reduced to
25% of fSW while FB is below 200 mV. If FB is above 200 mV
but below 400 mV, the switching frequency is 50% of fSW. At
the same time, the transconductance of the error amplifier, gm,
is reduced to 1/2 of nominal value when FB is below 400 mV.
When FB is above 400 mV the switching frequency will be fSW
and the error amplifier’s gain will be the nominal value. The
reduced switching frequencies and error amplifier’s gain are necessary to help improve output regulation and stability when VOUT
is at very low voltage. When VOUT is very low, the PWM control
loop requires on-time near the minimum controllable on-time and
extra low duty cycles that are not possible at the nominal switching frequency.
When the voltage at the soft-start pin reaches approximately
1.2 V the error amplifier will “switch over” and begin regulating
the voltage at the FB to A8654’s adjusted reference voltage. The
voltage at the soft-start pin will continue to rise to the internal
LDO regulator’s output voltage.
If the A8654 is disabled or a fault occurs, the internal fault latch
is set and the capacitor at the SS pin is discharged to ground very
quickly through a 2 kΩ pull-down resistor. The A8654 will clear
the internal fault latch when the voltage at the SS pin decays to
approximately 200 mV. However, if the A8654 enters hiccup
mode, the capacitor at the SS pin is slowly discharged through a
current sink, ISS(HIC). Therefore, the soft-start capacitor CSS not
only controls the startup time but also the time between soft-start
attempts in hiccup mode.
Pre-Biased Startup
If the output of the buck regulator is pre-biased at a certain
output voltage level, the A8654 will modify the normal startup
routine to prevent discharging the output capacitors. As described
in the Soft-Start (Startup) and Inrush Current Control section,
the error amplifier usually becomes active when the voltage at
the soft-start pin exceeds 400 mV. If the output is pre-biased,
the voltage at the FB pin will be non-zero. The A8654 will not
start switching until the voltage at SS pin rises to approximately
VFB + 400 mV. From then on, the error amplifier becomes active,
the voltage at the COMP pin rises, PWM switching starts, and
VOUT will ramp upward from the pre-bias level.
Not Power-On Reset (NPOR) Output
The A8654 has an inverted Power-On Reset output (NPOR) with
a fixed delay of its rising edge (td(NPOR)). The NPOR output is an
open-drain output so an external pull-up resistor must be used,
as shown in the applications schematic. NPOR transitions high
when the output voltage, sensed at the FB pin, is within regulation. The NPOR over- and undervoltage comparators incorporate
a small amount of hysteresis (see EC table) and filtering (5 µs,
typical) to help reduce chattering due to the voltage ripple at the
FB pin.
The NPOR output is immediately pulled low if either an underor overvoltage condition occurs or the A8654’s junction temperature exceeds the thermal shutdown threshold (TSD). For other
faults, NPOR depends on the output voltage. Table 2 summarizes
all the A8654 fault modes and their effects on NPOR.
At power-up, NPOR must be initialized (set to a logic low) when
VIN is relatively low. At power-down, NPOR must be held in the
logic-low state as long as possible.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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13
A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
PROTECTION FEATURES
The A8654 was designed to satisfy the most demanding automotive and nonautomotive applications. In this section, a description
of each protection feature is described and Table 2 summarizes
the protections and their operation.
5.4
5.2
5.0
4.8
Undervoltage Lockout Protection (UVLO)
4.4
ILIM (A)
An Undervoltage Lockout (UVLO) comparator in the A8654
monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the START threshold (VUVLO(START),
VIN rising) or the STOP threshold (VUVLO(STOP), VIN falling).
The UVLO comparator incorporates some hysteresis VUVLO(HYS)
to help reduce on/off cycling of the regulator due to the resistive
or inductive drops in the VIN path during heavy loading or during startup.
4.6
4.2
4.0
MAX_550 kHz
3.8
TYP_550 kHz
3.6
MIN_550 kHz
MAX_100 kHz
3.4
TYP_100 kHz
MIN_100 kHz
3.2
MAX_2 MHz
3.0
TYP_2 MHz
MIN_2 MHZ
2.8
Pulse-by-Pulse Overcurrent Protection (OCP)
The A8654 monitors the current in the upper MOSFET, and if this
current exceeds the pulse-by-pulse overcurrent threshold, then the
upper MOSFET is turned off. Normal PWM operation resumes
on the next clock pulse from the oscillator. The A8654 includes
leading-edge blanking to prevent falsely triggering the pulse-bypulse current limit when the upper MOSFET is turned on.
Because of the addition of the slope compensation ramp to the
inductor current, the A8654 can deliver more current at lower
duty cycles than at higher duty cycles to activate pulse-by-pulse
overcurrent protection. Also, the slope compensation is not a perfectly linear function of switching frequency, so the current limit
at lower switching frequency is larger compared with the limit at
higher switching frequency for a given duty cycle.
Figure 2 shows the typical and worst-case pulse-by-pulse current
limits versus duty cycles at 2 MHz, 550 kHz, and 100 kHz.
The exact current the buck regulators can support is heavily
dependent on duty cycle (VIN, VOUT), ambient temperature,
thermal resistance of the PCB, airflow, component selection, and
nearby heat sources.
Overcurrent Protection (OCP) and Hiccup
Mode
An OCP counter and hiccup mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when
the load current is too high.
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Duty Cycle (%)
Figure 2: Pulse-by-Pulse Current Limit vs. Duty Cycle
at 100 kHz (long dashed lines), 550 kHz (solid lines) and 2 MHz (short
dashed lines)
When the voltage at the SS pin is below the Hiccup OCP Threshold, the hiccup mode counter is disabled. Two conditions must be
met for the OCP counter to be enabled and begin counting:
1. VSS > VHIC(EN) (2.3 V) and
2. VCOMP clamped at its maximum voltage (OCL = 1)
As long as these two conditions are met, the OCP counter
remains enabled and will count pulses from the overcurrent
comparator. If the COMP voltage decreases (OCL = 0), the OCP
counter is cleared. If the OCP counter reaches OCPLIM counts
(240), a hiccup latch is set and the COMP pin is quickly pulled
down by a relatively low resistance (1 kΩ).
The hiccup latch also enables a small current sink connected to
the SS pin (ISS(HIC)). This causes the voltage at the soft-start pin
to slowly ramp downward. When the voltage at the soft-start pin
decays to a low-enough level (VSS(RST), 200 mVTYP) the hiccup latch is cleared and the small current sink turned off. At that
instant, the SS pin will begin to source current (ISS(SU)) and the
voltage at the SS pin will ramp upward. This marks the beginning of a new, normal soft-start cycle as described earlier. When
the voltage at the soft-start pin exceeds the error amp voltage
by approximately 400 mV, the error amp will force the voltage
at the COMP pin to quickly slew upward and PWM switching
will resume. If the short circuit at the regulator’s output remains,
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14
A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
another hiccup cycle will occur. Hiccups will repeat until the
short circuit is removed or the converter is disabled. If the short
circuit is removed, the A8654 will soft-start normally and the
output voltage will automatically recover to the desired level.
Thus, hiccup mode is a very effective protection for the overload
condition. It can avoid false trigger for a short-term overload. On
the other hand, for the extended overload, the average power dissipation during hiccup operation is very low to keep the controller cool and enhance the reliability.
Note that OCP is the only fault that results in hiccup mode being
ignored while VSS < 2.3 V.
BOOT Capacitor Protection
The A8654 monitors the voltage across the BOOT capacitor to
detect if the capacitor is missing or short-circuited. If the BOOT
capacitor is missing, the regulator will enter hiccup mode after 7
PWM cycles. If the BOOT capacitor is short-circuited, the regulator will enter hiccup mode after 64 PWM cycles.
For a BOOT fault, hiccup mode will operate virtually the same as
described previously for an output short-circuit fault (OCP), with
SS ramping up and down as a timer to initiate repeated soft-start
attempts. BOOT faults are nonlatched conditions, so the A8654
will automatically recover when the fault is corrected.
Overvoltage Protection (OVP)
The A8654 also includes an overvoltage comparator that monitors the FB pin exceeding 110%. When the voltage at the FB pin
exceeds the overvoltage threshold (VOUT(OV)), A8654 will stop
PWM switching, i.e. both high- and low-side switches will be
turned off, and NPOR will be pulled low.
In most cases, the error amplifier will be able to maintain regulation since the synchronous output stage has excellent sink and
source capability. However the error amplifier and its regulation
voltage clamp are not effective when the FB pin is disconnected
or when the output is shorted to the input supply. When the FB
pin is disconnected from the feedback resistor divider, a tiny
internal current source will force the voltage at the FB pin to rise
above VOUT(OV) and disable the regulator, preventing the load
from being significantly overvoltage. If a higher external voltage
is accidently shorted to the A8654’s output, VFB will rise above
the overvoltage threshold, triggering an OVP event and thus
protecting the low-side switch. In either case, if the conditions
causing the overvoltage are corrected, the regulator will automatically recover.
Thermal Shutdown (TSD)
The A8654 monitors its junction temperature and will stop PWM
switching and pull NPOR low if it becomes too hot. Also, to
prepare for a restart, the SS and COMP pins will be pulled low
until VSS < VSS(RST). TSD is a nonlatched fault, so the A8654 will
automatically recover if the junction temperature decreases by
approximately 20°C.
Pin-to-Ground and Pin-to-Pin Short Protections
The A8654 was designed to satisfy the most demanding automotive and nonautomotive applications. For example, the A8654
was carefully designed “up front” to withstand a short circuit to
ground at each pin without suffering damage.
In addition, care was taken when defining the A8654’s pinout
to optimize protection against pin-to-pin adjacent short circuits.
For example, logic pins and high voltage pins were separated as
much as possible. Inevitably, some low-voltage pins were located
adjacent to high-voltage pins. In these instances, the low-voltage
pins were designed to withstand increased voltages, with clamps
and/or series input resistance, to prevent damage to the A8654.
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115 Northeast Cutoff
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15
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
Table 1: Summary of A8654 Fault Modes and Operation
During Fault Count, before Hiccup
Dropout
Foldback
NPOR
BOOT
Charging
LATCH
RESET
CCM
according to
COMP
fSW/4 or fSW/2
based on VFB
Depends on
VOUT
Not
affected
No
Auto,
remove
short
Forced Off
Immediately
Forced off
Immediately
Dropout
Foldback
Reset
Depends on
VOUT
Not
affected
No
Auto,
remove
short
Pulled low only by
hiccup
Forced Off
Immediately
One Shot
Diode
Emulation
Dropout
Foldback
Reset
Depends on
VOUT
Not
affected
No
(option
avail
able)
Auto,
remove
short
Die is too hot
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Forced Off
Immediately
Forced off
Immediately
Dropout
Foldback
Reset
Pulled Low
Immediately
Off
No
Auto,
Cool
Down
Boot
Capacitor
Greater than
7.0 V
BOOT capacitor
Open
Hiccup, after 7
latched faults
Pulled low by
hiccup
CCM
according to
COMP
CCM
according to
COMP
Dropout
Foldback
Disabled by
Hiccup
Depends on
VOUT
Off for rest
of period
–
–
Boot
Capacitor On
Fault
BOOT Capacitor
Open
Hiccup, after 7
latched faults
Pulled low by
hiccup
CCM
according to
COMP
CCM
according to
COMP
Dropout
Foldback
Disabled by
Hiccup
Depends on
VOUT
Off only
during
hiccup
No
Auto,
replace
capacitor
Boot
Capacitor
Overcurrent
BOOT to GND
Short
Not affected
Not affected
Not affected
Pulsed at
minOff
Not affected
Depends on
VOUT
Off until
fault clears
–
–
Boot
Capacitor
Low Voltage
Normal Low VIN
Operation
Not affected
Not affected
Not affected
Active during
minOff period
Not affected
Depends on
VOUT
On
–
–
Boot
Capacitor
Undervoltage
BOOT Capacitor
Short
Not affected
Not affected
Forced Off
Immediately
Active during
minOff period
Dropout
Foldback
Reset
Depends on
VOUT
On
–
–
Low Side
Switch
Undervoltage
Low VIN
Not affected
Not affected
Forced Off
Immediately
Forced Off
Immediately
Dropout
Foldback
Reset
Depends on
VOUT
Not
affected
–
–
VREG
Undervoltage
Low VIN
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Forced Off
Immediately
Forced Off
Immediately
Dropout
Foldback
Reset
Pulled Low
Immediately
Off
No
Auto
VIN
Undervoltage
Low VIN
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Forced Off
Immediately
One Shot
Diode
Emulation
Dropout
Foldback
Reset
Depends on
VOUT
Off
No
Auto
Fault Mode
Fault Cases
VSS
Positive
Overcurrent
Protection
1. Excessive IOUT
2. VOUT Shorted
to GND
3. SW Soft Short
To GND
Negative
Overcurrent
Protection
SW Hard
Short to GND
VCOMP
High-Side
Switch
Low-Side
Switch
Hiccup, after 240
faults of OCL
Clamped to
achieve ILIM, and
pulled low only by
hiccup
CCM
according to
COMP
1. Excessive
Negative IOUT
2. Inductor Short
Hiccup, after 1
fault of LSOC
Pulled low only by
hiccup
SW to GND hard
Short
Hiccup at the
end of blankOn
Thermal
Shutdown
Continued on next page...
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16
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
Table 1: Summary of A8654 Fault Modes and Operation (continued)
During Fault Count, before Hiccup
Fault Mode
Hiccup Delay
(after fault
count is
reached)
Hiccup
Restart or
Startup (after
VSS returns to
VSS(RST))
FB
Overvoltage
Fault Cases
Hiccup
StartupHiccup
1. VOUT to VIN
Short
2. FB Pin Open
VSS
VCOMP
High-Side
Switch
Low-Side
Switch
Dropout
Foldback
NPOR
BOOT
Charging
LATCH
RESET
–
–
–
–
No
Auto,
VFB to
normal
range
Discharged with
ISS(HIC) until VSS
< VSS(RST)
Pulled Low until
VSS < VSS(RST)
Forced Off at
Start of Period
One Shot
Diode
Emulation
Dropout
Foldback
Reset
Depends on
VOUT
Not
affected, (off
only for boot
capacitor
faults)
(sleep
option
available)
Charged with
ISS(SU)
Released
from 0 V, then
responds to VSS↑
CCM after
VCOMP >
400 mV
CCM after
VCOMP >
400 mV
(pulsed at
minOff)
Dropout
Foldback
Reset
Depends on
VOUT
Not
affected
Not affected
Forced Off
Immediately
One Shot
Diode
Emulation
Dropout
Foldback
Reset
Pulled Low
Immediately
Off
CCM
according to
COMP
Not affected
Pulled Low
Immediately
Not
affected
No
Auto,
VFB to
normal
range
Not affected
FB
Undervoltage
Startup
Not affected
Not affected
CCM
according to
COMP
Feedback
Less Than
400 mV
Startup
Not affected
Not affected
fSW/2
CCM
according to
COMP
Not affected
Pulled Low
Not
affected
–
–
Feedback
Less Than
200 mV
StartupVOUT to
GND Short
Not affected
Not affected
fSW/4
CCM
according to
COMP
fSW already
at 1/4
Pulled Low
Not
affected
–
–
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Pulled Low
Immediately &
latched until VSS
< VSS(RST)
Forced Off
Immediately
One Shot
Diode
Emulation
Not affected
Depends on
VOUT
Off
–
–
FSET
Resistor Fault
1.FSET to GND
short
2.FSET pulled
high
3.Low R
4.High R
SS shorted
to VIN
SS to VIN short
Clamped to
zener voltage
internally
Not affected
CCM
according to
COMP
CCM
according to
COMP
Not affected
Depends on
VOUT
Not
affected
–
–
SS shorted to
GND
SS to GND short
At GND
Loop response
only
CCM
according to
COMP
CCM
according to
COMP
Not affected
Depends on
VOUT
Not
affected
–
–
COMP
shorted to
GND
COMP to GND
short
Not affected
At GND
CCM
according to
COMP
CCM
according to
COMP
Not affected
Depends on
VOUT
Not
affected
–
–
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17
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
DESIGN AND COMPONENT SELECTION
Setting the Output Voltage
2.0 × 103
1.6 × 10
3
1.4 × 10
3
1.2 × 103
1 × 10
3
800
600
400
CFB
FB Pin
1.8 × 103
Frequency (kHz)
The output voltage of the regulator is determined by connecting
a resistor divider from the output node (VOUT) to the FB pin as
shown in Figure 3. There are trade-offs when choosing the value
of the feedback resistors. If the series combination (RFB1 + RFB2)
is too low, then the light load efficiency of the regulator will
be reduced. So, to maximize the efficiency, it is best to choose
higher values of resistors. On the other hand, if the parallel
combination (RFB1//RFB2) is too high, then the regulator may be
susceptible to noise coupling onto the FB pin. 1% resistors are
recommended to maintain the output voltage accuracy.
200
VOUT
0
10
RFB1
20
30
40
50
60
70
80
90 100 110 120 130 140 150 160
RFSET (kΩ)
RFB2
Figure 4: PWM Switching Frequency versus RFSET
Figure 3: Connecting a Feedback Divider to Set the
Output Voltage
The feedback resistors must satisfy the ratio shown in equation 1
below to produce a desired output voltage (VOUT).
VOUT
RFB1
–1
RFB2 = 0.8 V
(1)
A phase lead capacitor (CFB) can be connected in parallel with
RFB1 to increase the phase and gain margins. It adds an additional
zero and pole to the compensation network and boosts the loop
phase at the crossover frequency. In general, CFB should be less
than 25 pF. If CFB is too large, it will have no effect.
If CFB is used, CFB can be calculated from equation 2:
CFB =
1
2πRFB1fc
(2)
where fc is crossover frequency.
PWM Switching Frequency (fSW, RFSET)
The PWM switching frequency is set by connecting a resistor
from the FSET pin to ground. Figure 4 is a graph showing the
relationship between the typical switching frequency (y-axis) and
the FSET resistor RFSET (x-axis).
For a desired switching frequency (fSW), the FSET resistor can be
calculated using equation 3, where fSW is in kHz and RFSET is in
kΩ.
RFSET =
26000
– 2.2
fSW
(3)
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable on-time, tON(MIN)
of the A8654. If the system’s required on-time is less than the
minimum controllable on-time, pulse skipping will occur and
the output voltage will have increased ripple or oscillations. The
PWM switching frequency should be calculated using equation 4,
where VOUT is the output voltage, tON(MIN) is the minimum
controllable on-time of the A8654 (See EC table), and VIN(MAX)
is the maximum required operational input voltage (not the peak
surge voltage).
fSW <
VOUT
tON(MIN) × VIN(MAX)
(4)
If the A8654 synchronization function is employed, the base
switching frequency should be chosen such that pulse skipping
will not occur at the maximum synchronized switching frequency
according to equation 4 (i.e. 1.5 × fSW is less than the result from
equation 4).
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Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
Output Inductor (LO)
Output Capacitors
For a peak current-mode regulator, it is common knowledge that
without adequate slope compensation, the system will become
unstable when the duty cycle is near or above 50%. However, the
slope compensation in the A8654 is a fixed value (SE). Therefore,
it is important to calculate an inductor value so the falling slope
of the inductor current (SF) will work well with the A8654’s
slope compensation. Equations 5 and 6 can be used to calculate a
range of values for the output inductor based on the well-known
approach of providing slope compensation that matches 50% to
100% of the down slope of the inductor current. In equation 5,
use the slope compensation (SE ), which is a function of switching frequency according to equation 6.
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage, and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin. The output voltage ripple (ΔVOUT)
is a function of the output capacitors parameters: CO, ESRCO,
ESLCO.
VOUT
VOUT
≤
L
O ≤
2 × SE
SE
2
SE = 0.0445 × fSW + 0.5612 × fSW
(5)
(6)
VOUT = IL × ESRCO +
IL
VIN – VOUT
× ESLCO +
LO
8fSWCO
The type of output capacitors will determine which terms of
equation 9 are dominant.
For ceramic output capacitors, the ESRCO and ESLCO are virtually zero so the output voltage ripple will be dominated by the
third term of equation 9.
VOUT =
SE is in A/µs, fSW is in MHz, and LO will be in µH
(9)
IL
8fSWCO
(10)
If equations 5 or 6 yield an inductor value that is not a standard
value, then the next highest available value should be used. The
final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation.
To reduce the voltage ripple of a design using ceramic output
capacitors, simply increase the total capacitance, reduce the
inductor current ripple (i.e. increase the inductor value), or
increase the switching frequency.
The saturation current of the inductor should be higher than the
peak current capability of the A8654. Ideally, for output shortcircuit conditions, the inductor should not saturate at the highest
pulse-by-pulse current limit at minimum duty cycle; this may be
too costly. At the very least, the inductor should not saturate at
the peak operating current according to equation 7. In equation 7
VIN(MAX) is the maximum continuous input voltage.
For electrolytic output capacitors, the value of capacitance will be
relatively high, so the third term in equation 9 will be very small
and the output voltage ripple will be determined primarily by the
first two terms of equation 9.
IPEAK = 5.3 –
SE × VOUT
1.15 × fSW × VIN(MAX)
(7)
Subtracting half of the inductor ripple current from equation 7
gives an interesting equation to predict the typical DC load capability of the regulator at a given duty cycle (D),
S ×D
V × (1 – D)
IOUT(DC) ≤ 5.3 – E
– OUT
fSW
2 × fSW × LO
(8)
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure neither
the inductor nor the regulator are damaged when the output is
shorted to ground at maximum input voltage and the highest
expected ambient temperature.
VOUT = IL × ESRCO +
VIN – VOUT
× ESLCO
LO
(11)
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply decrease the equivalent ESRCO and ESLCO
by using a high(er) quality capacitor, or add more capacitors in
parallel, or reduce the inductor current ripple (i.e. increase the
inductor value).
The ESR of some electrolytic capacitors can be quite high, so
Allegro recommends choosing a quality capacitor for which the
ESR or the total impedance is clearly documented in the datasheet. Also, the ESR of electrolytic capacitors usually increases
significantly at cold ambients, as much as 10×, which increases
the output voltage ripple and in most cases reduces the stability
of the system.
The transient response of the regulator depends on the quantity
and type of output capacitors. In general, minimizing the ESR of
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the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount
di
(12)
ESLCO
VOUT = ILOAD × ESRCO +
dt
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. This time will depend
on the system bandwidth, the output inductor value, and output
capacitance. Eventually, the error amplifier will bring the output
voltage back to its nominal value.
The speed at which the error amplifier will bring the output
voltage back to its setpoint mainly depends on the closed-loop
bandwidth of the system. A higher bandwidth usually results in
a shorter time to return to the nominal voltage. However, with
a higher bandwidth system it may be more difficult to obtain
acceptable gain and phase margins. Selection of the compensation components (RZ, CZ, CP) are discussed in more detail in the
Compensation Components section of this datasheet.
Input Capacitors
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input surge voltage with adequate design margin.
Second, the capacitor RMS current rating must be higher than
the expected RMS input current to the regulator. Third, they must
have enough capacitance and a low enough ESR to limit the input
voltage dV/dt to something much less than the hysteresis of the
VIN pin UVLO circuitry (VUVLO(HYS), nominally 800 mV for the
A8654) at maximum loading and minimum input voltage.
The input capacitors must deliver the RMS current according to:
IRMS = IO D × (1 – D)
(13)
where the duty cycle D is D ≈ VOUT / VIN. Figure 5 shows the
normalized input capacitor RMS current versus duty cycle. To
use this graph, simply find the operational duty cycle (D) on the
x-axis and determine the input/output current multiplier on the
y-axis. For example, at a 20% duty cycle, the input/output current
multiplier is 0.40. Therefore, if the regulator is delivering 3.0 A of
steady-state load current, the input capacitor(s) must support 0.40
× 3.0 A or 1.2 ARMS.
IRMS / IOUT
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
10
20
30
60
40
50
Duty Cycle (%)
70
80
90
100
Figure 5: Input Capacitor Ripple vs. Duty Cycle
The input capacitor(s) must limit the voltage deviations at the
VIN pin to something significantly less than the A8654’s UVLO
hysteresis during maximum load and minimum input voltage.
The minimum input capacitance can be calculated as follows:
CIN ≥
IOUT × D × (1 – D)
0.85 × fSW × ΔVIN(MIN)
(14)
Where ΔVIN(MIN) is chosen to be much less than the hysteresis
of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recommended), and fSW is the nominal PWM frequency.
The D × (1 – D) term in equation 13 has an absolute maximum
value of 0.25 at 50% duty cycle. So, for example, a very conservative design based on IOUT = 3.0 A, fSW = 85% of 425 kHz,
D × (1 – D) = 0.25, and ΔVIN = 150 mV,
CIN ≥
3.0 A × 0.25
= 14 µF
361 kHz × 150 mV
A good design should consider the DC bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction) so these types should be avoided. The X5R and
X7R type capacitors should be the primary choices due to their
stability versus both DC bias and temperature.
For all ceramic capacitors, the DC bias effect is even more
pronounced on smaller case sizes, so a good design will use the
largest affordable case size (i.e. 1206 or 1210). Also, it is advisable to select input capacitors with plenty of design margin in
the voltage rating to accommodate the worst-case transient input
voltage (such as a load dump as high as 40 V for automotive
applications).
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Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
Bootstrap Capacitor
A bootstrap capacitor must be connected between the BOOT and
SW pins to provide the floating gate drive to the high-side MOSFET. Usually, 100 nF is an adequate value. This capacitor should
be a high-quality ceramic capacitor, such as an X5R or X7R, with
a voltage rating of at least 16 V.
Soft-Start and Hiccup Mode Timing (CSS)
The soft-start time of the A8654 is determined by the value of the
capacitance at the soft-start pin (CSS).
When the A8654 is enabled, the voltage at the soft-start pin
will start from 0 V and will be charged by the soft-start current
(ISS(SU)). However, PWM switching will not begin instantly
because the voltage at the soft-start pin must rise above 400 mV.
The soft-start delay (tSS(DELAY)) can be calculated using equation
below,
tSS(DELAY) = C SS ×
(
400 mV
ISS(SU)
)
(15)
If the A8654 is starting with a very heavy load, a very fast softstart time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. This occurs because the sum of the full
load current, the inductor ripple current, and the additional current required to charge the output capacitors
ICO = CO × VOUT / tSS
is higher than the pulse-by-pulse current threshold, as shown in
Figure 6. This phenomena is more pronounced when using high
value electrolytic type output capacitors.
}
ILIM
ILOAD
Output
Capacitor
Current (ICO)
tSS
Figure 6: Output Current (ICO) During Startup
To avoid prematurely triggering hiccup mode, the soft-start
capacitor (CSS) should be calculated according to equation below,
CSS ≥
ISS(SU) × VOUT × CO
0.8 V × ICO
(16)
where VOUT is the output voltage, CO is the output capacitance,
ICO is the amount of current allowed to charge the output capacitance during soft-start (recommend 0.1 A < ICO < 0.3 A). Higher
values of ICO result in faster soft-start times. Howewer, lower
values of ICO ensure that hiccup mode is not falsely triggered.
Allegro recommends starting the design with an ICO of 0.1 A and
increasing it only if the soft-start time is too slow. If a non-standard capacitor value for CSS is calculated, the next larger value
should be used.
The output voltage ramp time (tSS) can be calculated by using
either of the following methods:
COUT
CSS
tSS = VOUT × I or 0.8 V × I
CO
SS(SU)
(17)
When the A8654 is in hiccup mode, the soft-start capacitor is
used as a timing capacitor and sets the hiccup period. The softstart pin charges the soft-start capacitor with ISS(SU) during a
startup attempt and discharges the same capacitor with ISS(HIC)
between startup attempts. Because the ratio of ISS(SU)/ISS(HIC) is
approximately 4:1, the time between hiccups will be about four
times as long as the startup time. Therefore, the effective duty
cycle will be very low and the junction temperature will be kept
low.
Compensation Components (RZ, CZ, CP)
To compensate the system, it is important to understand where
the buck power stage, load resistance, and output capacitance
form their poles and zeros in frequency. Also, it is important
to understand that the (Type II) compensated error amplifier
introduces a zero and two more poles and where these should be
placed to maximize the system’s stability, provide a high bandwidth, and optimize the transient response.
First, consider the power stage of the A8654, the output capacitors, and the load resistance. This circuitry is commonly referred
as the “control to output” transfer function. The low frequency
gain of this section depends on the COMP to SW current gain
(gmPOWER), and the value of the load resistor (RL). The DC gain
(GCO(0HZ)) of the control-to-output is:
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Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
GCO(0Hz) = gmPOWER × RL
(18)
The control to output transfer function has a pole (fP1) formed by
the output capacitance (COUT) and load resistance (RL) at:
fP1 =
1
2π × RL × COUT
(19)
The control to output transfer function also has a zero (fZ1)
formed by the output capacitance (COUT) and its associated ESR
fZ1 =
1
2π × ESR × COUT
(20)
For a design with very low-ESR type output capacitors (i.e.
ceramic or OSCON output capacitors), the ESR zero, fZ1, is
usually at a very high frequency, so it can be ignored. On the
other hand, if the ESR zero falls below or near the 0 dB crossover
frequency of the system (as is the case with electrolytic output
capacitors), then it should be cancelled by the pole formed by the
CP capacitor and the RZ resistor (discussed and identified later as
fP3).
Next, consider the feedback resistor divider, (RFB1 and RFB2),
the error amplifier (gm), and its compensation network RZCZ-CP. It greatly simplifies the transfer function derivation if
RO ≫ RZ, and CZ ≫ CP (where RO is the error amplifier output
impedance). In most cases, RO > 2 MΩ, 1 kΩ < RZ < 100 kΩ,
220 pF < CZ < 47 nF, and CP < 50 pF, so the following equations
are very accurate.
The low frequency gain of the control section (GC(0Hz)) is formed
by the feedback resistor divider and the error amplifier. It can be
calculated using equation 21:
RFB2
× gm× R O
RFB1 + RFB2
VFB
=
× gm× R O
VOUT
VFB
=
× A VOL
VOUT
GC(0Hz ) =
(21)
where
VOUT is the output voltage,
VFB is the reference voltage (0.8 V),
gm is the error amplifier transconductance (750 µA/V), and
RO is the error amplifier output impedance (AVOL/gm).
The transfer function of the Type-II compensated error amp
has a (very) low frequency pole (fP2) dominated by the output
error amplifier’s output impedance RO and the CZ compensation
capacitor,
fP2 =
1
2π × RO × CZ
(22)
The transfer function of the Type-II error amp also has a low
frequency zero (fZ2) dominated by the RZ resistor and the CZ
capacitor.
fZ2 =
1
2π × RZ × CZ
(23)
Lastly, the transfer function of the Type-II compensated error
amp has a (very) high frequency pole (fP3) dominated by the RZ
resistor and the CP capacitor
fP3 =
1
2π × RZ × CP
(24)
Placing fZ2 just above fP1 will result in excellent phase margin,
but relatively slow transient recovery time.
The magnitude and phase of the entire system are simply the sum
of the error amp response and the control-to-output response.
A Generalized Tuning Procedure
1. Choose the system bandwidth, fC, the frequency at which the
magnitude of the gain will cross 0 dB. Recommended values
for fC based on the PWM switching frequency are fSW/20
< fC < fSW/7.5. A higher value of fC will generally provide
a better transient response while a lower value of fC will be
easier to obtain higher gain and phase margins.
2. Calculate the RZ resistor value to set the desired system
bandwidth (fC),
VOUT 2 × π × COUT
RZ = fC ×
×
(25)
VFB
gmPOWER × gm
3. Determine the frequency of the pole (fP1) formed by COUT
and RL by using equation 19 (repeated here).
1
fP1 =
2π × RL × COUT
4. Calculate a range of values for the CZ capacitor,
4
1
< CZ <
2 × π × RZ × fC
2 × π × RZ × 1.5 × fP1
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22
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
To maximize system stability (i.e. have the most gain margin), use a higher value of CZ. To optimize transient recovery
time at the expense of some phase margin, use a lower value
of CZ.
5. Calculate the frequency of the ESR zero (fZ1) formed by the
output capacitor(s) by using equation 20 (repeated here).
1
fZ1 =
2π × ESR × COUT
A.If fZ1 is at least 1 decade higher than the target crossover
frequency (fC), then fZ1 can be ignored. This is usually
the case for a design using ceramic output capacitors. Use
equation 24 to calculate the value of CP by setting fP3 to
either 5 × fC or fSW/2, whichever is higher.
B. On the other hand, if fZ1 is near or below the target
crossover frequency (fC) then use equation 24 to calculate
the value of CP by setting fP3 equal to fZ1. This is usually
the case for a design using high ESR electrolytic output
capacitors.
Referring to Typical Application Diagram on the front page, several typical designs are provided in Table 2 for A8654.
Table 2: Recommended Components Values for Three Typical Designs
fSW
VOUT
RFSET
LO
CO
RZ + CZ // CP
RFB1
RFB2
500 kHz
5.0 V
52.3 kΩ
10 µH (74437368100)
44 µF
14 kΩ + 2.7 nF/33 pF
24.9 kΩ
4.75 kΩ
1 MHz
3.3 V
23.7 kΩ
6.8 µH (74437368068)
44 µF
14 kΩ + 2.2 nF/15 pF
16.5 kΩ
5.23 kΩ
2 MHz
5.0 V
10.5 kΩ
6.8 µH (74437368068)
32 µF
37.4 kΩ + 1.8 nF/4.7 pF
24.9 kΩ
4.75 kΩ
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Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
POWER DISSIPATION AND THERMAL CALCULATIONS
The power dissipated in the A8654 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated
due to the switching of the high-side power MOSFET (PSW1), the
power dissipated due to the RMS current being conducted by the
high-side MOSFET (PCOND1) and low-side MOSFET (PCOND2),
and the power dissipated by both gate drivers (PDRIVER).
The power dissipated from the VIN supply current can be calculated using equation 27,
PIN = VIN × IQ + (VIN – VGS ) × (QG1 + QG2 ) × fSW
(27)
Similarly, the conduction losses dissipated by the low-side MOSFET while it is conducting can be calculated by the following
equation:
PCOND2 = I
(
1–
RMS(FET) × R DS(ON)LS =
2
)(
)
VOUT
ΔI
2
× I OUT + L × R DS(ON)LS
VIN
12
(30)
2
where
IOUT is the regulator output current,
ΔIL is the peak-to-peak inductor ripple current,
where
RDS(ON)HS is the on-resistance of the high-side MOSFET,
VIN is the input voltage,
IQ is the input quiesent current drawn by the A8654 (see EC
table),
VGS is the MOSFET gate drive voltage (typically 5 V),
QG1 and QG2 is the internal high-side and low-side MOSFET
gate charges (approximately 5.8 nC and 10.4 nC, respectively), and
fSW is the PWM switching frequency.
The power dissipated by the high-side MOSFET during PWM
switching can be calculated using equation 28,
VIN × IOUT × (tr + tf ) × fSW
PSW1 =
2
(28)
where
RDS(ON)LS is the on-resistance of the low-side MOSFET
The RDS(ON) of both MOSFETs have some initial tolerance plus
an increase from self-heating and elevated ambient temperatures.
A conservative design should accomodate an RDS(ON) with at
least a 15% initial tolerance plus 0.39%/°C increase due to temperature.
The power dissipated from the low-side MOSFET body diode
during the non-overlap time can be calculated as follows:
PNO = VSD × IOUT × 2 × tNO × fSW (31)
where
VSD is the source-to-drain voltage of the low-side MOSFET
(typically 0.60 V), and
tNO is the non-overlap time (15 ns(typ))
VIN is the input voltage,
IOUT is the regulator output current,
The sum of the power dissipated by the internal gate driver can be
calculated using equation 32,
fSW is the PWM switching frequency, and
tr and tf are the rise and fall times measured at the SW node.
where
The exact rise and fall times at the SW node will depend on the
external components and PCB layout, so each design should be
measured at full load. Approximate values for both tr and tf range
from 10 to 20 ns.
The power dissipated by the high-side MOSFET while it is conducting can be calculated using equation 29,
PCOND1 = I
2
RMS,FET
× R DS(ON)HS =
VOUT
I
2
× I OUT + L × R DS(ON)HS
VIN
12
(29)
( )(
2
)
PDRIVER = (QG1 + QG2) × VGS × fSW
(32)
VGS is the gate drive voltage (typically 5 V),
QG1 and QG2 is the gate charges to drive high-side and
low-side MOSFETs to VGS = 5 V (about 5.8 nC and 10.4 nC
respectively), and
fSW is the PWM switching frequency.
Finally, the total power dissipated by the A8654 (PTOTAL) is the
sum of the previous equations,
PTOTAL = PIN + PSW1 + PCOND1 + PCOND2 + PNO + PDRIVER (33)
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Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
The average junction temperature can be calculated with the
equation below,
TJ = PTOTAL × RθJA + TA
(34)
where
PTOTAL is the total power dissipated from equation 33,
RθJA is the junction-to-ambient thermal resistance (34°C/W
on a 4-layer PCB), and
TA is the ambient temperature.
The maximum junction temperature will be dependent on how
efficiently heat can be transferred from the PCB to the ambient air. It is critical that the thermal pad on the bottom of the IC
should be connected to at least one ground plane using multiple
vias.
As with any regulator, there are limits to the amount of heat that
can be dissipated before risking thermal shutdown. There are
trade-offs between ambient operating temperature, input voltage,
output voltage, output current, switching frequency, PCB thermal
resistance, airflow, and other nearby heat sources. Even a small
amount of airflow will reduce the junction temperature considerably.
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A8654
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
PCB COMPONENT PLACEMENT AND ROUTING
A good PCB layout is critical for the A8654 to provide clean,
stable output voltages. Follow these guidelines to ensure a good
PCB layout. Figure 7 shows a typical buck converter schematic
with the critical power paths/loops. Figure 8 shows an example
PCB component placement and routing with the same critical
power paths/loops from the schematic.
1. Place the ceramic input capacitors as close as possible to the
VIN pin and GND pins to make the loop area minimal; and
the traces of the input capacitors to VIN pin should be short
and wide to minimize the inductance. This critical loop is
shown as Trace 1 in Figure 7 and Figure 8. The larger input
capacitor can be located further away from VIN pin. The
input capacitors and A8654 IC should be on the same side of
the board with traces on the same layer.
2. The loop from the input supply and capacitors, through the
high-side MOSFET, into the load via the output inductor, and
back to ground should be minimized with relatively wide
traces.
3. When the high-side MOSFET is off, free-wheeling current flows from ground, through the synchronous low-side
MOSFET, into the load via the output inductor, and back to
ground. This loop should be minimized and have relatively
wide traces. This loop is shown as Trace 2 in Figure 7 and
Figure 8.
4. Place the output capacitors relatively close to the output
inductor (LO) and the A8654. Ideally, the output capacitors,
output inductor and the controller IC A8654 should be on the
same layer. Connect the output inductor and the output capacitors with a fairly wide trace. The output capacitors must
use a ground plane to make a very low-inductance connection
to the GND. These critical connections are shown as Trace 3
in Figure 7.
5. Place the output inductor (Lo) as close as possible to the SW
pin with short and wide traces. This critical trace is shown
as Trace 4 in Figure 7 and Figure 8. The SW node voltage
transitions from 0 V to VIN and with a high dV/dt rate. This
node is the root cause of many noise issues. It is suggested to
minimize the SW copper area to minimize the coupling capacitance between SW node and other noise-sensitive nodes.
However the SW node area cannot be too small in order to
conduct high current. A ground copper area can be placed
beneath the SW node to provide additional shielding. Also,
keep low-level analog signals (like FB, COMP) away from
the SW polygon.
6. Place the feedback resistor divider (RFB1 and RFB2) very
close to the FB pin. Make the ground side of RFB2 as close as
possible to the A8654.
7. Place the compensation components (RZ, CZ, and CP) as
close as possible to the COMP pin. Also make the ground
side of CZ and CP as close as possible to the A8654.
8. Place the FSET resistor as close as possible to the SYNC/
FSET pin. Place the soft-start capacitor CSS as close as possible to the SS pin.
9. The output voltage sense trace (from VOUT to RFB1) should
be connected as close as possible to the load to obtain the
best load regulation.
10.Place the bootstrap capacitor (CBOOT) near the BOOT pin and
keep the routing from this capacitor to thw SW polygon as
short as possible.
11. When connecting the input and output ceramic capacitors,
use multiple vias to GND and place the vias as close as possible to the pads of the components. Do not use thermal reliefs
around the pads for the input and output ceramic capacitors.
12.To minimize PCB losses and improve system efficiency, the
input and output traces should be as wide as possible and be
duplicated on multiple layers, if possible.
13.The thermal pad under the A8654 IC should be connected to
the GND plane (preferably on the top and bottom layer) with
as many vias as possible. Allegro recommends vias with an
approximately 0.25 to 0.30 mm hole and a 0.13 and 0.18 mm
ring.
14.EMI/EMC issues are always a concern. Allegro recommends
having locations for an RC snubber from SW to ground. The
resistor should be 0805 or 1206 size.
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26
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
1
VIN
RFB1
CIN
FB
LO
SW
SS
VOUT
4
VREG
SYNC/FSET
CO
COMP
CSS
RFB2
CP
RFSET
CZ
Load
2
RZ
SGND
PGND
1
3
Figure 7: Typical Synchronous Buck Regulator
A single-point ground is recommended, which could be the exposed thermal pad under the IC.
2
1
4
Figure 8: Example PCB Component Placement and Routing
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
27
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.65
0.45
8º
0º
5.00 ±0.10
16
16
0.20
0.09
1.70
B
3 NOM
4.40 ±0.10
6.40 ±0.20
A
1
3.00
6.10
0.60 ±0.15
1.00 REF
2
3 NOM
1 2
0.25 BSC
Branded Face
C
16X
0.10 C
0.30
0.19
3.00
SEATING PLANE
GAUGE PLANE
C
PCB Layout Reference View
SEATING
PLANE
1.20 MAX
0.65 BSC
NNNNNNN
0.15
0.00
YYWW
LLLL
A Terminal #1 mark area
B Exposed thermal pad (bottom surface); dimensions may vary with device
C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Branding scale and appearance at supplier discretion
1
D
Standard Branding Reference View
N = Device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W= Week of manufacture
L = Characters 5-8 of lot number
Figure 9: Package LP, 16-Pin eTSSOP with Exposed Thermal Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28
Wide Input Voltage, Adjustable Frequency,
3 A, 2 MHz Synchronous Buck Regulator
A8654
Revision Table
Number
Date
–
February 10, 2015
1
March 4, 2016
2
April 6, 2016
Description
Initial Release
Added AEC-Q100 qualification to Features and Benefits
Updated Electrical Characteristics table:
SW Leakage Current, PWM Switching Frequency (page 6),
Peak Inductor (Pulse-by-Pulse) Current Limit, Slope Compensation, SS Maximum Charge Voltage,
SS Switching Frequency, VOUT UV Threshold (page 7);
Multiple editorial changes (all pages).
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
29