LE25S40QE D

LE25S40QE
Advance Information
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CMOS LSI
4M-bit (512K x 8)
Serial Flash Memory
Overview
The LE25S40QE is a SPI bus flash memory device with a 4M bit (512K  8bit) configuration. It uses a single 1.8V power supply. While making the
most of the features inherent to a serial flash memory device, the
LE25S40QE is housed in an 8-pin ultra-miniature package. All these features
make this device ideally suited to storing program in applications such as
portable information devices, which are required to have increasingly more
compact dimensions. The LE25S40QE also has a small sector erase
capability which makes the device ideal for storing parameters or data that
have fewer rewrite cycles and conventional EEPROMs cannot handle due to
insufficient capacity.
VDFN8 5x6, 1.27P / VSON8T (6x5)
Features
 Read/write operations enabled by single 1.8V power supply: 1.65 to 1.95V supply voltage range
 Operating frequency
: 40MHz
 Temperature range
: 40 to 85C
 Serial interface
: SPI mode 0, mode 3 supported
 Sector size
: 4K bytes/small sector, 64K bytes/sector
 Small sector erase, sector erase, chip erase functions
 Page program function (256 bytes / page)
 Block protect function
 Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ), 150ms (max)
Sector erase time
: 80ms (typ), 250ms (max)
Chip erase time
: 300ms (typ), 3.0s (max)
Page program time
: 6.0ms/256 bytes (typ), 8.0ms/256 bytes (max)
 Status functions
: Ready/busy information, protect information
 Data retention period
: 20 years
 Package
: VDFN8 5x6
* This product is licensed from Silicon Storage Technology, Inc. (USA).
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 22 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. P0
1
Publication Order Number :
LE25S40QE/D
LE25S40QE
Package Dimensions
unit : mm
VDFN8 5x6, 1.27P / VSON8T (6x5)
CASE 509AG
ISSUE O
Figure 1 Pin Assignments
CS 1
8 VDD
SO 2
7 HOLD
WP 3
6 SCK
5 SI
VSS 4
Top view
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LE25S40QE
Figure 2 Block Diagram
4M Bit
Flash EEPROM
Cell Array
XDECODER
ADDRESS
BUFFERS
&
LATCHES
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
CS
SCK
SI
SO
WP
HOLD
Table 1 Pin Description
Symbol
SCK
Pin Name
Serial clock
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
SI
Serial data input
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock.
SO
Serial data output
CS
Chip select
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby
status when the logic level of the pin is high.
WP
Write protect
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
HOLD
Hold
Serial communication is suspended when the logic level of this pin is low.
VDD
Power supply
This pin supplies the 1.65 to 1.95V supply voltage.
VSS
Ground
This pin supplies the 0V supply voltage.
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LE25S40QE
Device Operation
The read, erase, program and other required functions of the device are executed through the command registers.
The serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the
device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit
units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to
execute operation according to the command that is input.
The LE25S40QE supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Figure 3 I/O waveforms
CS
Mode3
SCK
Mode0
8CLK
SI
1st bus
Nth bus
2nd bus
LSB
(Bit0)
MSB
(Bit7)
High Impedance
DATA
DATA
SO
Table 2 Command Settings
Command
Read
Small sector erase
Sector erase
Chip erase
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
5th bus cycle
6th bus cycle
03h
A23-A16
A15-A8
A7-A0
RD *1
RD *1
Nth bus cycle
RD *1
0Bh
A23-A16
A15-A8
A7-A0
X
RD *1
RD *1
20h / D7h
A23-A16
A15-A8
A7-A0
D8h
A23-A16
A15-A8
A7-A0
A23-A16
A15-A8
A7-A0
PD *2
PD *2
PD *2
X
X
60h / C7h
Page program
02h
Write enable
06h
Write disable
04h
Power down
B9h
Status register read
05h
Status register write
01h
JEDEC ID read
9Fh
ID read
ABh
power down
B9h
Exit power down mode
ABh
DATA
X
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input).
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A19 for all commands are "Don't care".
*1: "RD" stands for read data. *2: "PD" stands for page program data.
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LE25S40QE
Table 3 Memory Organization
4M Bit
sector(64KB)
7
6
5
4
3
2
1
0
small sector
127
to
112
111
to
96
95
to
80
79
to
64
63
to
48
47
to
32
31
to
16
15
to
2
1
0
address space(A23 to A0)
07F000h
07FFFFh
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5
070000h
06F000h
070FFFh
06FFFFh
060000h
05F000h
060FFFh
05FFFFh
050000h
04F000h
050FFFh
04FFFFh
040000h
03F000h
040FFFh
03FFFFh
030000h
02F000h
030FFFh
02FFFFh
020000h
01F000h
020FFFh
01FFFFh
010000h
00F000h
010FFFh
00FFFFh
002000h
001000h
000000h
002FFFh
001FFFh
000FFFh
LE25S40QE
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses
following (03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference.
"Figure 4-a Read" shows the timing waveforms.
Figure 4-a Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39 40
47
Mode0
8CLK
SI
03h
Add.
Add.
Add.
N
High Impedance
SO
DATA
MSB
N+1
N+2
DATA
DATA
MSB
MSB
1-2. High-speed Read command
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8
dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55
Mode0
8CLK
SI
0Bh
Add.
Add.
Add.
X
MSB
SO
High Impedance
N
N+1
N+2
DATA
DATA
DATA
MSB
MSB
MSB
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
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LE25S40QE
2. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table
4 Status registers" gives the significance of each bit.
Table 4 Status Registers
Bit
Bit0
Bit1
Name
RDY
Logic
Function
0
Ready
Power-on Time Information
1
Erase/Program
0
Write disabled
1
Write enabled
0
WEN
0
0
Bit2
Nonvolatile information
BP0
1
Bit3
0
Block protect information
1
Protecting area switch
BP1
Nonvolatile information
0
Bit4
BP2
Nonvolatile information
1
Bit5
0
Block protect
1
Upper side/Lower side switch
0
Status register write enabled
1
Status register write disabled
TB
Bit6
Bit7
Reserved bits
SRWP
Nonvolatile information
0
Nonvolatile information
2-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be
executed even during the following operations.
 Small sector erase, sector erase, chip erase
 Page program
 Status register write
"Figure 5 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the
first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence,
synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is
output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock
input is continued. The data can be read by the status register read command at any time (even during a program or
erase cycle).
Figure 5 Status Register Read
CS
Mode 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23
Mode 0
8CLK
SI
05h
MSB
SO
High Impedance
DATA
MSB
DATA
MSB
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DATA
MSB
LE25S40QE
2-2. Status register write
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write
command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2,
TB and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained
even at power-down. "Figure 6 Status Register Write" shows the timing waveforms of status register write, and
Figure 19 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register
write command initiates the internal write operation at the rising CS edge after the data has been input following
(01h). Erase and program are performed automatically inside the device by status register write so that erasing or
other processing is unnecessary before executing the command. By the operation of this command, the information
in bits BP0, BP1, BP2, TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status
register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the
status register. Status register write ends can be detected by RDY of status register read. To initiate status register
write, the logic level of the WP pin must be set high and status register WEN must be set to "1".
Figure 6 Status Register Write
Self-timed
Write Cycle
tSRW
CS
tWPH
tWPS
WP
Mode3
SCK
0 1 2 3 4 5 6 7 8
15
Mode0
8CLK
SI
01h
DATA
MSB
SO
High Impedance
2-3. Contents of each status register
RDY (Bit 0)
The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is
in a busy state, and when it is "0", it means that write is completed.
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will
not perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following
states, WEN is automatically set to "0" in order to protect against unintentional writing.
 At power-on
 Upon completion of small sector erase, sector erase or chip erase
 Upon completion of page program
 Upon completion of status register write
* If a write operation has not been performed inside the LE25S40QE because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior
to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
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LE25S40QE
BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)
Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be
protected can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting
conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order
address area or lower-order address area.
Table 5 Protect Level Setting Conditions
Status Register Bits
Protect Level
Protected Area
TB
BP2
BP1
BP0
0 (Whole area unprotected)
X
0
0
0
None
T1 (Upper side 1/8 protected)
0
0
0
1
07FFFFh to 070000h
T2 (Upper side 1/4 protected)
0
0
1
0
07FFFFh to 060000h
T3 (Upper side 1/2 protected)
0
0
1
1
07FFFFh to 040000h
B1 (Lower side 1/8 protected)
1
1
0
1
00FFFFh to 000000h
B2 (Lower side 1/4 protected)
1
1
1
0
01FFFFh to 000000h
B3 (Lower side 1/2 protected)
1
1
1
1
03FFFFh to 000000h
4 (Whole area protected)
X
1
X
X
07FFFFh to 000000h
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status
registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP
setting conditions".
Table 6 SRWP Setting Conditions
WP Pin
SRWP
Status Register Protect State
0
Unprotected
1
Protected
0
Unprotected
1
Unprotected
0
1
Bit 6 are reserved bits, and have no significance.
3. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation
is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 7 Write Enable" shows the timing waveforms when the write enable operation is performed. The write
enable command consists only of the first bus cycle, and it is initiated by inputting (06h).
 Small sector erase, sector erase, chip erase
 Page program
 Status register write
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LE25S40QE
4. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 8 Write
Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is
initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write
enable command (06h).
Figure 7 Write Enable
Figure 8 Write Disable
CS
CS
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
8CLK
SI
06h
04h
MSB
MSB
High Impedance
SO
High Impedance
SO
5. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 9 Power-down"
shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by
inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The
power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or
more of the silicon ID read command (ABh) has been input). "Figure 10 Exiting from Power-down" shows the
timing waveforms of the power-down exit command.
Figure 9 Power-down
Figure 10 Exiting from Power-down
Power down
mode
Power down
mode
CS
CS
tPRB
tDP
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
8CLK
SI
B9h
MSB
MSB
SO
ABh
High Impedance
SO
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High Impedance
LE25S40QE
6. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes. "Figure 11 Small Sector Erase" shows the timing waveforms, and Figure 20 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by
inputting the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19
are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it
ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register
RDY.
Figure 11 Small Sector Erase
Self-timed
Erase Cycle
tSSE
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
Mode0
8CLK
SI
20h / D7h
Add.
Add.
Add.
MSB
High Impedance
SO
7. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes.
"Figure 12 Sector Erase" shows the timing waveforms, and Figure 20 shows a sector erase flowchart. The sector
erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses
following (D8h). Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command
has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control
exercised by the internal timer. Erase end can also be detected using status register RDY.
Figure 12 Sector Erase
Self-timed
Erase Cycle
tSE
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
Mode0
8CLK
SI
D8h
Add.
Add.
Add.
MSB
SO
High Impedance
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LE25S40QE
8. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 13 Chip Erase" shows the
timing waveforms, and Figure 20 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase
operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer.
Erase end can also be detected using status register RDY.
Figure 13 Chip Erase
Self-timed
Erase Cycle
tCHE
CS
Mode3
SCK
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
60h / C7h
MSB
High Impedance
SO
9. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 14 Page Program" shows the page program timing waveforms,
and Figure 21 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by
the 24-bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until
the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes,
the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS edge occurring at any other timing.
Figure 14 Page Program
Self-timed
Program Cycle
tPP
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
2079
Mode0
8CLK
SI
02h
Add.
Add.
Add.
MSB
SO
High Impedance
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PD
PD
PD
LE25S40QE
10. Silicon ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is
not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID.
In the first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the
subsequent bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory
type, memory capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as
clock inputs are present, "Table 7-1 JEDEC ID code " lists the silicon ID codes and "Figure 15-a JEDEC ID read"
shows the JEDEC ID read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID code " lists
the silicon ID codes and "Figure 15-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence
is finished by setting CS high.
Table 7-1 JEDEC ID code
Table 7-2 ID code
Output code
1 byte device ID
Memory type
16h
Memory capacity code
13h(4M Bit)
1
00h
2 byte device ID
Device code
Output Code
62h
Manufacturer code
Figure 15-a JEDEC ID Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39
Mode0
8CL
SI
SO
9Fh
High Impedance
62h
MSB
16h
MSB
00h
13h
MSB
MSB
62h
MSB
Figure 15-b ID Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39
Mode0
8CL
SI
SO
ABh
X
X
X
High Impedance
3Eh
MSB
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3Eh
MSB
3E
(LE25S40QE)
LE25S40QE
11. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure16
HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is
high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the highimpedance state, and SI and SCK are "don't care".
Figure 16 HOLD
Active
CS
Active
HOLD
tHS
tHS
SCK
tHH
tHH
HOLD
tHLZ
tHHZ
High Impedance
SO
12. Power-on
In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After
power-on, the supply voltage has stabilized at VDD min. or higher, waits for tPU before inputting the command to
start a device operation. The device is in the standby state and not in the power-down state after power is turned on.
To put the device into the power-down state, it is necessary to enter a power-down command.
Figure 17 Power-on Timing
CS = VDD level
VDD
Full Access Allowed
VDD(Max)
VDD(Min)
tPU
0V
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LE25S40QE
13. Hardware Data Protection
LE25S40QE incorporates a power-on reset function. The following conditions must be met in order to ensure that
the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 18 Power-down Timing
VDD
VDD(Max)
VDD(Min)
tPD
0V
vBOT
Power-on timing
Parameter
power-on to operation time
Symbol
power-down time
tPU
tPD
power-down voltage
tBOT
spec
min
max
unit
100
µs
10
ms
0.2
V
14. Software Data Protection
The LE25S40QE eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
 When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
 When the page program data is not in 1-byte increments
 When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to
ensure that the device will operate stably.
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LE25S40QE
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
unit
VDDmax
With respect to VSS
-0.5 to +2.4
V
DC voltage (all pins)
VIN/VOUT
With respect to VSS
-0.5 to VDD+0.5
V
Storage temperature
Tstg
-55 to +150
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Operating Conditions
Parameter
Symbol
Conditions
Ratings
unit
Operating supply voltage
VDD
1.65 to 1.95
V
Operating ambient temperature
Topr
-40 to +85
C
Allowable DC Operating Conditions
Ratings
Parameter
Symbol
Conditions
unit
min
Read mode operating current
ICCR
typ
max
SCK=0.1VDD/0.9VDD,
HOLD=WP=0.9VDD,
6
mA
8
mA
15
mA
50
A
10
A
SO=open,25MHz
SCK=0.1VDD/0.9VDD,
HOLD=WP=0.9VDD,
SO=open,40MHz
Write mode operating current
ICCW
tSSE= tSE= tCHE=typ.,tPP=max
CMOS standby current
ISB
Power-down standby current
IDSB
CS=VDD, HOLD=WP=VDD,
SI=VSS/VDD, SO=open,
CS=VDD, HOLD=WP=VDD,
(erase+page program)
SI=VSS/VDD, SO=open,
Input leakage current
ILI
2
A
Output leakage current
ILO
2
A
Input low voltage
VIL
-0.3
0.3VDD
V
Input high voltage
VIH
0.7VDD
VDD+0.3
V
Output low voltage
VOL
Output high voltage
VOH
IOL=100A, VDD=VDD min
0.2
IOL=1.6mA, VDD=VDD min
0.4
IOH=-100A, VDD=VDD min
V
VCC-0.2
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Data hold, Rewriting frequency
Parameter
condition
min
Program/Erase
Rewriting frequency
Status resister write
Data hold
max
unit
100,000
times/
1,000
Sector
20
year
Pin Capacitance at Ta=25C, f=1MHz
Ratings
Parameter
Symbol
Conditions
unit
max
Output pin capacitance
CSO
VSO=0V
12
pF
Input pin Capacitance
CIN
VIN=0V
6
pF
Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values
for some of the sampled devices.
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LE25S40QE
AC Characteristics
Ratings
Parameter
Symbol
unit
min
typ
max
Read instruction(03h)
Clock frequency
All instructions except for read(03h)
Input signal rising/falling time
SCK logic high level pulse width
25MHz
fCLK
tRF
0.1
tCLHI
14
40MHz
SCK logic low level pulse width
25MHz
25
MHz
40
MHz
V/ns
ns
11.5
tCLLO
40MHz
14
ns
11.5
CS setup time
tCSS
10
ns
CS hold time
tCSH
10
ns
Data setup time
tDS
5
ns
Data hold time
tDH
CS wait pulse width
tCPH
Output high impedance time from CS
tCHZ
Output data time from SCK
tV
Output data hold time
tHO
1
Output low impedance time from SCK
tCLZ
0
ns
WP setup time
tWPS
20
ns
WP hold time
tWPH
20
ns
HOLD setup time
tHS
5
ns
HOLD hold time
tHH
5
ns
Output low impedance time from HOLD
tHLZ
12
Output high impedance time from HOLD
tHHZ
9
ns
Power-down time
tDP
5
s
Power-down recovery time
tPRB
Write status register time
tSRW
nByte
ns
ns
8
256Byte
Page programming cycle time
5
25
tPP
15
ns
11
ns
ns
ns
5
s
8
10
ms
6
8
ms
ms
0.15+
0.20+
n*5.85/256
n*7.80/256
Small sector erase cycle time
tSSE
0.04
0.15
s
Sector erase cycle time
tSE
0.08
0.25
s
Chip erase cycle time
tCHE
0.3
3.0
s
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
AC Test Conditions
Input pulse level ··········· 0.2VDD to 0.8VDD
Input rising/falling time ·· 5ns
Input timing level ········· 0.3VDD, 0.7VDD
Output timing level ······· 1/2VDD
Output load ················ 15pF
Note: As the test conditions for "typ", the measurements are conducted using 1.8V for VDD at room temperature.
0.8VDD
input / output timing level
input level
0.7VDD
1/2VDD
0.3VDD
0.2VDD
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17
LE25S40QE
Timing waveforms
Serial Input Timing
tCPH
CS
tCSH
tCLHI
tCSS
tCLLO tCSH
tCSS
SCK
tDS
SI
tDH
DATA VALID
High Impedance
SO
High Impedance
Serial Output Timing
CS
SCK
tCLZ
SO
tHO
tCHZ
DATA VALID
tV
SI
Hold Timing
CS
tHS
tHH
tHH
tHS
SCK
HOLD
tHLZ
tHHZ
High Impedance
SI
Status register write Timing
CS
tWPS
tWPH
WP
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LE25S40QE
Figure 19 Status Register Write Flowchart
Status register write
Start
06h
01h
Write enable
Set status register write
command
Data
status register write start
on rising edge of CS
05h
NO
Set status register read
command
Bit 0= “0” ?
YES
End of status register
write
* Automatically placed in write disabled state
at the end of the status register write
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LE25S40QE
Figure 20 Erase Flowcharts
Small sector erase
Sector erase
Start
Start
06h
Write enable
06h
D8h
20h / D7h
Address 1
NO
Address 1
Set small sector erase
command
Address 2
Address 2
Address 3
Address 3
Start erase on rising
edge of CS
Start erase on rising
edge of CS
Set status register read
command
05h
Write enable
05h
NO
Bit 0 = “0” ?
Set sector erase
command
Set status register read
command
Bit 0 = “0” ?
YES
YES
End of erase
End of erase
* Automatically placed in write disabled
state at the end of the erase
* Automatically placed in write disabled
state at the end of the erase
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LE25S40QE
Figure 21 Page Program Flowchart
Page program
Chip erase
Start
Start
06h
06h
Write enable
60h / C7h
Set chip erase
command
Write enable
02h
Address 1
Start erase on rising edge
of CS
05h
Set page program
command
Address 2
Address 3
Set status register read
command
Data 0
Bit 0 = “0” ?
Data n
YES
NO
Start program on rising
edge of CS
End of erase
* Automatically placed in write disabled state at
the end of the erase
Set status register read
command
05h
NO
Bit 0= “0” ?
YES
End of
programming
* Automatically placed in write disabled state at
the end of the programming operation.
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LE25S40QE
ORDERING INFORMATION
Device
LE25S40QE-AH
Package
VDFN8 5x6
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
2000 / Tape & Reel
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
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