MC10H141 D

MC10H141
Four−Bit Universal Shift
Register
Description
The MC10H141 is a four−bit universal shift register. This device is a
functional/pinout duplication of the standard MECL 10K™ part with
100% improvement in propagation delay and operation frequency and
no increase in power supply current.
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MARKING DIAGRAMS*
Features
• Shift frequency, 250 MHz Min
• Power Dissipation, 425 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
16
MC10H141L
AWLYYWW
Temperature Range)
• Voltage Compensated
• MECL 10K Compatible
• Pb−Free Packages are Available*
1
CDIP−16
L SUFFIX
CASE 620A
Table 1. TRUTH TABLE
SELECT
S1 S2
OUTPUTS
OPERATING
Q0n + 1 Q1n + 1 Q2n + 1 Q3n + 1
MODE
L
L Parallel Entry
D0
D1
D2
D3
L
H
Shift Right*
Q1n
Q2n
Q3n
DR
H
L
Shift Left*
DL
Q0n
Q1n
Q2n
H
H
Stop Shift
Q0n
Q1n
Q2n
32n
16
MC10H141P
AWLYYWWG
16
1
PDIP−16
P SUFFIX
CASE 648
* Outputs as exist after pulse appears at “C” input with
input conditions as shown (Pulse Positive transition of
clock input).
1
1 20
VCC1
1
16
VCC2
Q2
2
15
Q1
Q3
3
14
Q0
C
4
13
DL
DR
5
12
D0
D3
6
11
D1
S2
7
10
S1
VEE
8
9
D2
PLLC−20
FN SUFFIX
CASE 775
A
WL
YY
WW
G
Pin assignment is for Dual−in−Line Package.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
February, 2006 − Rev. 8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Pin Assignment
© Semiconductor Components Industries, LLC, 2006
10H141G
AWLYYWW
20 1
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC10H141/D
MC10H141
Table 2. MAXIMUM RATINGS
Symbol
Rating
Unit
VEE
Power Supply (VCC = 0)
Characteristic
−8.0 to 0
Vdc
VI
Input Voltage (VCC = 0)
0 to VEE
Vdc
Iout
Output Current
50
100
mA
TA
Operating Temperature Range
0 to +75
°C
Tstg
Storage Temperature Range − Plastic
− Ceramic
−55 to +150
−55 to +165
°C
°C
− Continuous
− Surge
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 3. ELECTRICAL CHARACTERISTICS (VEE = −5.2 V ±5% (Note 1)
0°
Symbol
IE
IinH
Characteristic
25°
75°
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
−
112
−
102
−
112
mA
Input Current High
Pins 5,6,9,11,12,13
Pins 7,10
Pin 4
−
−
−
405
416
510
−
−
−
255
260
320
−
−
−
255
260
320
0.5
−
0.5
−
0.3
−
mA
mA
IinL
Input Current Low
VOH
High Output Voltage
−1.02
−0.84
−0.98
−0.81
−0.92
−0.735
Vdc
VOL
Low Output Voltage
−1.95
−1.63
−1.95
−1.63
−1.95
−1.60
Vdc
VIH
High Input Voltage
−1.17
−0.84
−1.13
−0.81
−1.07
−0.735
Vdc
VIL
Low Input Voltage
−1.95
−1.48
−1.95
−1.48
−1.95
−1.45
Vdc
1. Each MECL 10H™ series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is
maintained. Outputs are terminated through a 50 W resistor to −2.0 V.
Table 4. AC PARAMETERS
Propagation Delay
1.0
2.0
1.0
2.0
1.1
2.1
ns
thold
tpd
Hold Time −
Data, Select
1.0
−
1.0
−
1.0
−
ns
tset
Set−up Time
Data
Select
1.5
3.0
−
−
1.5
3.0
−
−
1.5
3.0
−
−
tr
Rise Time
0.5
2.4
0.5
2.4
0.5
2.4
tf
Fall Time
0.5
2.4
0.5
2.4
0.5
2.4
ns
Shift Frequency
250
−
250
−
250
−
MHz
fshift
ns
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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2
MC10H141
LOGIC DIAGRAM
D3
S1
D2
PARALLEL ENTER
D1
D0
1 OF 4
DECODER
S2
SHIFT RIGHT
DR
SHIFT LEFT
DL
HOLD
D Q
D Q
D Q
D Q
C
C
C
C
C
Q3
Q2
Q1
Q0
VCC1 = PIN 1
SCC2 = PIN 16
VEE = PIN 8
APPLICATION INFORMATION
The MC10H141 is a four−bit universal shift register
which performs shift left, or shift right, serial/parallel in, and
serial/parallel out operations with no external gating. Inputs
S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip−flops shift
information on the positive edge of the clock. The four
operations are stop shift, shift left, shift right, and parallel
entry of data. The other six inputs are all data type inputs;
four for parallel entry data, and one for shifting in from the
left (DL) and one for shifting in from the right (DR).
ORDERING INFORMATION
Package
Shipping †
MC10H141FN
PLLC−20
46 Units / Rail
MC10H141FNG
PLLC−20
(Pb−Free)
46 Units / Rail
MC10H141FNR2
PLLC−20
500 / Tape & Reel
MC10H141FNR2G
PLLC−20
(Pb−Free)
500 / Tape & Reel
MC10H141L
CDIP−16
25 Unit / Rail
MC10H141P
PDIP−16
25 Unit / Rail
MC10H141PG
PDIP−16
(Pb−Free)
25 Unit / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC10H141
PACKAGE DIMENSIONS
20 LEAD PLLC
CASE 775−02
ISSUE E
0.007 (0.180) M T L−M
B
Y BRK
−N−
U
N
S
0.007 (0.180) M T L−M
S
S
N
S
D
−L−
−M−
Z
W
20
D
1
V
0.007 (0.180) M T L−M
S
N
S
R
0.007 (0.180) M T L−M
S
N
S
Z
T L−M
S
N
H
J
0.007 (0.180) M T L−M
S
−T−
VIEW S
SEATING
PLANE
F
0.007 (0.180) M T L−M
S
VIEW S
N
S
N
S
K
0.004 (0.100)
G
S
S
K1
E
G1
0.010 (0.250) S T L−M
S
VIEW D−D
A
C
0.010 (0.250)
G1
X
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M,
1982.
2. DIMENSIONS IN INCHES.
3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP
OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT
DATUM −T−, SEATING PLANE.
5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER
THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
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4
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10 _
0.310
0.330
0.040
−−−
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10 _
7.88
8.38
1.02
−−−
N
S
MC10H141
PACKAGE DIMENSIONS
CDIP−16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620A−01
ISSUE O
B
A
A
16
9
1
8
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
5 THIS DRAWING REPLACES OBSOLETE
CASE OUTLINE 620−10.
M
L
16X
0.25 (0.010)
E
M
DIM
A
B
C
D
E
F
G
H
K
L
M
N
J
T B
F
C
K
T
N
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
−−−
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
SEATING
PLANE
G
16X
0.25 (0.010)
M
D
T A
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE R
−A−
16
9
1
8
B
F
C
L
S
−T−
H
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
−−− 0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC10H141
MECL 10H and MECL 10K are trademarks of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC10H141/D