MC74AC377, MC74ACT377 Octal D Flip-Flop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. www.onsemi.com SOIC−20W DW SUFFIX CASE 751D 1 Features • • • • • • • • • • • • Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ACT377 Has TTL Compatible Inputs MSL = 1 for all Surface Mount Chip Complexity: 292 FETs or 73 Gates These are Pb−Free Devices VCC O7 D7 D6 O6 O5 D5 D4 O4 CP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 CE O0 D0 D1 O1 O2 D2 D3 O3 GND TSSOP−20 DT SUFFIX CASE 948E 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. Figure 1. Pinout: 20−Lead Packages Conductors (Top View) PIN NAMES D0 D1 D2 D3 D4 D5 D6 D7 PIN FUNCTION D0−D7 Data Inputs CE Clock Enable (Active LOW) Q0−Q7 Data Outputs CP Clock Pulse Input © Semiconductor Components Industries, LLC, 2015 March, 2015 − Rev. 10 CP CE O0 O1 O2 O3 O4 O5 O6 O7 Figure 2. Logic Symbol 1 Publication Order Number: MC74AC377/D MC74AC377, MC74ACT377 MODE SELECT-FUNCTION TABLE Inputs Operating Mode CP Load ′1′ Load ′0′ Hold (Do Nothing) X Outputs CE Dn Qn L H H L L L H X No Change H X No Change H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition D0 D1 D2 D3 D4 D5 D6 D7 CE D Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q CP CP O0 O1 O2 O3 O4 O5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2 O6 O7 MC74AC377, MC74ACT377 MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) (Note 1) −0.5 to VCC +0.5 V VOUT IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±50 mA IOUT DC Output Sink/Source Current ±50 mA ICC DC Supply Current, per Output Pin ±50 mA IGND DC Ground Current, per Output Pin ±100 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature Under Bias 140 _C qJA Thermal Resistance (Note 2) 65.8 110.7 _C/W MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup SOIC TSSOP Level 1 Oxygen Index: 30% − 35% ESD Withstand Voltage Latchup Performance UL 94 V−0 @ 0.125 in Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Above VCC and Below GND at 85_C (Note 6) > 2000 > 200 > 1000 V ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IOUT absolute maximum rating must be observed. 2. The package thermal impedance is calculated in accordance with JESD 51−7. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout tr, tf Parameter Supply Voltage Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − −40 25 85 °C DC Input Voltage, Output Voltage (Ref. to GND) Input Rise and Fall Time (Note 7) ′AC Devices except Schmitt Inputs Unit V V ns/V tr, tf Input Rise and Fall Time (Note 8) ′ACT Devices except Schmitt Inputs TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 8. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. www.onsemi.com 3 MC74AC377, MC74ACT377 74AC − DC CHARACTERISTICS Symbol TA = −40°C to +85°C TA = +25°C VCC (V) Parameter Typ Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 3.0 4.5 5.5 1.50 2.25 2.75 2.10 3.15 3.85 2.10 3.15 3.85 V V V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 3.0 4.5 5.5 1.50 2.25 2.75 0.90 1.35 1.65 0.90 1.35 1.65 V V V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V V V IOUT = −50 mA 3.0 4.5 5.5 − 2.56 3.86 4.86 2.46 3.76 4.76 V V V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 V V V IOUT = 50 mA 3.0 4.5 5.5 − 0.36 0.36 0.36 0.44 0.44 0.44 V V V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA ±0.1 ±1.0 mA VI = VCC, GND − 75 −75 mA mA VOLD = 1.65 V Max VOHD = 3.85 V Min 8.0 80 mA VIN = VCC or GND VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current 5.5 − IOLD IOHD Maximum Input Leakage Current 5.5 5.5 − ICC Maximum Quiescent Supply Current − 5.5 *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. 74AC − AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6. Symbol TA = +25°C CL = 50 pF VCC* (V) Parameter TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max 3.3 5.0 90 140 − − 75 125 − Unit fmax Maximum Clock Frequency MHz tPLH Propagation Delay CP to Qn 3.3 5.0 3.0 2.0 − 13.0 9.0 1.5 1.5 14.0 10.0 ns tPHL Propagation Delay CP to Qn 3.3 5.0 3.5 2.5 − 13.0 10.0 2.0 1.5 14.5 11.0 ns * Voltage Range 3.3 V is 3.3 V ±0.3 V; Voltage Range 5.0 V is 5.0 V ±0.5 V. 74AC − AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter TA = +25°C CL = 50 pF Typ TA = −40°C to +85°C Guaranteed Minimum Unit ts Setup Time, HIGH or LOW Dn to CP 3.3 5.0 − 5.5 4.07 6.0 4.5 ns th Hold Time, HIGH or LOW Dn to CP 3.3 5.0 − 0 1.0 0 1.0 ns ts Setup Time, HIGH or LOW CE to CP 3.3 5.0 − 6.0 4.0 7.5 4.5 ns th Hold Time, HIGH or LOW CE to CP 3.3 5.0 − 0 1.0 0 1.0 ns tw CP Pulse Width HIGH or LOW 3.3 5.0 − 5.5 4.0 6.0 4.5 * Voltage Range 3.3 V is 3.3 V ±0.3 V; Voltage Range 5.0 V is 5.0 V ±0.5 V. www.onsemi.com 4 ns MC74AC377, MC74ACT377 74ACT − DC CHARACTERISTICS Symbol TA = −405C to +855C TA = +255C VCC (V) Parameter Typ Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V IOUT = −50 mA 4.5 5.5 − 3.86 4.86 3.76 4.76 V *VIN = VIL or VIH −24 mA IOH −24 mA 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 V IOUT = 50 mA 4.5 5.5 − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH −24 mA IOH −24 mA Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND DICCT Additional Max ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOLD IOHD †Minimum Dynamic Output Current 5.5 − − 75 −75 mA VOLD = 1.65 V Max VOHD = 3.85 V Min Maximum Quiescent Supply Current 5.5 8.0 80 mA VIN = VCC or GND VOL IIN ICC Maximum Low Level Output Voltage − VOUT = 0.1 V or VCC − 0.1 V VOUT = 0.1 V or VCC − 0.1 V *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. 74ACT − AC CHARACTERISTICS For Figures and Waveforms — See Figures 4, 5, and 6. Symbol TA = +25°C CL = 50 pF VCC* (V) Parameter Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Unit Max fmax Maximum Clock Frequency 5.0 140 − − 125 − MHz tPLH Propagation Delay CP to Qn 5.0 3.0 − 9.0 2.5 10 ns tPHL Propagation Delay CP to Qn 5.0 3.5 − 10 2.5 11 ns *Voltage Range 5.0 V is 5.0 V ±0.5 V. 74ACT − AC OPERATING REQUIREMENTS Symbol TA = +25°C CL = 50 pF VCC* (V) Parameter Typ TA = −40°C to +85°C CL = 50 pF Unit Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to CP 5.0 − 4.5 5.5 ns th Hold Time, HIGH or LOW Dn to CP 5.0 − 1.0 1.0 ns ts Setup Time, HIGH or LOW CE to CP 5.0 − 4.5 5.5 ns th Hold Time, HIGH or LOW CE to CP 5.0 − 1.0 1.0 ns tw CP Pulse Width 5.0 − 4.0 4.5 ns HIGH or LOW *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Value Typ Unit Test Conditions CIN Input Capacitance Parameter 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 90 pF VCC = 5.0 V www.onsemi.com 5 MC74AC377, MC74ACT377 SWITCHING WAVEFORMS tf tr VCC CLOCK 50% CE GND tw VCC 50% tsu 1/fmax tPLH th VCC tPHL CLOCK 50% GND Q 50% Figure 4. Figure 5. VALID VCC DATA 50% GND tsu th VCC CLOCK 50% GND Figure 6. 450 W OUTPUT 50 W SCOPE TEST POINT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 7. Test Circuit www.onsemi.com 6 MC74AC377, MC74ACT377 ORDERING INFORMATION Package Shipping† MC74AC377DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74AC377DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74ACT377DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74ACT377DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74AC377DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74AC377DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−20W TSSOP−20 20 20 ACT 377 ALYWG G ACT377 AWLYYWWG 1 1 20 20 AC 377 ALYWG G AC377 AWLYYWWG 1 1 www.onsemi.com 7 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) MC74AC377, MC74ACT377 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B L SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− N F DETAIL E C G D H DETAIL E 0.100 (0.004) −T− SEATING NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C --1.20 --0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC −W− H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 8 MC74AC377, MC74ACT377 PACKAGE DIMENSIONS SOIC−20W DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SEATING PLANE C T ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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