MC74ACT323 8−Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load. • • • • • • http://onsemi.com MARKING DIAGRAMS 20 MC74ACT323N AWLYYWW 20 Common Parallel I/O for Reduced Pin Count PDIP−20 N SUFFIX CASE 738 1 Additional Serial Inputs and Outputs for Expansion 1 Four Operating Modes: Shift Left, Shift Right, Load and Store 20 3-State Outputs for Bus-Oriented Applications Outputs Source/Sink 24 mA SO−20 DW SUFFIX CASE 751D 20 TTL Compatible Inputs 1 ACT323 AWLYYWW 1 20 TSSOP−20 DT SUFFIX CASE 948E 20 1 ACT 323 ALYW 1 A L, WL Y, YY W, WW = = = = Assembly Location Wafer Lot Year Work Week ORDERING INFORMATION Device Package Shipping MC74ACT323N PDIP−20 18 Units/Rail MC74ACT323DW SOIC−20 38 Units/Rail MC74ACT323DWR2 SOIC−20 1000 Tape & Reel MC74ACT323DT TSSOP−20 75 Units/Rail MC74ACT323DTR2 TSSOP−20 2500 Tape & Reel © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 2 1 Publication Order Number: MC74ACT323/D MC74ACT323 VCC S1 DS7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0 20 19 18 17 16 15 14 13 12 11 DS7 Q7 CP DQ 1 2 3 4 5 6 7 8 9 10 S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 SR GND I/O7 CP I/O6 DQ Figure 1. Pinout: 20−Lead Packages Conductors (Top View) CP PIN ASSIGNMENT DQ PIN FUNCTION CP Clock Pulse Input DS0 Serial Data Input for Right Shift DS7 Serial Data Input for Left Shift S0, S1 Mode Select Inputs SR Synchronous Master Reset OE1, OE2 3-State Output Enable Inputs I/O0−I/O7 Multipled Parallel Data Inputs or 3-State Parallel Data Outputs Q0, Q7 Serial Outputs I/O5 CP DQ I/O4 CP DQ I/O3 CP I/O2 DQ DS0 S0 DS7 S1 Q7 CP 1 2 CP OE SR Q0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ Figure 3. Logic Symbol I/O1 CP DQ I/O0 TRUTH TABLE Inputs S0 SR S1 S0 CP L X X Synchronous Reset; Q0 − Q7 = LOW H H H Parallel Load; I/On → Qn H L H Shift Right; DS0 → Q0, Q0 → Q1, etc. H H L Shift Left; DS7 → Q7, Q7 → Q6, etc. H L L X H = HIGH Voltage Level L = LOW Voltage Level Response S1 DS0 SR CP OE1 Q0 OE2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 2. LOGIC DIAGRAM Hold X = Immaterial = LOW-to-HIGH Clock Transition http://onsemi.com 2 MC74ACT323 FUNCTIONAL DESCRIPTION The MC74ACT323 contains eight edge- triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3 state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit *0.5 to )7.0 V *0.5 v VI v VCC )0.5 V VCC DC Supply Voltage VI DC Input Voltage VO DC Output Voltage *0.5 v VO v VCC )0.5 V IIK DC Input Diode Current $20 mA IOK DC Output Diode Current $50 mA IO DC Output Sink/Source Current $50 mA ICC DC Supply Current per Output Pin $50 mA IGND DC Ground Current per Output Pin $50 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction temperature under Bias )150 _C qJA Thermal resistance PDIP SOIC TSSOP 67 96 128 _C/W PD Power Dissipation in Still Air at 85_C PDIP SOIC TSSOP 750 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) > 2000 > 200 >1000 V ILatch−Up Latch−Up Performance Above VCC and Below GND at 85_C (Note 6) $100 mA (Note 2) Level 1 Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum−rated conditions is not implied. 2. IO absolute maximum rating must be observed. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. http://onsemi.com 3 MC74ACT323 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min VCC DC Input Voltage (Referenced to GND) Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Note 8) VCC = 4.5 V VCC = 5.5 V Typ Max Unit 4.5 5.5 V 0 VCC V −40 25 +85 °C 0 0 10 8.0 10 8.0 ns/V TJ Junction Temperature (PDIP) 140 °C IOH Output Current − High −24 mA IOL Output Current − Low 24 mA 7. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level. 8. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS TA = +255C Symbol Parameter TA = −405C to +855C VCC (V) Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V V IOUT = −50 μA 3.86 4.86 3.76 4.76 V V *VIN = VIL or VIH IOH 0.1 0.1 0.1 0.1 V V IOUT = 50 μA 4.5 5.5 0.36 0.36 0.44 0.44 V V *VIN = VIL or VIH IOH ±0.1 ±1.0 μA VI = VCC, GND 1.5 mA VI = VCC − 2.1 V ±5.0 μA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 75 −75 mA mA VOLD = 1.65 V Max VOHD = 3.85 V Min 80 μA VIN = VCC or GND 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 IIN Maximum Input Leakage Current 5.5 DICCT Additional Maximum ICC/Input 5.5 IOZ Maximum 3−State Current 5.5 IOLD IOHD †Minimum Dynamic Output Current 5.5 5.5 ICC Maximum Quiescent Supply Current 5.5 0.001 0.001 0.6 ±0.5 8.0 *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. http://onsemi.com 4 −24 mA −24 mA −24 mA −24 mA MC74ACT323 AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 4 and 5.) TA = +25°C CL = 50 pF Symbol Parameter VCC* (V) Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Max 110 Unit fmax Maximum Input Frequency 5.0 120 125 MHz tPLH Propagation Delay CP to Q0 or Q7 5.0 5.0 9.0 12.5 4.0 14 ns tPHL Propagation Delay CP to Q0 or Q7 5.0 5.0 9.0 13.5 4.5 15 ns tPLH Propagation Delay CP to I/On 5.0 5.0 8.5 12.5 4.5 14.5 ns tPZH Output Enable Time 5.0 3.5 7.5 11 3.0 12.5 ns tPZL Output Enable Time 5.0 3.5 7.5 11.5 3.0 13 ns tPHZ Output Disable Time 5.0 4.0 8.5 12.5 3.0 13.5 ns tPLZ Output Disable Time 5.0 3.0 8.0 11.5 2.5 12.5 ns *Voltage Range 5.0 V is 5.0 V ±0.5 V AC OPERATING REQUIREMENTS Symbol Parameter TA = +25°C CL = 50 pF VCC* (V) Typ TA = −40°C to +85°C CL = 50 pF Unit Guaranteed Minimum ts Setup Time, HIGH or LOW S0 or S1 to CP 5.0 2.0 5.0 5.0 ns th Hold Time, HIGH or LOW S0 or S1 to CP 5.0 0 1.5 1.5 ns ts Setup Time, HIGH or LOW I/On, DS0, DS7 to CP 5.0 1.0 4.0 4.5 ns th Hold Time, HIGH or LOW I/On, DS0, DS7 to CP 5.0 0 1.0 1.0 ns ts Setup Time, HIGH or LOW SR to CP 5.0 1.0 2.5 2.5 ns th Hold Time, HIGH or LOW SR to CP 5.0 0 1.0 1.0 ns tw CP Pulse Width HIGH or LOW 5.0 2.0 4.0 4.5 ns *Voltage Range 5.0 V is 5.0 V ±0.5 V CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 170 pF VCC = 5.0 V http://onsemi.com 5 MC74ACT323 SWITCHING WAVEFORMS tr Cp tf SR 90% 50% 10% 3.0 V 50% 3.0 V GND GND ts tw th 1/fmax tPLH Q0 − Q7 I/O0 − I/O7 3.0 V 50% tPHL Cp 90% 50% 10% tTLH tPHL Q0 − Q7 I/O0 − I/O7 tTHL Figure 4. OE1 OR OE2 Figure 5. 50% tPZL 50% 10% tPZH tPHZ Q0−Q7 90% 50% GND 3.0 V GND tPLZ VCC S0 OR S1 3.0 V HIGH IMPEDANCE S1 OR S0 50% GND tPZL VOL tPLZ 50% VOH Q0−Q7 HIGH IMPEDANCE 10% tPZH tPHZ 90% 50% Figure 6. Figure 7. VALID MODE SELECT OR DATA 3.0 V 50% ts GND th Cp 3.0 V 50% GND Figure 8. INPUT 450 W OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL* *Includes all probe and jig capacitance Figure 9. Test Circuit http://onsemi.com 6 HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE MC74ACT323 PACKAGE DIMENSIONS PDIP−20 N SUFFIX 20 PIN PLASTIC DIP PACKAGE CASE 738−03 ISSUE E −A− 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C −T− K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SO−20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D−05 ISSUE F A 20 q X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74ACT323 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E−02 ISSUE A 20X 0.15 (0.006) T U 2X L S L/2 K REF 0.10 (0.004) 20 M T U S V S K K1 11 B −U− PIN 1 IDENT J J1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ PLANE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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