ESD5371 Product Preview ESD Protection Diode Micro−Packaged Diodes for ESD Protection The ESD5371 is designed to protect voltage sensitive components that require low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. www.onsemi.com 2 1 Features Low Clamping Voltage Small Body Outline Dimensions: 0.62 mm x 0.32 mm Low Body Height: 0.3 mm Stand−off Voltage: 3.3 V IEC61000−4−2 Level 4 ESD Protection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MARKING DIAGRAM PIN 1 X3DFN2 CASE 152AF 3 M Typical Applications • mSD Card Protection • Audio Line • GPIO M = Specific Device Code = Date Code ORDERING INFORMATION Device MAXIMUM RATINGS ESD5371MXT5G Rating IEC 61000−4−2 (ESD) 3 • • • • • • Symbol Contact Air Value Unit ±30 ±30 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 250 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) Package Shipping† X3DFN2 (Pb−Free) 10000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. P2 1 Publication Order Number: ESD5371/D ESD5371 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM VBR IT Breakdown Voltage @ IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions Min Typ VRWM Breakdown Voltage (Note 2) VBR IT = 1 mA Max Unit 3.3 V 3.5 V Reverse Leakage Current IR VRWM = 3.3 V 0.1 mA Clamping Voltage (Note 3) VC IPP = 1 A 8 V Clamping Voltage (Note 3) VC IPP = 4 A 10 V Peak Pulse Current (Note 3) IPP tP = 8/20 ms Clamping Voltage TLP (Note 4) VC IPP = 16 A Junction Capacitance CJ VR = 0 V, f = 1 MHz Dynamic Resistance RDYN 5.0 A 11 IEC 61000−4−2 Level 4 equivalent (±8 kV Contact, ±15 kV Air) V 10 TLP Pulse pF W 0.22 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. 4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 60 10 50 0 40 −10 VOLTAGE (V) VOLTAGE (V) TYPICAL CHARACTERISTICS 30 20 −20 −30 10 −40 0 −50 −10 −20 0 20 40 60 80 100 120 −60 −20 140 TIME (ns) 0 20 40 60 80 100 120 TIME (ns) Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 www.onsemi.com 2 140 ESD5371 TYPICAL CHARACTERISTICS 9 1.E−03 8 1.E−04 7 1.E−05 6 1.E−06 5 I1 (A) C (pF) 1.E−02 1.E−07 4 1.E−08 3 1.E−09 2 1.E−10 1 1.E−11 −8 −6 −4 −2 0 2 4 6 0 −5 8 −4 −3 −2 −1 V1 (V) 0 1 2 3 4 5 18 20 VBias (V) Figure 3. IV Characteristics Figure 4. CV Characteristics 16 14 CAPACITANCE (pF) 12 10 8 6 4 2 0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 FREQUENCY (GHz) 20 −20 18 −18 16 −16 TLP CURRENT (A) TLP CURRENT (A) Figure 5. Capacitance over Frequency 14 12 10 8 6 −14 −12 −10 −8 −6 4 −4 2 −2 0 0 2 4 6 8 10 12 14 16 18 0 0 20 2 4 6 8 10 12 14 16 VC, VOLTAGE (V) VC, VOLTAGE (V) Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve www.onsemi.com 3 ESD5371 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 8. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 9. Diagram of ESD Test Setup ESD Voltage Clamping at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 10. 8 X 20 ms Pulse Waveform www.onsemi.com 4 80 ESD5371 Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 11. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 12 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 11. Simplified Schematic of a Typical TLP System Figure 12. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 5 ESD5371 PACKAGE DIMENSIONS X3DFN2, 0.62x0.32, 0.355P, (0201) CASE 152AF ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D PIN 1 INDICATOR (OPTIONAL) DIM A A1 b D E e L2 E TOP VIEW 0.05 C A RECOMMENDED MOUNTING FOOTPRINT* 0.05 C 2X A1 SIDE VIEW MILLIMETERS MIN MAX 0.25 0.33 −−− 0.05 0.22 0.28 0.58 0.66 0.28 0.36 0.355 BSC 0.17 0.23 C SEATING PLANE 0.74 2X 0.30 1 e 2X 1 b 2 2X 0.31 DIMENSIONS: MILLIMETERS 2X 0.05 M 0.05 L2 M C A B See Application Note AND8398/D for more mounting details C A B BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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