ESD5381 D

ESD5381 Series
ESD Protection Diodes
Micro−Packaged Diodes for ESD Protection
The ESD5381 series are designed to protect voltage sensitive
components from ESD. Excellent clamping capability, low leakage,
and fast response time provide best in class protection on designs that
are exposed to ESD. Because of their small size, they are suited for use
in cellular phones, MP3 players, digital cameras and many other
portable applications where board space comes at a premium.
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1
Cathode
Specification Features
•
•
•
•
•
•
•
•
•
Low Capacitance
Low Clamping Voltage
Small Body Outline Dimensions: 0.60 mm x 0.30 mm
Low Body Height: 0.3 mm
Low Leakage
Response Time is < 1 ns
IEC61000−4−2 Level 4 ESD Protection
IEC61000−4−4 Level 4 EFT Protection
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING
DIAGRAM
PIN 1
X3DFN2
CASE 152AF
ORDERING INFORMATION
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
IEC 61000−4−2 (ESD)
Contact
Air
Value
Unit
8
kV
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
°PD°
300
mW
RqJA
400
°C/W
Junction and Storage Temperature Range
TJ, Tstg
−55 to +150
°C
TL
260
°C
Lead Solder Temperature − Maximum
(10 Second Duration)
Package
Shipping†
ESD5381MUT5G
X3DFN2
(Pb−Free)
10000 /
Tape & Reel
ESD5382MUT5G
X3DFN2
(Pb−Free)
10000 /
Tape & Reel
Device
Symbol
XM
X
= Specific Device Code
M = Date Code
(Specific marking on following page)
Mechanical Characteristics
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Rating
2
Anode
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 6
1
Publication Order Number:
ESD5381/D
ESD5381 Series
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IF
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
VC VBR VRWM
Working Peak Reverse Voltage
V
IR VF
IT
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
Test Current
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
IPP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
VRWM
(V)
IR (nA)
@ VRWM
VBR (V) @ IT
(Note 2)
IT
Device
Marking
Max
Max
Min
mA
Typ
ESD5381MUT5G
J
3.0
100
6.1
1.0
ESD5382MUT5G
K
3.0
50
14.2
1.0
Device
VC (V) @
IPP = 1 A
VC
Max
Max
(Note 3)
Per IEC61000−4−2
(Note 4)
12
13
10.5
Figures 1 and 2
See Below
6
8
26.0
Figures 3 and 4
See Below
C (pF)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
3. Surge current waveforms per Figure 7.
4. For test procedure see Figures 5 and 6 and Application Note AND8307/D.
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2
ESD5381 Series
0
60
−5
−10
−15
40
VOLTAGE (V)
VOLTAGE (V)
50
30
20
−20
−25
−30
−35
−40
10
−45
0
50
100
150
−50
−50
200
0
50
100
150
TIME (ns)
TIME (ns)
Figure 1. ESD5381MUT5G Clamping Voltage
Screenshot Positive 8 kV Contact per
IEC61000−4−2
Figure 2. ESD5381MUT5G Clamping Voltage
Screenshot Negative 8 kV Contact per
IEC61000−4−2
60
0
50
−10
40
−20
VOLTAGE (V)
VOLTAGE (V)
0
−50
30
20
10
200
−30
−40
−50
0
−50
0
50
100
150
200
−60
−50
0
50
100
150
TIME (ns)
TIME (ns)
Figure 3. ESD5382MUT5G Clamping Voltage
Screenshot Positive 8 kV Contact per
IEC61000−4−2
Figure 4. ESD5382MUT5G Clamping Voltage
Screenshot Negative 8 kV Contact per
IEC61000−4−2
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3
200
ESD5381 Series
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 6. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 7. 8 X 20 ms Pulse Waveform
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4
80
ESD5381 Series
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
D
PIN 1
INDICATOR
(OPTIONAL)
DIM
A
A1
b
D
E
e
L2
E
TOP VIEW
0.05 C
MILLIMETERS
MIN
MAX
0.25
0.33
−−−
0.05
0.22
0.28
0.58
0.66
0.28
0.36
0.355 BSC
0.17
0.23
A
0.05 C
2X
A1
SIDE VIEW
C
RECOMMENDED
MOUNTING FOOTPRINT*
SEATING
PLANE
0.74
e
2X
1
1
b
2
2X
2X
0.05
M
2X
0.30
0.05
L2
M
C A B
0.31
DIMENSIONS: MILLIMETERS
C A B
See Application Note AND8398/D for more mounting details
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and the
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ESD5381/D