ESD5482 Transient Voltage Suppressors Micro−Packaged Diodes for ESD Protection The ESD5482 is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, this part is well suited for use in cellular phones, MP3 players, digital cameras and many other portable applications where board space comes at a premium. www.onsemi.com 1 Cathode 2 Anode Specification Features Low Capacitance 5 pF Low Clamping Voltage Small Body Outline Dimensions: 0.60 mm x 0.30 mm Low Body Height: 0.3 mm Stand−off Voltage: 3.3 V Low Leakage Response Time is < 1 ns IEC61000−4−2 Level 4 ESD Protection IEC61000−4−4 Level 4 EFT Protection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MARKING DIAGRAM PIN 1 X3DFN2 CASE 152AF J M = Specific Device Code (Rotated 90° Clockwise) ORDERING INFORMATION Device ESD5482MUT5G Mechanical Characteristics MOUNTING POSITION: Any QUALIFIED MAX REFLOW TEMPERATURE: 260°C J • • • • • • • • • • Package Shipping† X3DFN2 (Pb−Free) 10000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Device Meets MSL 1 Requirements MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Air Value Unit ±10 ±10 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 300 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. 1 1 Publication Order Number: ESD5482/D ESD5482 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM VBR IT IT VC VBR VRWM IR Breakdown Voltage @ IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Parameter Reverse Working Voltage Breakdown Voltage Symbol Condition Min Typ VRWM VBR IT = 1 mA (Note 2) Max Unit 3.3 V 5.0 V Reverse Leakage Current IR VRWM = 3.3 V Clamping Voltage VC IPP = 1 A (Note 3) ESD Clamping Voltage VC Per IEC61000−4−2 See Figures 1 and 2 Junction Capacitance CJ VR = 0 V, f = 1 MHz VR = 0 V, f = 1 GHz 5.0 5.0 Dynamic Resistance RDYN TLP Pulse 0.60 W f = 1 MHz f = 8.5 GHz 0.20 0.56 dB Insertion Loss <1 50 nA 7.8 9.1 V 7.0 7.0 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at 25°C, per IEC61000−4−5 waveform. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 www.onsemi.com 2 pF ESD5482 TYPICAL CHARACTERISTICS 1E−02 5.0 1E−03 4.5 1E−04 4.0 3.5 C (pF) I (A) 1E−05 1E−06 1E−07 1.5 1E−09 1.0 1E−10 0.5 1E−11 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 0 −4 −3 −2 −1 0 1 2 V (V) VBias (V) Figure 3. IV Characteristics Figure 4. CV Characteristics 20 0 18 −3 16 CAPACITANCE (pF) 3 −6 −9 (dB) 2.5 2.0 1E−08 −12 −15 −18 3 4 14 12 10 8 6 0V −21 4 −24 −27 3.3 V 2 0 0E+00 5E+08 1E+09 1.5E+09 2E+09 2.5E+09 3E+09 1E+07 1E+06 1E+08 1E+09 FREQUENCY (Hz) FREQUENCY (Hz) Figure 5. RF Insertion Loss Figure 6. Capacitance over Frequency 16 −16 14 −14 12 −12 CURRENT (A) CURRENT (A) 3.0 10 8 6 −10 −8 −6 4 −4 2 −2 0 0 0 2 4 6 8 10 12 14 16 18 0 20 −2 −4 −6 −8 −10 −12 −14 −16 −18 −20 VOLTAGE (V) VOLTAGE (V) Figure 7. Positive TLP I−V Curve Figure 8. Negative TLP I−V Curve www.onsemi.com 3 ESD5482 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 9. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 10. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 11. 8 X 20 ms Pulse Waveform www.onsemi.com 4 80 ESD5482 PACKAGE DIMENSIONS X3DFN2, 0.62x0.32, 0.355P, (0201) CASE 152AF ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D PIN 1 INDICATOR (OPTIONAL) DIM A A1 b D E e L2 E TOP VIEW 0.05 C MILLIMETERS MIN MAX 0.25 0.33 −−− 0.05 0.22 0.28 0.58 0.66 0.28 0.36 0.355 BSC 0.17 0.23 A 0.05 C 2X A1 SIDE VIEW C RECOMMENDED MOUNTING FOOTPRINT* SEATING PLANE 0.74 e 2X 1 1 b 2 2X 2X 0.05 M 2X 0.30 0.05 L2 M C A B 0.31 DIMENSIONS: MILLIMETERS C A B See Application Note AND8398/D for more mounting details *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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