CM1241 4-Channel Low Capacitance Dual-Voltage ESD Protection Array Features http://onsemi.com • 3 Channels of Low Voltage ESD Protection • 1 Channel of High Voltage ESD Protection • Provides ESD Protection to IEC61000−4−2 Level 4: • • • • • • 8 ±8 kV Contact Discharge (Pins 1−3) ±15 kV Contact Discharge (Pin 4) Low Channel Input Capacitance Minimal Capacitance Change with Temperature and Voltage High Voltage Zener Diode Protects Supply Rail No Need for External Bypass Capacitors Each I/O Pin Can Withstand Over 1000 ESD Strikes* These Devices are Pb−Free and are RoHS Compliant TYPICAL APPLICATION 1 WDFN−8 D4 SUFFIX CASE 511BF BLOCK DIAGRAM VCC Pin 4 VP (Internal) CH1 CH2 CH3 Pin 1 Pin 2 Pin 3 VN Pin 5 GND Pins 6 − 8 MARKING DIAGRAM AW1 MG G AW1 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device CM1241−04D4 Package Shipping† WDFN−8 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 4 1 Publication Order Number: CM1241/D CM1241 PACKAGE / PINOUT DIAGRAMS Table 1. PIN DESCRIPTIONS 4−Channel, 8−Lead, WDFN−8 Package Top View (Pins Down View) Pin Name Type Description 1 CH1 I/O LV Low−capacitance ESD Channel 2 CH2 I/O LV Low−capacitance ESD Channel 3 CH3 I/O LV Low−capacitance ESD Channel 4 VCC HV VDD 5 GND 6 VN Negative Voltage Supply Rail 7 VN Negative Voltage Supply Rail 8 VN Negative Voltage Supply Rail DAP GND Bottom View (Pins Up View) 8 7 6 5 1 2 3 Pin 1 Marking HV ESD Channel AW1 4 DAP Ground 8 7 6 5 1 2 3 4 8−Lead WDFN Die Attach Pad (Ground) SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units DC Voltage on Low−voltage Pins 6.0 V DC Voltage on High−voltage Pins (VCC pin) 14.5 V Operating Temperature Range –40 to +85 °C Storage Temperature Range –65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Range http://onsemi.com 2 Rating Units –40 to +85 °C CM1241 Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1) Symbol Min Typ Max Units LV Diode Reverse Voltage (Positive Voltage) IF = 10 mA; TA = 25°C 6.8 8.2 9.2 V LV Diode Forward Voltage (Negative Voltage) IF = 10 mA; TA = 25°C –1.05 –0.9 –0.6 V LV Channel Leakage Current (Pins 1 and 2) TA = −30°C to 65°C; VIN = 3.3 V, VN = 0 V 100 nA LV Channel Leakage Current (Pin 3 only) TA = −30°C to 65°C; VIN = 3.3 V, VN = 0 V 100 nA CIN LV Channel Input Capacitance At 1 MHz, VN = 0 V, VIN = 1.65 V 1.2 1.5 pF ΔCIN LV Channel Input Capacitance Matching At 1 MHz, VN = 0 V, VIN = 1.65 V 0.02 ILEAK_HV HV Channel Leakage Current TA = 25°C; VCC = 11 V, VN = 0 V 0.1 CIN_HV HV Channel Input Capacitance At 1 MHz, VN = 0 V, VIN = 2.5 V 53 VF_HV HV Diode Breakdown Voltage Positive Voltage IF = 10 mA; TA = 25°C VESD ESD Protection Peak Discharge Voltage at any channel input, in system Contact discharge per IEC 61000−4−2 standard VF ILEAK VCL RDYN Parameter Conditions 14.6 pF 1.0 mA pF 17.7 V kV TA = 25°C ±8 (Pin 1−3) ±15 (Pin 4) LV Channel Clamp Voltage (Pin 1−3) Positive Transients Negative Transients TA = 25°C, IPP = 1 A, tP = 8/20 mS Dynamic Resistance LV Channel Positive Transients LV Channel Negative Transients HV Channel Positive Transients HV Channel Negative Transients IPP = 1 A, tP = 8/20 mS Any I/O pin to Ground V +9.64 –1.75 1. All parameters specified at TA = –40°C to +85°C unless otherwise noted. http://onsemi.com 3 0.72 0.59 1.20 0.36 W CM1241 PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves for Low Voltage Pins Figure 1. Typical Variation of CIN vs. VIN (Low Voltage Inputs, f = 1 MHz, VN = 0 V) Figure 2. Typical Variation of CIN vs. Temp (Low Voltage Inputs, f = 1 MHz, VN = 0 V) http://onsemi.com 4 CM1241 PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance for Low Voltage Pins Nominal conditions unless specified; otherwise, 50 W environment. Figure 3. Channel 1 vs. All GND Pins (0 V DC Bias) Figure 4. Channel 2 vs. All GND Pins (0 V DC Bias) http://onsemi.com 5 CM1241 PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance for Low Voltage Pins Nominal conditions unless specified; otherwise, 50 W environment. Figure 5. Channel 3 vs. All GND Pins (0 V DC Bias) http://onsemi.com 6 CM1241 PACKAGE DIMENSIONS WDFN8, 1.7x1.35, 0.4P CASE 511BF−01 ISSUE O PIN ONE REFERENCE 2X 0.10 C DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW (A3) DETAIL B 0.10 C 0.08 C SIDE VIEW DETAIL A D2 1 A1 C 8X 4 MOLD CMPD ÉÉÉ ÉÉÉ ÇÇÇ A3 A1 DETAIL B A NOTE 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 ÉÉ ÉÉ 0.10 C 2X L A B D SEATING PLANE ALTERNATE CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.15 0.25 1.7 BSC 1.10 1.30 1.35 BSC 0.30 0.50 0.40 BSC 0.22 REF 0.15 0.35 −−− 0.15 L E2 RECOMMENDED SOLDERING FOOTPRINT* K 8 5 e e/2 8X b 0.10 C A B 0.05 C 1.30 8X 0.43 NOTE 3 BOTTOM VIEW 1.65 0.50 0.25 0.40 PITCH 8X DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CM1241/D