ESD7451, SZESD7451 ESD Protection Diodes Micro−Packaged Diodes for ESD Protection The ESD7451 is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, the part is well suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications. www.onsemi.com 1 Anode 2 Anode Features • • • • • • • • • Ultra−Low Capacitance (0.35 pF Max) Low Clamping Voltage Stand−off Voltage: 3.3 V Low Leakage Response Time is < 1 ns Low Dynamic Resistance < 1 W IEC61000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • RF Signal ESD Protection • RF Switching, PA, and Antenna ESD Protection • Near Field Communications MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Air Human Body Model ESD (HBM) °PD° Value Unit ±25 ±25 ±8.0 kV 250 mW Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) MARKING DIAGRAM XDFN2 CASE 711AM E M EM G = Specific Device Code = Date Code ORDERING INFORMATION Device Package Shipping† ESD7451N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel SZESD7451N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2016 March, 2016 − Rev. 4 1 Publication Order Number: ESD7451/D ESD7451, SZESD7451 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage IR V Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage Conditions Min Typ VRWM Breakdown Voltage (Note 2) VBR IT = 1 mA Max Unit 3.3 V 6.0 V Reverse Leakage Current IR < 1.0 50 nA Clamping Voltage (Note 3) VC IPP = 1 A IPP = 3 A 10 13 V Clamping Voltage, ESD VC Per IEC61000−4−2 Waveform Clamping Voltage, TLP VC IPP = ±8 A IPP = ±16 A 13.5 18 V Dynamic Resistance RDYN TLP Pulse 0.55 W Junction Capacitance CJ VR = 0 V, f = 1 MHz VR = 0 V, f = 1 GHz 0.25 0.22 See Figures 1 & 2 0.35 0.35 pF 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform shown in Figure 9. 120 20 100 0 80 −20 VOLTAGE (V) VOLTAGE (V) TYPICAL CHARACTERISTICS 60 40 −40 −60 20 −80 0 −100 −20 −25 0 25 50 75 100 125 150 −120 −25 175 0 25 50 75 100 125 150 175 TIME (ns) TIME (ns) Figure 1. Typical IEC61000−4−2 + 8 kV Contact ESD Clamping Voltage Figure 2. Typical IEC61000−4−2 − 8 kV Contact ESD Clamping Voltage www.onsemi.com 2 ESD7451, SZESD7451 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup ESD Voltage Clamping at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform www.onsemi.com 3 80 ESD7451, SZESD7451 16 8 −16 12 6 10 −12 −10 8 4 6 4 2 2 0 0 6 −8 4 −6 −4 2 −2 2 4 6 8 10 12 14 VC, VOLTAGE (V) 16 18 0 20 0 0 2 Figure 6. Typical Positive TLP IV Curve NOTE: 4 6 8 10 12 14 VC, VOLTAGE (V) 16 0 20 18 Figure 7. Typical Negative TLP IV Curve TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 8. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 9 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 8. Simplified Schematic of a Typical TLP System Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4 EQUIVALENT VIEC (kV) −14 EQUIVALENT VIEC (kV) TLP CURRENT (A) TLP CURRENT (A) 14 8 ESD7451, SZESD7451 TYPICAL CHARACTERISTICS 1.0 1.E−04 0.9 1.E−05 0.8 CAPACITANCE (pF) 1.E−03 1.E−06 I (A) 1.E−07 1.E−08 1.E−09 1.E−10 0.6 0.5 0.4 0.3 0.2 1.E−11 1.E−12 −8 0.7 0.1 −6 −4 −2 0 V (V) 2 4 6 0 8 −3 −2 Figure 10. IV Characteristics 0 VBias (V) 1 2 3 Figure 11. CV Characteristics 2.0 2 1.8 0 1.6 −2 CAPACITANCE (pF) Db (ESD7451_882..S(2,1)) −1 −4 −6 −8 −10 1.4 1.2 1.0 0.8 0.6 0.4 −12 −14 0.2 1.E+08 1.E+09 FREQUENCY (Hz) 0.0 1.E+10 Figure 12. RF Insertion Loss 1.0 2.0 3.0 4.0 5.0 6.0 7.0 FREQUENCY (GHz) 8.0 9.0 Figure 13. Capacitance over Frequency www.onsemi.com 5 10 ESD7451, SZESD7451 PACKAGE DIMENSIONS XDFN2 1.0x0.6, 0.65P (SOD−882) CASE 711AM ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. 0.10 C ÉÉ ÉÉ A B D PIN 1 INDICATOR E DIM A A1 b D E e L 0.05 C TOP VIEW NOTE 3 0.10 C A 0.10 C A1 C SIDE VIEW MILLIMETERS MIN MAX 0.34 0.44 −−− 0.05 0.43 0.53 1.00 BSC 0.60 BSC 0.65 BSC 0.20 0.30 RECOMMENDED SOLDER FOOTPRINT* SEATING PLANE 1.20 2X e 2X 0.47 0.60 b e/2 0.05 M PIN 1 C A B 1 DIMENSIONS: MILLIMETERS 2X L 0.05 M *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. C A B BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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