MC100LVEL38 D

MC100LVEL38
3.3V ECL ÷2, ÷4/6 Clock
Generation Chip
Description
The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either a
differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as can happen with an
asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2 and the ÷4/6 outputs of a
single device.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
•
•
•
SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL38
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Features
•
•
•
•
•
•
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See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
Internal Input 75 kW Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Pb = Level 1
•
•
•
Pb−Free = Level 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 388 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2008
November, 2008 − Rev. 10
1
Publication Order Number:
MC100LVEL38/D
MC100LVEL38
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CLK
VBB
MR
VCC
EN DIV_SEL CLK
VCC Phase_Out Phase_Out
Figure 1. Pinout: 20-Lead SOIC (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Q0
CLK
÷2
CLK
R
Q0
Q1
Q1
Q2
EN
R
÷4/6
Q2
R
Q3
MR
Q3
DIVSEL
PHASE_OUT
Phase
Out
R Logic
PHASE_OUT
VBB
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Table 2. FUNCTION TABLE
Function
CLK, CLK
ECL Diff Clock Inputs
Q0, Q1; Q0, Q1
ECL Diff ÷2 Outputs
Q2, Q3; Q2, Q3
ECL Diff ÷4/6 Outputs
EN
ECL Sync Enable Input
MR
ECL Master Reset Input
DIVSEL
ECL Frequency Select Input
Phase_Out, Phase_Out
ECL Phase Sync Diff. Signal Output
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
CLK
EN
MR
Z
ZZ
X
L
H
X
L
L
H
Function
Divide
Hold Q0−3
Reset Q0−3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
X = Don’t Care
DVSEL
L
H
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2
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
MC100LVEL38
CLK
Q (÷2)
Q (÷4)
Q (÷6)
Phase_Out (÷4)
Phase_Out (÷6)
Figure 3. Timing Diagrams
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−20
SOIC−20
90
60
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−20
30 to 35
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Pb
Pb−Free
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC100LVEL38
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
50
60
Min
85°C
Typ
Max
50
60
Min
Typ
Max
Unit
54
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
1.65
2.75
1.65
2.75
1.65
2.75
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
150
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP Min and 1.0 V.
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 4)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
50
60
Min
85°C
Typ
Max
50
60
Min
Typ
Max
Unit
54
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 5)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
−1.65
−0.55
−1.65
−0.55
−1.65
−0.55
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP Min and 1.0 V.
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4
MC100LVEL38
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 7)
−40°C
Min
Characteristic
Symbol
fmax
Maximum Toggle Frequency (Figure 4)
Divide by 2
Divide by 4, Divide by 6
1.0
0.8
tPLH
tPHL
Propagation Delay to Output
CLK to Q (Differential)
CLK to Q (Single−Ended)
CLK to Phase_Out (Differential)
CLK to Phase_Out (Single−Ended)
MR to.Q
810
710
800
750
510
tSKEW
Within-Device Skew (Note 8)
Typ
25°C
Max
1.2
0.82
Min
1.0
0.8
1010
1010
1000
1050
810
850
750
840
790
540
Typ
85°C
Max
1.2
0.82
Min
1.0
0.8
1050
1050
1040
1090
840
900
800
890
840
570
Typ
Max
Unit
GHz
1.2
0.82
1100
1100
1090
1140
870
ps
Q0 − Q3
All
50
75
50
75
50
75
Part-to-Part
Q0 − Q3 (Differential)
All
200
240
200
240
200
240
tS
Setup Time
EN to CLK
DIVSEL to CLK
150
150
150
ps
tH
Hold Time
CLK to EN
CLK to Div_Sel
150
200
150
200
150
200
ps
VPP
Input Swing (Note 9)
CLK
250
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
tr, tf
Output Rise/Fall Times Q (20% − 80%)
1000
250
100
CLK
MR
800
700
1000
100
800
700
280
550
250
280
1000
mV
100
ps
800
700
550
280
ps
ps
550
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary ±0.3 V.
8. Skew is measured between outputs under identical transitions.
9. VPP(min) is minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down
to 100 mV.
Figure 4. Fmax: Voutpp vs Input Frequency per DIV2/4/6
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5
MC100LVEL38
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Package†
MC100LVEL38DW
SOIC−20
38 Units / Rail
MC100LVEL38DWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC100LVEL38DWR2
SOIC−20
1000 / Tape & Reel
MC100LVEL38DWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVEL38
PACKAGE DIMENSIONS
SO−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
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MC100LVEL38/D