SEMICONDUCTOR TECHNICAL DATA ÷ ÷ The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but is specified for operation at the standard 100K ECL voltage supply. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended LVECL or, if positive power supplies are used, LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL38 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. 20 1 The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. The Phase_Out output will go HIGH for one clock cycle whenever the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a HIGH. This output allows for clock synchronization within the system. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple LVEL38s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL38, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2 and the ÷4/6 outputs of a single device. • • • • • • 50ps Output-to-Output Skew Synchronous Enable/Disable DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 PIN DESCRIPTION PIN FUNCTION CLK EN MR VBB Q0, Q1 Q2, Q3 DIVSEL Phase_Out Diff Clock Inputs Sync Enable Master Reset Reference Output Diff ÷2 Outputs Diff ÷4/6 Outputs Frequency Select Input Phase Sync Signal Master Reset for Synchronization FUNCTION TABLE 75kΩ Internal Input Pulldown Resistors >1500V ESD Protection CLK EN MR Z ZZ X L H X L L H FUNCTION Low Voltage VEE Range of –3.0 to –3.8V Pinout: 20-Lead SOIC (Top View) VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 Z = Low-to-High Transition ZZ = High-to-Low Transition 3 4 EN DIV_SEL CLK 5 6 7 8 9 10 CLK VBB MR VCC Phase_Out VCC 2 Phase_Out DIVSEL 1 0 1 10/94 Motorola, Inc. 1996 4–1 Divide Hold Q0–3 Reset Q0–3 REV 1 Q2, Q3 OUTPUTS Divide by 4 Divide by 6 MC100LVEL38 MC100EL38 LOGIC DIAGRAM Q0 CLK ÷2 CLK R Q0 Q1 Q1 EN Q2 R ÷4/6 R MR Q2 Q3 Q3 DIVSEL Phase Out R Logic PHASE_OUT PHASE_OUT CLK Q (÷2) Q (÷4) Q (÷6) Phase_Out (÷4) Phase_Out (÷6) Figure 1. Timing Diagrams MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL38 MC100EL38 MC100LVEL38 DC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND) –40°C Symbol Characteristic IEE Power Supply Current VBB Output Reference Voltage IIH Input High Current Min 0°C Typ Max 50 60 –1.38 –1.26 Min 25°C Typ Max 50 60 –1.38 –1.26 150 Min 85°C Typ Max 50 60 –1.38 –1.26 150 Min Typ Max Unit 54 65 mA –1.38 150 –1.26 V 150 µΑ Max Unit MC100LVEL38 AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND) –40°C Symbol Characteristic Min fMAX Maximum Toggle Frequency 1000 tPLH tPHL Propagation Delay CLK → Q (Diff) to Output CLK → Q (S.E.) CLK → Phase_Out (Diff) CLK → Phase_Out (S.E.) MR → Q 760 710 800 750 510 tSKEW Within-Device Skew1 Typ 0°C Max Min Typ 25°C Max 1000 960 1010 1000 1050 810 Min Typ 85°C Max 1000 780 730 820 770 530 980 1030 1020 1070 830 Min Typ 1000 800 750 840 790 540 1000 1050 1040 1090 840 MHz 850 800 890 840 570 1050 1100 1090 1140 870 ps ps Q0 – Q3 All 50 75 50 75 50 75 50 75 Part-to-Part Q0 – Q3 (Diff) All 200 240 200 240 200 240 200 240 tS Setup Time EN → CLK DIVSEL → CLK 150 150 150 150 ps tH Hold Time CLK → EN CLK → Div_Sel 150 200 150 200 150 200 150 200 ps VPP2 Minimum Input Swing CLK 250 VCMR3 Common Mode Range tRR Reset Recovery Time tPW Minimum Pulse Width CLK MR 800 700 tr, tf Output Rise/Fall Times Q (20% – 80%) 280 CLK –0.55 250 See3 –0.55 100 250 See3 800 700 550 –0.55 100 280 250 See3 800 700 550 –0.55 100 280 mV See3 V 100 ps 800 700 550 280 ps 550 ps 1. Skew is measured between outputs under identical transitions. 2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP Min and 1.0V. The lower end of the CMR range is dependent on VEE and is equal to VEE + 1.65V. ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVEL38 MC100EL38 MC100EL38 DC CHARACTERISTICS (VEE = –4.2V to –5.46; VCC = GND) –40°C Symbol Characteristic IEE Power Supply Current VBB Output Reference Voltage IIH Input High Current Min 0°C Typ Max 50 60 –1.38 –1.26 Min 25°C Typ Max 50 60 –1.38 –1.26 150 Min 85°C Typ Max 50 60 –1.38 –1.26 150 Min Typ Max Unit 54 65 mA –1.38 150 –1.26 V 150 µΑ Max Unit MC100EL38 AC CHARACTERISTICS (VEE = –4.2V to –5.46; VCC = GND) –40°C Symbol Characteristic Min fMAX Maximum Toggle Frequency 1000 tPLH tPHL Propagation Delay CLK → Q (Diff) to Output CLK → Q (S.E.) CLK → Phase_Out (Diff) CLK → Phase_Out (S.E.) MR → Q 760 710 800 750 510 tSKEW Within-Device Skew1 Typ 0°C Max Min Typ 25°C Max 1000 960 1010 1000 1050 810 Min Typ 85°C Max 1000 780 730 820 770 530 980 1030 1020 1070 830 Min Typ 1000 800 750 840 790 540 1000 1050 1040 1090 840 MHz 850 800 890 840 570 1050 1100 1090 1140 870 ps ps Q0 – Q3 All 50 75 50 75 50 75 50 75 Part-to-Part Q0 – Q3 (Diff) All 200 240 200 240 200 240 200 240 tS Setup Time EN → CLK DIVSEL → CLK 150 150 150 150 ps tH Hold Time CLK → EN CLK → Div_Sel 150 200 150 200 150 200 150 200 ps VPP2 Minimum Input Swing CLK 250 VCMR3 Common Mode Range tRR Reset Recovery Time tPW Minimum Pulse Width CLK MR 800 700 tr, tf Output Rise/Fall Times Q (20% – 80%) 280 CLK –0.55 250 See3 –0.55 100 250 See3 800 700 550 –0.55 100 280 250 See3 800 700 550 –0.55 100 280 mV See3 V 100 ps 800 700 550 280 ps 550 ps 1. Skew is measured between outputs under identical transitions. 2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP Min and 1.0V. The lower end of the CMR range is dependent on VEE and is equal to VEE + 1.65V. MOTOROLA 4–4 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL38 MC100EL38 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A – 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 1 –B – P 10 PL A B 0.010 (0.25) M B M 10 D 20 PL 0.010 (0.25) J M T S S F R X 45° C –T G K 18 PL SEATING – PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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