MC14022B Octal Counter The MC14022B is a four−stage Johnson octal counter with built−in code converter. High−speed operation and spike−free outputs are obtained by use of a Johnson octal counter design. The eight decoded outputs are normally low, and go high only at their appropriate octal time period. The output changes occur on the positive−going edge of the clock pulse. This part can be used in frequency division applications as well as octal counter or octal decode display applications. http://onsemi.com Features • • • • • • • • • Fully Static Operation DC Clock Input Circuit Allows Slow Rise Times Carry Out Output for Cascading Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range Pin−for−Pin Replacement for CD4022B Triple Diode Protection on All Inputs NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) PIN ASSIGNMENT Q1 1 16 VDD Q0 2 15 R Q2 3 14 C Q5 4 13 CE Q6 5 12 Cout NC 6 11 Q4 Q3 7 10 Q7 VSS 8 9 NC NC = NO CONNECTION Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V MARKING DIAGRAM 16 Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Iin, Iout SOIC−16 D SUFFIX CASE 751B Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C 14022BG AWLYWW 1 A WL YY, Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 8 1 Publication Order Number: MC14022B/D MC14022B BLOCK DIAGRAM CLOCK 14 CLOCK ENABLE 13 RESET 15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Cout VDD = PIN 16 VSS = PIN 8 2 1 3 7 11 4 5 10 12 NC = PIN 6, 9 FUNCTIONAL TRUTH TABLE (Positive Logic) Clock Clock Enable 0 X Reset Output=n 0 0 0 0 0 0 1 n n n+1 n n+1 n Q0 X 1 0 X 1 X X X X = Don’t Care. If n < 4 Carry = 1, Otherwise = 0. LOGIC DIAGRAM 11 1 Q4 5 Q1 7 Q6 Q3 CLOCK 14 13 CLOCK ENABLE 15 RESET VDD VSS C Q C D RQ C Q C D RQ Q0 2 Q5 4 http://onsemi.com 2 C Q C D RQ C Q C D RQ Q2 3 Q7 10 CARRY 12 MC14022B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (0.28 mA/kHz)f + IDD IT = (0.56 mA/kHz)f + IDD IT = (0.85 mA/kHz)f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.00125. http://onsemi.com 3 MC14022B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Reset to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns tPLH, tPHL Propagation Delay Time Clock to Cout tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 142 ns tPLH, tPHL = (0.5 ns/pF) CL + 100 ns tPLH, tPHL Propagation Delay Time Clock to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns tPLH, tPHL Turn−Off Delay Time Reset to Cout tPLH = (1.7 ns/pF) CL + 315 ns tPLH = (0.66 ns/pF) CL + 142 ns tPLH = (0.5 ns/pF) CL + 100 ns tPLH Clock Pulse Width VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns 5.0 10 15 − − − 500 230 175 1000 460 350 ns 5.0 10 15 − − − 400 175 125 800 350 250 ns 5.0 10 15 − − − 275 125 95 1000 460 350 ns 5.0 10 15 − − − 400 175 125 800 350 250 tWH 5.0 10 15 250 100 75 125 50 35 − − − ns fcl 5.0 10 15 − − − 5.0 12 16 2.0 5.0 6.7 MHz Reset Pulse Width tWH 5.0 10 15 500 250 190 250 125 95 − − − ns Reset Removal Time trem 5.0 10 15 750 275 210 375 135 105 − − − ns tTLH, tTHL 5.0 10 15 Clock Frequency Clock Input Rise and Fall Time − No Limit Clock Enable Setup Time tsu 5.0 10 15 350 150 115 175 75 52 − − − ns Clock Enable Removal Time trem 5.0 10 15 420 200 140 260 100 70 − − − ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14022B VDD VSS VDD VSS A S1 B Output Sink Drive Output Source Drive Outputs (S1 to A) Clock to desired Output (S1 to B) Carry Clock to Q5 thru Q7 (S1 to B) VGS = VDD − VDD VDS = Vout Vout − VDD Vout CLOCK Q0 ENABLE Q1 Q2 Q3 RESET Q4 Q5 Q6 Q7 CLOCK C out ID EXTERNAL POWER SUPPLY VSS S1 to A Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit VDD 500 mF 0.01 mF CERAMIC ID Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Cout CLOCK ENABLE RESET PULSE GENERATOR fc CLOCK CL VSS CL CL CL CL CL CL CL CL Figure 2. Typical Power Dissipation Test Circuit APPLICATIONS INFORMATION Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). C R CE MC14022B Q0 Q1 • • • Q6 Q7 7 DECODED OUTPUTS C R CE MC14022B Q0 Q1 • • • Q6 Q7 6 DECODED OUTPUTS C R CE MC14022B Q1 • • • Q6 Q7 6 DECODED OUTPUTS CLOCK FIRST STAGE INTERMEDIATE STAGES Figure 3. Counter Expansion http://onsemi.com 5 LAST STAGE MC14022B tWH tWL 90% CLOCK trel CLOCK ENABLE tsu 20 ns trem 10% 20 ns 20 ns 20 ns VDD 20 ns VSS tPLH tPHL tPLH 50% tPLH tPHL tTHL 90% Q1 VSS VDD RESET Q0 VDD 50% VSS tPLH tPHL VOH VOL VOH 50% 10% VOL tTLH VOH Q2 tPLH tPHL VOL tTLH VOH Q3 tPLH tPHL VOL tTLH VOH Q4 tPLH Q5 tTLH tPHL tPLH VOL tPHL VOH tTLH tTHL VOL tTHL VOH tTLH tPHL Q6 VOL tPLH tPHL VOH Q7 tPHL Cout tTLH tPLH tTHL VOL VOH tPHL VOL tTLH tTHL Figure 4. AC Measurement Definition and Functional Waveforms ORDERING INFORMATION Package Shipping† MC14022BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14022BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14022BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 6 MC14022B PACKAGE DIMENSIONS SOIC−16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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