MC14516B D

MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P−channel and N−channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog−to−Digital and Digital−to−Analog conversions,
and (3) Magnitude and sign generation.
Features
•
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge−Clocked Design — Count Occurs on Positive Going
Edge of Clock
Single Pin Reset
Asynchronous Preset Enable Operation
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky Load Over the Rated Temperature Range
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
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MARKING
DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
1
A
WL
Y
WW
G
16
14516BG
AWLYWW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused
outputs must be left open.
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
± 10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature (8−Second Soldering)
TL
260
°C
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “DW” Packages:
– 7.0 mW/_C From 65_C To 125_C
© Semiconductor Components Industries, LLC, 2014
March, 2014 − Rev. 10
1
Publication Order Number:
MC14516B/D
MC14516B
PIN ASSIGNMENT
PE
1
16
VDD
Q3
2
15
C
P3
3
14
Q2
P0
4
13
P2
CARRY IN
5
12
P1
Q0
6
11
Q1
CARRY OUT
7
10
U/D
VSS
8
9
BLOCK DIAGRAM
R
1
PE
5
CARRY IN
9
RESET
10
UP/DOWN
15
CLOCK
4
P0
12
P1
13
P2
3
P3
Q0
6
Q1
11
Q2
14
Q3
2
CARRY
OUT
7
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Carry In
Up/Down
Preset Enable
Reset
Clock
Action
1
X
0
0
X
No Count
0
1
0
0
Count Up
0
0
0
0
Count Down
X
X
1
0
X
Preset
X
X
X
1
X
Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only when Q0 through Q3 are high and Carry In is low. When
counting down, Carry Out is low only when Q0 through Q3 and Carry In are low.
ORDERING INFORMATION
Package
Shipping†
MC14516BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14516BDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
Device
NLV14516BDR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14516B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
25_C
VDD
125_C
Symbol
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
Input Capacitance (Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
“0” Level
“1” Level
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Source
Sink
VIL
Vdc
VIH
Vdc
IOH
mAdc
IT = (0.58 mA/kHz) f + IDD
IT = (1.20 mA/kHz) f + IDD
IT = (1.70 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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3
MC14516B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Clock to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
VDD
Min
Typ (Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
−
−
−
315
130
100
630
260
200
5.0
10
15
−
−
−
315
130
100
630
260
200
5.0
10
15
−
−
−
180
80
60
360
160
120
5.0
10
15
−
−
−
315
130
100
630
360
200
5.0
10
15
−
−
−
550
225
150
1100
450
300
ns
ns
ns
ns
Reset Pulse Width
tw
5.0
10
15
380
200
160
190
100
80
−
−
−
ns
Clock Pulse Width
tWH
5.0
10
15
350
170
140
200
100
75
−
−
−
ns
fcl
5.0
10
15
−
−
−
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time
The Preset or Reset signal must be low prior to a
positive−going transition of the clock.
trem
5.0
10
15
650
230
180
325
115
90
−
ns
Clock Rise and Fall Time
tTLH,
tTHL
5.0
10
15
−
−
−
−
−
−
15
5
4
ms
Setup Time
Carry In to Clock
tsu
5.0
10
15
260
120
100
130
60
50
−
−
−
ns
Hold Time
Clock to Carry In
th
5.0
10
15
0
20
20
– 60
– 20
0
−
−
−
ns
Setup Time
Up/Down to Clock
tsu
5.0
10
15
500
200
150
250
100
75
−
−
−
ns
Hold Time
Clock to Up/Down
th
5.0
10
15
– 70
– 10
0
– 160
– 60
– 40
−
−
−
ns
Setup Time
Pn to PE
tsu
5.0
10
15
– 40
– 30
– 25
– 120
– 70
– 50
−
−
−
ns
Hold Time
PE to Pn
th
5.0
10
15
480
420
420
240
210
210
−
−
−
ns
tWH
5.0
10
15
200
100
80
100
50
40
−
−
−
ns
Clock Pulse Frequency
Preset Enable Pulse Width
−
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
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4
MC14516B
VDD
500 pF
ID
PE
0.01 mF
CERAMIC
Q0
CARRY IN
R
Q1
UP/DOWN
PULSE
GENERATOR
CLOCK
20 ns
20 ns
CL
Q2
Q3
P3
CARRY
OUT
10%
VARIABLE
WIDTH
CL
P0
P1
P2
VDD
90%
50%
CLOCK
CL
CL
CL
Figure 1. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
P0
4
RESET
9
PRESET
ENABLE
1
Q0
6
P1 Q1
12 11
P2
13
Q2
14
P3
3
CLOCK 15
PE
P
PE
Q
C
CARRY OUT
Q
C
PE
P
Q
C
PE
P
Q
C
7
T
CARRY IN
P
Q
T
Q
5
UP/DOWN 10
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5
T
Q
T
Q
Q3
2
VSS
MC14516B
TOGGLE FLIP−FLOP
FLIP−FLOP FUNCTIONAL TRUTH TABLE
PARALLEL IN
PE
P
Preset
Enable
Clock
T
Qn+1
1
X
X
Parallel In
0
0
Qn
0
1
Qn
0
X
Qn
Q
C
T
Q
X = Don’t Care
tsu
trem
1
fcl
th
CARRY IN OR
UP/DOWN
VDD
50%
VSS
VDD
50%
CLOCK
VSS
tw(H)
tw(H)
VDD
PRESET ENABLE
VSS
tTLH
CARRY OUT ONLY
Q0 OR CARRY OUT
VOH
90%
10%
90%
10%
VOL
tPHL
tTHL
tPLH
tPLH
trem
VDD
50%
RESET
VSS
tw
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — This active−low input is used when
Cascading stages. Carry In is usually connected to Carry Out
of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or
decremented, depending on the direction of count, on the
positive transition of this input.
PE, Preset Enable, (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q out−
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count,
high for up count, low for down count.
OUTPUTS
VSS, Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) — This pin is
connected to a positive supply voltage ranging from 3.0 V
to 18 V.
SUPPLY PINS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0
corresponding to the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
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6
MC14516B
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
PE
Q1
Q2
Q3
Q0
PE
Q1
Q2
Q3
Cout
Cin
PRESET
ENABLE
0 = COUNT
1 = PRESET
Cin
CLOCK
1 = UP
0 = DOWN
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P0
P1
P2
CLOCK
P3
U/D
R
P0
P1
P2
P3
P3
P4
P5
P6
P7
+VDD
CLOCK
+VDD
Cout
M.S.D.
MC14516B
TERMINAL COUNT
INDICATOR
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0")
RESISTORS = 10 kW
RESET
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8−Bit Up/Down Counter
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7
8
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COUNT
RESET
CARRY OUT
(LSD)
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CARRY OUT
(MSD)
P0
P1
P2
P3
P4
P5
P6
P7
PE
CARRY IN
(MSD)
UP/DOWN
CLOCK
13
15
16
UP COUNT
PRESET ENABLE
14
17
18
19
18
17
15
DOWN COUNT
16
14
13
PRESET
ENABLE
251
252
UP COUNT
253 254 255
0
1
2
3
1
DOWN
COUNT
2
0
1
RESET
UP COUNT
2
MC14516B
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8−BIT UP/DOWN COUNTER
MC14516B
fout
BUFFER
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
PE
Q1
Q2
Q3
Q0
PE
Q1
Q2
Q3
Cout
Cin
Cin
CLOCK
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P0
P1
P2
Cout
M.S.D.
MC14516B
CLOCK
P3
U/D
R
P0
P1
P2
P3
P3
P4
P5
P6
P7
+VDD
+VDD
CLOCK (fin)
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0")
RESISTORS = 10 kW
RESET
fout =
fin
n
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
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9
MC14516B
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC14516B/D