MC14585B D

MC14585B
4-Bit Magnitude Comparator
The MC14585B 4−Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The circuit
has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0), three
cascading inputs (A < B, A = B, and A > B), and three outputs (A < B,
A = B, and A > B). This device compares two 4−bit words (A and B)
and determines whether they are “less than”, “equal to”, or “greater
than” by a high level on the appropriate output. For words greater than
4−bits, units can be cascaded by connecting outputs (A > B), (A < B),
and (A = B) to the corresponding inputs of the next significant
comparator. Inputs (A < B), (A = B), and (A > B) on the least significant
(first) comparator are connected to a low, a high, and a low, respectively.
Applications include logic in CPU’s, correction and/or detection of
instrumentation conditions, comparator in testers, converters, and
controls.
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1
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Features
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Expandable
Applicable to Binary or 8421−BCD Code
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
Can be Cascaded − See Figure 3
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
This Device is Pb−Free and is RoHS Compliant
B2
1
16
VDD
A2
2
15
A3
(A = B)out
3
14
B3
(A u B)in
4
13
(A u B)out
(A t B)in
5
12
(A t B)out
(A = B)in
6
11
B0
A1
7
10
A0
VSS
8
9
B1
MARKING DIAGRAM
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
16
Symbol
Value
Unit
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature (8−Second Soldering)
TL
260
°C
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9
1
14585BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
MC14585BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14585BDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
NLV14585BDR2G*
SOIC−16
(Pb−Free)
2500/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC14585B/D
MC14585B
BLOCK DIAGRAM
(A>B)in
(A=B)in
(A<B)in
A0
B0
A1
B1
A2
B2
A3
B3
4
6
5
10
11
7
9
2
1
15
14
(A>B)out
13
(A=B)out
3
(A<B)out
12
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE (x = Don’t Care)
Inputs
Comparing
Cascading
Outputs
A3, B3
A2, B2
A1, B1
A0, B0
A<B
A=B
A>B
A<B
A=B
A>B
A3 > B3
A3 = B3
A3 = B3
A3 = B3
x
A2 > B2
A2 = B2
A2 = B2
x
x
A1 > B1
A1 = B1
x
x
x
A0 > B0
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
A0 = B0
0
0
1
1
0
1
0
1
x
x
x
x
0
0
1
1
0
1
0
1
1
0
0
0
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 < B2
A1 = B1
A1 < B1
x
A0 < B0
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
0
0
0
0
0
A3 < B3
x
x
x
x
x
x
1
0
0
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MC14585B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
–55_C
Symbol
Characteristic
Output Voltage
Vin = VDD or 0
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance (Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
Vin = 0 or VDD
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
IT = (0.6 mA/kHz) f + IDD
IT = (1.2 mA/kHz) f + IDD
IT = (1.8 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Turn−On, Turn−Off Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 345 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
tPLH,
tPHL
VDD
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
430
180
130
860
360
260
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
Unit
MC14585B
20 ns
20 ns
VDD
A3
VSS
1
2f
VDD
B3
VSS
20 ns
20 ns
VOH
(A>B)out
VDD
90%
VOL
50%
B0
VOH
10%
VSS
tPHL
tPLH
(A=B)out
VOL
50%
(A<B)out
10%
VOL
VOL
tTLH
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low.
f in respect to a system clock.
Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
A2, B1, A1, A0, and (A<B) low.
Figure 2. Dynamic Signal Waveforms
(A>B)
(A=B)
(A<B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT
MC14585B
MC14585B
WORD B = B11, B10, ..., B0.
WORD A = A11, A10, ..., A0.
(A>B)
(A=B)
MC14585B
OUTPUTS
Figure 3. Cascading Comparators
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4
VSS VDD VSS
(A>B)
WORD
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B = B11
WORD
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A=
(A<B)
Figure 1. Dynamic Power Dissipation
Signal Waveforms
(A<B)
tTHL
(A=B)
(A<B)out
VOH
90%
VOH
INPUTS
MC14585B
LOGIC DIAGRAM
A3
B3
A2
B2
A1
B1
A0
B0
(A<B)in
15
14
2
1
12
7
9
10
11
5
3
(A=B)in
(A>B)in
(A<B)out
6
13
4
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5
(A=B)out
(A>B)out
MC14585B
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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MC14585B/D