NB6LQ572 D

NB6LQ572
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 LVPECL Clock/Data
Fanout / Translator
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Multi−Level Inputs w/ Internal Termination
The NB6LQ572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock / Data fanout buffer that
operates up to 5 GHz / 6.5 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572, which is pin−compatible to the NB6LQ572.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572 incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
LVPECL output copies of Clock or Data. As such, the NB6LQ572 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The two differential LVPECL outputs will swing 750 mV when
externally loaded and terminated with a 50 W resistor to VCC – 2 V
and are optimized for low skew and minimal jitter.
The NB6LQ572 is offered in a low profile 5x5 mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6LQ572 is a member of the ECLinPS MAX™ family of
high performance clock products.
MARKING
DIAGRAM
1
1
32
QFN32
MN SUFFIX
CASE 488AM
NB6L
Q572
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Data Rate > 6.5 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 5 GHz Typical
Random Clock Jitter < 0.8ps RMS
Fixed Input Equalization
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 Multi−Level Mux Inputs, accepts LVPECL, CML LVDS
150ps Typical Propagation Delay
55ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peak−to−peak, typical
Operating Range: VCC = 2.375 V to 3.6 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN−32 Package, 5mm x 5mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 0
1
Publication Order Number:
NB6LQ572/D
NB6LQ572
Multilevel Inputs
LVPECL, LVDS, CML
IN0
VT0
IN0
50 W
EQ0
50 W
0
VREFAC0
IN1
VT1
IN1
LVPECL OUTPUTS
50 W
EQ1
50 W
IN2
IN2
Q0
4:1 MUX
VREFAC1
VT2
Q0
1
50 W
50 W
EQ2
2
EQ3
3
Q1
Q1
VREFAC2
IN3
VT3
IN3
50 W
50 W
VREFAC3
SEL0
SEL1
IN3
VREFAC3
VT3
IN3
IN2
VREFAC2
VT2
IN2
Figure 1. Simplified Block Diagram
32
31
30
29
28
27
26
25
Table 1. Input Select Function Table
Exposed
Pad (EP)
SEL1*
SEL0*
Clock / Data Input Selected
0
0
IN0 Input Selected
2
23
VCC
1
0
IN2 Input Selected
VREFAC0
3
22
Q1
1
1
IN3 Input Selected
IN0
4
21
Q1
IN1
5
20
VCC
VT1
6
19
NC
VREFAC1
7
18
SEL1
IN1
8
17
VCC
9
10
11
12
13
14
15
16
VCC
VT0
SEL0
IN1 Input Selected
NC
1
VCC
0
Q0
GND
Q0
24
VCC
1
GND
IN0
*Defaults HIGH when left open.
Figure 2. Pinout: QFN−32 (Top View)
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2
NB6LQ572
Table 2. PIN DESCRIPTION
Pin Number
Pin Name
I/O
1, 4
5, 8
25, 28
29, 32
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
LVPECL, CML,
LVDS Input
2, 6
26, 30
VT0, VT1
VT2, VT3
15
18
SEL0
SEL1
LVTTL/LVCMOS
Input
14, 19
NC
−
No Connect
10, 13, 16
17, 20, 23
VCC
−
Positive Supply Voltage.
11, 12
21, 22
Q0, Q0
Q1, Q1
LVPECL Output
9, 24
GND
3
7
27
31
VREFAC0
VREFAC1
VREFAC2
VREFAC3
−
Output Voltage Reference for Capacitor−Coupled Inputs
−
EP
−
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die, and
must be electrically connected to GND.
Pin Description
Noninverted, Inverted, Differential Clock or Data Inputs
Internal 100 W Center−tapped Termination Pin for INx / INx
Input Select pins, default HIGH when left open through a 94 kW pullup resistor.
Input logic threshold is VCC / 2. See Select Function, Table 1.
Non−inverted, Inverted Differential Outputs.
Negative Supply Voltage
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or
left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB6LQ572
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
RPU − SELx Input Pull−up Resistor
94 kW
Moisture Sensitivity (Note 3)
Flammability Rating
QFN−32
Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
221
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
−0.5 to +4.0
V
VIN
Positive Input Voltage
GND = 0 V
−0.5 to VCC +0.5
V
VINPP
Differential Input Voltage |IN – IN|
1.89
V
IOUT
LVPECL Output Current
50
100
mA
IIN
Input current Through RT (50 W resistor)
$40
mA
IVREFAC
VREFAC Sink or Source Current
$1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient) (Note 4)
31
27
°C/W
qJC
Thermal Resistance (Junction−to−Case) (Note 4)
12
°C/W
Tsol
Wave Solder
265
°C
Continuous
Surge
0 lfpm
500 lfpm
QFN−32
QFN−32
QFN−32
v 20 sec
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6LQ572
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
(Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
2.375
3.0
2.5
3.3
2.625
3.6
V
75
110
mA
POWER SUPPLY
VCC
Power Supply Voltage
ICC
Power Supply Current for VCC (Inputs and Outputs Open)
VCC = 2.5 V
VCC = 3.3 V
LVPECL OUTPUTS
VOH
Output HIGH Voltage (Note 6)
VOL
Output LOW Voltage (Note 6)
VCC = 2.5 V
VCC = 3.3 V
VCC – 1145
1355
2155
VCC – 900
1600
2400
VCC – 800
1700
2500
mV
VCC = 2.5 V
VCC = 3.3 V
VCC – 2000
500
1300
VCC − 1700
800
1600
VCC – 1500
1000
1800
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 and 6)
VIH
Single−ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
Vth – 100
mV
Vth
Input Threshold Reference Voltage Range (Note 8)
1100
VCC – 100
mV
VISE
Single−ended Input Voltage (VIH – VIL)
200
1200
mV
VCC – 900
mV
VREFAC
VREFAC
VCC – 1300
Output Reference Voltage (100 mA Load)
VCC – 1100
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 7 and 8)
VIHD
Differential Input HIGH Voltage (INx, INx)
1200
VCC
mV
VILD
Differential Input LOW Voltage (INx, INx)
0
VIHD – 100
mV
VID
Differential Input Voltage (INx, INx) (VIHD – VILD)
100
1200
mV
VCMR
Input Common Mode Range (Differential Configuration)
(Note 10) (Figure 9)
1150
VCC – 50
mV
IIH
Input HIGH Current INx/INx (VTx/VTx Open)
−150
150
mA
IIL
Input LOW Current INx/INx (VTx/VTx Open)
−150
150
mA
VCC
V
CONTROL INPUT (SELx Pin)
VIH
Input HIGH Voltage for Control Pin
2.0
VIL
Input LOW Voltage for Control Pin
GND
0.8
V
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
55
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with VCC.
6. LVPECL outputs loaded with 50 W to VCC − 2 V for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
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NB6LQ572
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 11)
Min
Typ
fMAX
Maximum Input Clock Frequency
Characteristic
VOUT w 450 mV
5
6
GHz
fDATAMAX
Maximum Operating Data Rate
NRZ, (PRBS23)
6.5
8
Gbps
fSEL
Maximum Toggle Frequency, SELx
4
10
MHz
VOUTPP
Output Voltage Amplitude (@ VINPPmin) fin ≤ 5 GHz (Note 11) (Figures 3 and 10)
450
800
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs
Measured at Differential Crosspoint
100
175
5
tPD Tempco
Differential Propagation Delay Temperature Coefficient
100
tskew
Output – Output skew (within device) (Note 13)
Device – Device skew (tpdmax – tpdmin)
0
30
15
100
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
50
55
%
FN
Phase Noise, fin = 1 GHz
tŐFN
tJITTER
Symbol
INx/INx to Qx/Qx @1 GHz
@ 50 MHz SELn to Qx
fin = 1 GHz
45
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Max
250
10
Unit
ps
ns
Dfs/°C
−134
−136
−149
−150
−150
dBc
Integrated Phase Jitter (Figure 1) fin = 1GHz, 12 kHz − 20 MHz Offset (RMS)
35
fs
Random Clock Jitter, RJ(RMS), (Note 14)
Deterministic Jitter, DJ (Note 15)
0.2
Crosstalk Induced Jitter (Adjacent Channel) (Note 16)
VINPP
Input Voltage Swing (Differential Configuration) (Note 17)
100
tr,, tf
Output Rise/Fall Times @ 1 GHz; (20% − 80%), Qx, Qx
25
50
0.8
10
ps
0.7
psRMS
1200
mV
75
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC − 2 V. Input edge rates 40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
17. Input voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE
(mV)
900
850
Q AMP (mV)
800
750
700
650
600
550
500
0
1.0
2.0
3.0
4.0
5.0
6.0
fin, CLOCK INPUT FREQUENCY (GHz)
7.0
8.0
Figure 3. Clock Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
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NB6LQ572
VCC
IN
VIH
Vth
INx
VIL
50 W
VTx
IN
Vth
50 W
INx
Figure 5. Differential Input Driven Single−Ended
Figure 4. Input Structure
VCC
VIHmax
Vthmax
Vth
VILmax
IN
VIH
Vth
VIL
IN
IN
VIHmin
Vthmin
VILmin
VEE
Figure 6. Vth Diagram
Figure 7. Differential Inputs Driven Differentially
VCC
VIHDmax
VILDmax
VCMmax
IN
IN
IN
VID = |VIHD(IN) − VILD(IN)|
VCMR
VIHD
VIHDtyp
VILDtyp
IN
VILD
VID = VIHD − VILD
VIHDmin
VCMmin
VILDmin
VEE
Figure 8. Differential Inputs Driven Differentially
Figure 9. VCMR Diagram
IN
VCC / 2
VINPP = VIH(IN) − VIL(IN)
IN
VCC / 2
SELx
tpd
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tpd
Q
Q
tPHL
tPLH
Figure 11. SELx to Qx Timing Diagram
Figure 10. AC Reference Measurement
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NB6LQ572
VCC
VCC
VCC
NB6LQ572
IN
Zo = 50 W
LVPECL
Driver
VCC
VT = VCC − 2.0 V
50 W
50 W
LVDS
Driver
50 W
Zo = 50 W
VT = OPEN
50 W
Zo = 50 W
IN
CLKx
IN
CLKx
GND
GND
GND
Figure 12. LVPECL Interface
VCC
GND
Figure 13. LVDS Interface
VCC
Zo = 50 W
NB6LQ572
IN
Zo = 50 W
VCC
VCC
NB6LQ572
IN
Zo = 50 W
NB6LQ572
IN
50 W
CML
Driver
50 W
Differential
Driver
VT = VCC
50 W
Zo = 50 W
VT = VREFAC*
50 W
Zo = 50 W
IN
GND
IN
GND
GND
GND
Figure 15. Capacitor−Coupled Differential
Interface (VT Connected to External VREFAC)
Figure 14. Standard 50 W Load CML Interface
*VREFAC bypassed to ground with a 0.01 mF capacitor.
ZO = 50 W
Q
Driver
Device
D
ZO = 50 W
Q
D
50 W
Receiver
Device
50 W
VTT
VTT = VCC − 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
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NB6LQ572
VTx
Q
Driver
FR4 − 12 Inch Backplane
NB6LQ572
Equalizer
INx
Q
INx
DJ1
DJ2
DJ3
Figure 17. Typical NB6LQ572 Equalizer Application and Interconnect with PRBS23 Pattern at 6.5 Gbps
DEVICE ORDERING INFORMATION
Package
Shipping†
NB6LQ572MNG
QFN−32
(Pb−Free)
74 Units / Rail
NB6LQ572MNR4G
QFN−32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB6LQ572
PACKAGE DIMENSIONS
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
SOLDERING FOOTPRINT*
EXPOSED PAD
16
K
5.30
32 X
17
8
3.20
E2
1
32 X
0.63
24
32
25
32 X b
0.10 C A B
3.20
e
5.30
0.05 C
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NB6LQ572/D