NB6VQ572M 1.8V / 2.5V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator http://onsemi.com Multi−Level Inputs w/ Internal Termination MARKING DIAGRAM Description The NB6VQ572M is a high performance differential 4:1 Clock / Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that operates up to 5 GHz / 6.5 Gbps respectively with a 1.8 V or 2.5 V power supply. Each INx / INx input pair incorporates a fixed Equalizer Receiver, which when placed in series with a Clock / Data path, will enhance the degraded signal transmitted across an FR4 backplane or cable interconnect. For applications that do not require Equalization, consider the NB7V572M, which is pin−compatible to the NB6VQ572M. The differential Clock / Data inputs have internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The NB6VQ572M incorporates a pair of Select pins that will choose one of four differential inputs and will produce two identical CML output copies of Clock or Data. As such, the NB6VQ572M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The two differential CML outputs will swing 400 mV when externally loaded and terminated with a 50 W resistor to VCC and are optimized for low skew and minimal jitter. The NB6VQ572M is offered in a low profile 5x5 mm 32−pin QFN Pb−Free package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6VQ572M is a member of the ECLinPS MAX™ family of high performance clock products. Features • • • • • • • • April, 2009 − Rev. 0 1 32 QFN32 MN SUFFIX CASE 488AM NB6V Q572M AWLYYWWG G A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. • Differential CML Outputs, 400 mV Peak−to−Peak, Input Data Rate > 6.5 Gb/s Typical Data Dependent Jitter < 10 ps Maximum Input Clock Frequency > 5 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:2 CML Outputs, < 15 ps max 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML, LVDS 175 ps Typical Propagation Delay 45 ps Typical Rise and Fall Times © Semiconductor Components Industries, LLC, 2009 1 • • • • • • 1 Typical Operating Range: VCC = 1.71 V to 2.625 V with GND =0V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN−32 Package, 5mm x 5mm, Pb−Free −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices Publication Order Number: NB6VQ572M/D NB6VQ572M Multilevel Inputs LVPECL, LVDS, CML IN0 50 W VT0 EQ0 50 W IN0 0 VREFAC0 IN1 CML OUTPUTS Q0 50 W VT1 EQ1 50 W IN1 1 4:1 MUX VREFAC1 IN2 50 W VT2 50 W IN2 Q0 EQ2 2 EQ3 3 Q1 Q1 VREFAC2 IN3 50 W VT3 50 W IN3 VREFAC3 SEL0 SEL1 IN3 VREFAC3 VT3 IN3 IN2 VREFAC2 VT2 IN2 Figure 1. Simplified Block Diagram 32 31 30 29 28 27 26 25 Table 1. INPUT SELECT FUNCTION TABLE Exposed Pad (EP) SEL1* SEL0* Clock / Data Input Selected 0 0 IN0 Input Selected IN0 1 24 GND 0 1 IN1 Input Selected VT0 2 23 VCC 1 0 IN2 Input Selected VREFAC0 3 22 Q1 1 1 IN3 Input Selected IN0 4 21 Q1 IN1 5 20 VCC VT1 6 19 NC VREFAC1 7 18 SEL1 IN1 8 17 VCC 9 10 11 12 13 14 15 16 GND VCC Q0 Q0 VCC NC SEL0 VCC NB6VQ572M *Defaults HIGH when left open. Figure 2. Pinout: QFN−32 (Top View) http://onsemi.com 2 NB6VQ572M Table 2. PIN DESCRIPTION Pin Number Pin Name I/O 1, 4 5, 8 25, 28 29, 32 IN0, IN0 IN1, IN1 IN2, IN2 IN3, IN3 LVPECL, CML, LVDS Input Pin Description 2, 6 26, 30 VT0, VT1 VT2, VT3 15 18 SEL0 SEL1 LVTTL/LVCMOS Input 14, 19 NC − No Connect 10, 13, 16 17, 20, 23 VCC − Positive Supply Voltage. 11, 12 21, 22 Q0, Q0 Q1, Q1 CML Output 9, 24 GND 3 7 27 31 VREFAC0 VREFAC1 VREFAC2 VREFAC3 − Output Voltage Reference for Capacitor−Coupled Inputs − EP − The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND. Noninverted, Inverted, Differential Clock or Data Inputs Internal 100 W Center−tapped Termination Pin for INx / INx Input Select pins, default HIGH when left open through a 94 kW pullup resistor. Input logic threshold is VCC/2. See Select Function, Table 1. Inverted, Non−inverted Differential Outputs. Negative Supply Voltage 1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation. 2. All VCC, and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 3 NB6VQ572M Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 2 kV > 200 V RPU − SELx Input Pullup Resistor 94kW Moisture Sensitivity (Note 3) QFN−32 Flammability Rating Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 221 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V 3.0 V VIN Positive Input Voltage GND = 0 V −0.5 to VCC +0.5 V VINPP Differential Input Voltage |IN − IN| 1.89 V Iout Output Current Through RT (50 W Resistor) $40 mA IIN Input current Through RT (50 W Resistor) $40 mA IVREFAC VREFAC Sink or Source Current $1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 4) QFN−32 12 °C/W Tsol Wave Solder 265 °C 0 lfpm 500 lfpm v 20 sec Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB6VQ572M Table 5. DC CHARACTERISTICS CML OUTPUT VCC = 1.71 V to 2.625 V , GND = 0 V, TA = −40°C to +85°C (Note 5) Characteristic Symbol Min Typ Max Unit POWER SUPPLY VCC Power Supply Voltage VCC = 2.5 V VCC = 1.8 V 2.375 1.71 2.5 1.8 2.625 1.89 V ICC Power Supply Current for VCC (Inputs and Outputs Open) VCC = 2.5 V VCC = 1.8 V 70 60 105 85 140 120 mA VCC = 2.5 V VCC = 1.8 V VCC − 30 2470 1770 VCC − 10 2490 1790 VCC 2500 1800 mV VCC = 2.5 V VCC =1.8 V VCC − 550 1950 1250 VCC − 450 2050 1350 VCC − 350 2150 1450 mV CML OUTPUTS (Note 6) VOH Output HIGH Voltage VOL Output LOW Voltage DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 7 and 8) (Note 7) VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV Vth Input Threshold Reference Voltage Range (Note 8) 1100 VCC − 100 mV VISE Single−ended Input Voltage (VIH − VIL) 200 1200 mV VCC − 450 mV VREFAC VREFAC VCC − 700 Output Reference Voltage (100 mA Load) VCC − 550 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 and 10) (Note 9) VIHD Differential Input HIGH Voltage (IN, IN) 1200 VCC mV VILD Differential Input LOW Voltage (IN, IN) 0 VIHD − 100 mV VID Differential Input Voltage (IN, IN) (VIHD − VILD) 100 1200 mV VCMR Input Common Mode Range (Differential Configuration, Note 10) (Figure 11) 1150 VCC − 50 mV IIH Input HIGH Current IN / IN (VTIN/VTIN Open) −150 150 mA IIL Input LOW Current IN / IN (VTIN/VTIN Open) −150 150 mA CONTROL INPUT (SELx Pin) VIH Input HIGH Voltage for Control Pin VCC x 0.65 VCC V VIL Input LOW Voltage for Control Pin GND VCC x 0.35 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA TERMINATION RESISTORS RTIN Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and Output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB6VQ572M Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C (Note 11) Min Typ fMAX Maximum Input Clock Frequency Characteristic VOUT w 250 mV 5 6 GHz fDATAMAX Maximum Operating Data Rate NRZ, (PRBS23) 6.5 8 Gbps fSEL Maximum Toggle Frequency, SELx 4 10 MHz VOUTPP Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figure 12) fin ≤ 5 GHz 250 400 tPLH, tPHL Propagation Delay to Differential Outputs Measured at Differential Crosspoint 100 175 7 tPD Tempco Differential Propagation Delay Temperature Coefficient 50 tskew Output − Output skew (within device) (Note 13) Device − Device skew (tpdmax − tpdmin) 0 30 15 100 tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) 50 55 FN Phase Noise, fin = 1 GHz tŐFN tJITTER Symbol @ 1 GHz INx/INx to Qx/Qx @ 50 MHz SELx to Qx fIN v 5 GHz 45 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz Max Unit mV 250 20 ps ns Dfs/°C ps % −135 −136 −149 −150 −150 −151 dBc Integrated Phase Jitter (Figure TBD) fin = 1 GHz, 12 kHz − 20 MHz Offset (RMS) 35 fs Random Clock Jitter, RJ (Note 14) Deterministic Jitter, DJ (Note 15) 0.2 fin ≤ 5 GHz fin ≤ 6.5 Gbps (12” FR4) Crosstalk Induced Jitter (Adjacent Channel) (Note 17) VINPP Input Voltage Swing (Differential Configuration) (Note 16) 100 tr,, tf Output Rise/Falltimes @ 1 GHz; (20% − 80%), VIN = 400 mV Qx, Qx 25 45 0.8 ps RMS 10 ps pk−pk 0.7 ps RMS 1200 mV 65 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Output voltage swing is a single−ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from crosspoint of the inputs to the crosspoint of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 16. Input voltage swing is a single−ended measurement operating in differential mode. 17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. http://onsemi.com 6 NB6VQ572M OUTPUT VOLTAGE AMPLITUDE (mV) 600 500 Q AMP (mV) 400 300 200 100 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 fin, CLOCK INPUT FREQUENCY (GHz) 8.0 1.0 8.0 Figure 3. Clock Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical) 600 EYE HEIGHT (mV) 500 400 300 200 100 0 0 2.0 3.0 4.0 5.0 6.0 7.0 fDATA, DATA RATE (Gbps) Figure 4. Inside Eye Height vs. Input Data Rate (Gbps) at Ambient Temperature (typical), FR4 = 12” VTx Q Driver FR4 − 12 Inch Backplane NB6VQ572M INx Q INx DJ1 DJ2 DJ3 Figure 5. Typical NB6VQ572M Equalizer Application and Interconnect with PRBS23 Pattern at 6.5 Gbps http://onsemi.com 7 NB6VQ572M VCC IN VIH Vth VIL INx 50 W IN Vth VTx 50 W Figure 7. Differential Input Driven Single−Ended INx Figure 6. Input Structure VCC VIHmax Vthmax Vth VILmax IN VIH Vth VIL IN IN VIHmin Vthmin VILmin VEE Figure 8. Vth Diagram Figure 9. Differential Inputs Driven Differentially VCC VIHDmax VILDmax VCMmax IN IN IN VID = |VIHD(IN) − VILD(IN)| VCMR VIHD VIHDtyp VILDtyp IN VILD VID = VIHD − VILD VIHDmin VCMmin VILDmin VEE Figure 10. Differential Inputs Driven Differentially Figure 11. VCMR Diagram IN VCC / 2 VINPP = VIH(IN) − VIL(IN) IN VCC / 2 SELx tpd Q VOUTPP = VOH(Q) − VOL(Q) Q tpd Qx Qx tPHL tPLH Figure 13. SELx to Qx Timing Diagram Figure 12. AC Reference Measurement http://onsemi.com 8 NB6VQ572M VCC VCC Zo = 50 W LVPECL Driver VCC VCC NB6VQ572M IN Zo = 50 W NB6VQ572M IN 50 W VT = GND 50 W LVDS Driver 50 W Zo = 50 W VT = OPEN 50 W Zo = 50 W IN CLKx CLKx GND GND GND Figure 14. LVPECL Interface VCC GND Figure 15. LVDS Interface VCC Zo = 50 W IN VCC NB6VQ572M IN VCC Zo = 50 W NB6VQ572M IN 50 W CML Driver 50 W Differential Driver VT = VCC 50 W Zo = 50 W 50 W Zo = 50 W IN GND VT = VREFAC* IN GND GND GND Figure 17. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) Figure 16. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor. NB6VQ572M RECEIVER VCC VCC (Receiver) 50 W 50 W Q 50 W 50 W Q 16 mA GND Figure 18. Typical CML Output Structure and Termination http://onsemi.com 9 NB6VQ572M DEVICE ORDERING INFORMATION Package Shipping† NB6VQ572MMNG QFN−32 (Pb−free) 74 Units / Rail NB6VQ572MMNR4G QFN−32 (Pb−free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NB6VQ572M PACKAGE DIMENSIONS PIN ONE LOCATION 2X ÉÉ ÉÉ 0.15 C 2X QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 SOLDERING FOOTPRINT* EXPOSED PAD 16 K 5.30 32 X 17 8 3.20 E2 1 32 X 0.63 24 32 25 32 X b 0.10 C A B 3.20 e 5.30 0.05 C BOTTOM VIEW 32 X 0.28 28 X 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). 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