NB7L72M D

NB7L72M
2.5V / 3.3V Differential 2 x 2
Crosspoint Switch with
CML Outputs Clock/Data
Buffer/Translator
http://onsemi.com
Multi−Level Inputs w/ Internal Termination
MARKING
DIAGRAM*
Description
The NB7L72M is a high bandwidth, low voltage, fully differential
2 x 2 crosspoint switch with CML outputs. The NB7L72M design is
optimized for low skew and minimal jitter as it produces two identical
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
The differential IN/IN inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels (see
Figure 11). The 16 mA differential CML outputs provide matching
internal 50 W terminations and produce 400 mV output swings when
externally terminated with a 50 W resistor to VCC (see Figure 9).
The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and
is offered in a low profile 3x3 mm 16−pin QFN package. Application
notes, models, and support documentation are available at
www.onsemi.com.
The NB7L72M is a member of the GigaComm™ family of high
performance clock products.
1
NB7L
72M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
+
SEL0
IN0
Features
•
•
•
•
•
•
•
•
•
•
•
•
QFN−16
MN SUFFIX
CASE 485G
Maximum Input Data Rate > 10 Gb/s
Data Dependent Jitter < 10 ps pk−pk
Maximum Input Clock Frequency > 7 GHz
Random Clock Jitter < 0.5 ps RMS, Max
150 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV peak−to−peak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN−16 Package, 3mm x 3mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
Q0
VT0
IN0
Q0
0
1
Q1
IN1
VT1
Q1
+
IN1
SEL1
0
Figure 1. Logic Diagram1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2013 − Rev. 3
1
Publication Order Number:
NB7L72M/D
NB7L72M
VT0
16
IN0
1
IN0
2
SEL0 GND VCC
15
14
Exposed Pad (EP)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
13
12
Q0
11
Q0
SEL0*
SEL1*
Q0
Q1
L
L
IN0
IN0
L
H
IN0
IN1
H
L
IN1
IN0
H
H
IN1
IN1
NB7L72M
IN1
3
10
Q1
IN1
4
9
Q1
*Defaults HIGH when left open
5
VT1
6
7
SEL1 GND
8
VCC
Figure 2. Pin Configuration (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IN0
LVPECL, CML,
LVDS Input
Noninverted Differential Input. (Note 1)
2
IN0
LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
3
IN1
LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
4
IN1
LVPECL, CML,
LVDS Input
Noninverted Differential Input. (Note 1)
5
VT1
−
6
SEL1
LVCMOS Input
7
GND
8
VCC
−
9
Q1
CML Output
Noninverted Differential Output. (Note 1)
10
Q1
CML Output
Inverted Differential Output. (Note 1)
11
Q0
CML Output
Inverted Differential Output. (Note 1)
12
Q0
CML Output
Noninverted Differential Output. (Note 1)
13
VCC
−
Positive Supply Voltage
14
GND
−
Negative Supply Voltage
15
SEL0
LVCMOS Input
16
VT0
−
Internal 50 W Termination Pin for IN0 and IN0
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and is recommended to be electrically and
thermally connected to GND on the PC board.
Internal 50 W Termination Pin for IN1 and IN1.
Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
Negative Supply Voltage
Positive Supply Voltage
Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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2
NB7L72M
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 200 V
QFN−16
Level 1
RPU − Input Pullup Resistor
75 kW
Moisture Sensitivity (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
212
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
4.0
V
VIN
Positive Input Voltage
GND = 0 V
−0.5 to VCC +0.5
V
VINPP
Differential Input Voltage |IN − IN|
1.89
V
IIN
Input Current Through RT (50 W Resistor)
$40
mA
IOUT
Output Current Through RT (50 W Resistor)
$40
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient) (Note 4)
QFN−16
QFN−16
42
35
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case) (Note 4)
QFN−16
4
°C/W
Tsol
Wave Solder
265
°C
0 lfpm
500 lfpm
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L72M
Table 5. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
2.375
3.0
2.5
3.3
2.625
3.6
V
80
135
175
mA
VCC – 40
3260
2460
VCC – 20
3280
2480
VCC
3300
2500
mV
VCC – 650
2650
VCC – 600
1900
VCC – 500
2800
VCC – 500
2000
VCC – 400
2900
VCC – 350
2150
mV
1050
VCC − 100
mV
POWER SUPPLY CURRENT
VCC
Power Supply Voltage
VCC = 2.5 V
VCC = 3.3 V
ICC
Power Supply Current (Inputs and Outputs Open)
CML OUTPUTS
VOH
Output HIGH Voltage (Note 6)
VOL
Output LOW Voltage (Note 6)
VCC = 3.3 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 2.5 V
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 and 7)
Vth
Input Threshold Reference Voltage Range (Note 8)
VIH
Single−Ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth − 100
mV
VISE
Single−Ended Input Voltage (VIH − VIL)
200
2800
mV
DIFFERENTIAL DATA/CLOCK INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) (Note 9)
VIHD
Differential Input HIGH Voltage (INn, INn)
1100
VCC
mV
VILD
Differential Input LOW Voltage (INn, INn)
GND
VCC − 100
mV
VID
Differential Input Voltage (INn, INn) (VIHD − VILD)
100
1200
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
950
VCC − 50
mV
IIH
Input HIGH Current INn, INn (VTIN/VTIN Open)
−150
150
mA
IIL
Input LOW Current INn, INn (VTIN/VTIN Open)
−150
150
mA
CONTROL INPUTS (SEL0, SEL1)
VIH
Input HIGH Voltage for Control Pins
2.0
VCC
mV
VIL
Input LOW Voltage for Control Pins
GND
0.8
mV
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
40
50
60
W
RTOUT
Internal Output Termination Resistor
40
50
60
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs loaded with 50 W to VCC for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
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NB7L72M
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min
fMAX
Maximum Input Clock Frequency
fDATAMAX
Maximum Operating Data Rate (PRBS23)
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
(See Figures 3 and 10, Note 12)
tPLH,
tPHL
Propagation Delay to Differential Outputs,
@ 1GHz, Measured at Differential Cross−point
tPLH TC
Propagation Delay Temperature Coefficient
tSKEW
Output−to−Output Skew (within device) (Note 13)
Device−to−Device Skew (tpdmax – tpdmin)
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 8.5GHz
tjitter
RJ – Output Random Jitter (Note 14)
DJ – Deterministic Jitter (Note 15)
VINPP
Input Voltage Swing (Differential Configuration) (Note 16)
tr,, tf
Output Rise/Fall Times @ 1 GHz (20% − 80%),
Typ
VOUT w 250 mV
VOUT w 200 mV
7.0
8.5
fin ≤ 8.5 GHz
200
400
110
150
Max
10
INn/INn to Qn/Qn
SELn to Qn/Qn
Gbps
mV
180
50
45
fin v 8.5 GHz
v 10 Gbps
25
ps
Dfs/°C
10
20
ps
50
55
%
0.2
0.5
10
ps RMS
ps pk−pk
1200
mV
50
ps
100
Q, Q
Unit
GHz
30
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE
(mV)
500
450
VCC
Q AMP (mV)
400
350
INn
300
50 W
VTn
250
200
50 W
INn
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
fin, Clock Input Frequency (GHz)
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
Figure 4. Input Structure
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5
NB7L72M
IN
VIH
Vth
IN
VIL
IN
IN
Vth
Figure 5. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 6. Differential Inputs
Driven Differentially
VIHmax
VILmax
VIH
Vth
VIL
Vth
VILD
VILmin
GND
Figure 7. Vth Diagram
VCC
Figure 8. Differential Inputs Driven Differentially
VIHDmax
VCMmax
IN
VILDmax
IN
VCMR
IN
GND
VIHD
IN
VIHmin
Vthmin
VCMmin
VID = |VIHD(IN) − VILD(IN)|
IN
VINPP = VIH(IN) − VIL(IN)
IN
VIHDtyp
VID = VIHD − VILD
Q
VILDtyp
VOUTPP = VOH(Q) − VOL(Q)
Q
VIHDmin
tPHL
VILDmin
tPLH
Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
NB7L72M
Receiver
VCC
VCC (Receiver)
50 W
50 W
Q
50 W
50 W
Q
16 mA
GND
Figure 11. Typical CML Output Structure and Termination
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NB7L72M
VCC
50 W
Z = 50 W
DUT
Driver
Device
50 W
Q
D
Receiver
Device
Z = 50 W
Q
D
Figure 12. Typical Termination for CML Output Driver and Device Evaluation
VCC
VCC
VCC
ZO = 50 W
LVPECL
Driver
NB7L72M
NB7L72M
ZO = 50 W
IN
50 W
VT = VCC − 2 V
ZO = 50 W
VCC
LVDS
Driver
50 W
IN
50 W
VT = Open
ZO = 50 W
50 W
IN
GND
IN
Figure 13. LVPECL Interface
VCC
GND
GND
VCC
ZO = 50 W
CML
Driver
VCC
NB7L72M
ZO = 50 W
IN
50 W
Differential
Driver
50 W
IN
GND
VCC
NB7L72M
VT = VCC
ZO = 50 W
GND
Figure 14. LVDS Interface
IN
50 W
VT = VREFAC*
ZO = 50 W
50 W
IN
GND
GND
GND
Figure 16. Capacitor−Coupled
Differential Interface
(VT Connected to External VREFAC)
Figure 15. Standard 50 W Load CML Interface
*VREFAC bypassed to ground with a 0.01 mF capacitor
ORDERING INFORMATION
Package
Shipping†
NB7L72MMNG
QFN−16
(Pb−free)
123 Units / Rail
NB7L72MMNTXG
QFN−16
(Pb−free)
3000 / Tape & Reel
NB7L72MMNHTBG
QFN−16
(Pb−free)
100 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
NB7L72M
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
D
PIN 1
LOCATION
2X
0.10 C
2X
A
B
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉÉ
ÉÉÉ
TOP VIEW
(A3)
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
EXPOSED Cu
0.10 C
L
L
ÉÉ
ÉÉ
ÇÇ
A3
A1
DETAIL B
A
0.05 C
MOLD CMPD
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.18
0.24
0.30
3.00 BSC
1.65
1.75
1.85
3.00 BSC
1.65
1.75
1.85
0.50 BSC
0.18 TYP
0.30
0.40
0.50
0.00
0.08
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C A B
16X
L
DETAIL A
PACKAGE
OUTLINE
D2
8
4
16X
16X
0.58
1
9
2X
E2
K
2X
1.84 3.30
1
16X
16
e
e/2
BOTTOM VIEW
16X
0.30
b
0.50
PITCH
0.10 C A B
0.05 C
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NB7L72M/D