INTERSIL ACS125K

ACS125MS
Radiation Hardened
Quad Buffer, Three-State
January 1996
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96705 and Intersil’s QM Plan
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
-10
Errors/Bit/Day
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
OE1 1
14 VCC
A1 2
13 OE4
Y1 3
12 A4
OE2 4
11 Y4
A2 5
10 OE3
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
Y2 6
9 A3
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
GND 7
8 Y3
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)
Description
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
OE1
1
14
VCC
A1
2
13
OE4
Y1
3
12
A4
OE2
4
11
Y4
A2
5
10
OE3
Y2
6
9
A3
GND
7
8
Y3
The Intersil ACS125MS is a Radiation Hardened Quad Buffer with
Three-State outputs. Each output has it’s own enable input, which when
“HIGH” puts the output in a high impedance state.
The ACS125MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS125MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9670501VCC
-55oC to +125oC
MIL-PRF-38535 Class V
14 Lead SBDIP
5962F9670501VXC
-55oC
MIL-PRF-38535 Class V
14 Lead Ceramic Flatpack
to
+125oC
ACS125D/Sample
25oC
Sample
14 Lead SBDIP
ACS125K/Sample
25oC
Sample
14 Lead Ceramic Flatpack
ACS125HMSR
25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number
File Number
518817
3565.1
ACS125MS
Functional Diagram
P
Yn
An
n
OEn
TRUTH TABLE
INPUTS
OUTPUT
An
OEn
Yn
L
L
L
H
L
H
X
H
Z
NOTE: L = Low, H = High, X = Don’t Care, Z = High Impedance
Spec Number
2
518817
ACS125MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2.24mm x 2.24mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105 A/cm2
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
Metallization Mask Layout
ACS125MS
A1
(2)
OE1
(1)
VCC
(14)
OE4
(13)
Y1 (3)
(12) A4
OE2 (4)
(11) Y4
NC
NC
A2 (5)
(10) OE3
(6)
Y2
(7)
GND
(8)
Y3
(9)
A3
Spec Number
3
518817
ACS125MS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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FAX: (886) 2 2715 3029
Spec Number
4