NCP1254 D

NCP1254
Product Preview
Current-Mode PWM
Controller for Off-line
Power Supplies featuring
Peak Power Excursion
The NCP1254 is a highly integrated PWM controller capable of
delivering a rugged and high performance offline power supply in a
TSOP−6 package. With a supply range up to 35 V, the controller hosts
a jittered 65−kHz switching circuitry operated in peak current mode
control. When the power on the secondary side starts to decrease, the
controller automatically folds back its switching frequency down to a
minimum level of 26 kHz. As the power further goes down, the part
enters skip cycle while freezing the peak current setpoint.
To help building rugged converters, the controller features several
key protective features: a non−dissipative Over Power Protection for a
constant maximum output current regardless of the input voltage, two
latched over voltage protection inputs − either through a dedicated pin
or via the Vcc input and a dual−level auto−recovery/latched overload/
short−circuit timer.
The controller architecture is designed to authorize a transient peak
power excursion when the current setpoint hits the limit. At this point,
the switching frequency is increased from 65 kHz to 130 kHz until the
peak event disappears. The timer duration is then modulated as the
converter crosses a peak power excursion mode (long) or undergoes a
short circuit (short).
1
TSOP−6
CASE 318G
STYLE 13
MARKING DIAGRAM
54xAYWG
G
1
54
x
A
Y
W
G
= Specific Device Code
= A or B
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
• 65−kHz Fixed−frequency Current−mode Control Operation with
130−kHz Excursion
• Internal and Adjustable Over Power Protection (OPP) Circuit
• Frequency Foldback down to 26 kHz and Skip−cycle in Light Load
•
•
•
•
•
•
•
•
•
•
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Conditions
Adjustable Slope Compensation
Internally Fixed 4−ms Soft−start
Fixed Timer−based Auto−recovery Overload/Short−circuit Protection
100% to 25% Timer Reduction from Overload to Short−circuit Fault
Double Vcc Hiccup for a Reduced Average Power in Fault Mode
Frequency Jittering in Normal and Frequency Foldback Modes
Latched OVP Input for Improved Robustness and Latched OVP on Vcc
Up to 35−V Vcc Maximum Rating
Extremely Low No−load Standby Power
This is a Pb−Free Device
PIN CONNECTIONS
GND
1
6
DRV
FB
2
5
VCC
OPP/Latch
3
4
CS
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Typical Applications
• Converters requiring peak−power capability such as printers power
supplies, ac−dc adapters for game stations.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. P1
1
Publication Order Number:
NCP1254/D
NCP1254
Vbulk
Vout
.
.
OVP
OPP
.
NCP1254
1
6
2
5
3
4
ramp
comp.
Figure 1. Typical Application Schematic
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
GND
−
2
FB
Feedback pin
3
OPP/OVP
Adjust the Over Power Protection
Latches off the part
4
CS
Current sense + ramp compensation
5
Vcc
Supplies the controller – protects the IC
6
DRV
Driver output
The controller ground.
Hooking an optocoupler collector to this pin will allow regulation via peak current mode control or frequency modulation in
high−power conditions.
A resistive divider from the auxiliary winding to this pin sets the
OPP compensation level. When brought above 3 V, the part is
fully latched off.
This pin monitors the primary peak current but also offers a
means to introduce slope compensation.
This pin is connected to an external auxiliary voltage. An OVP
comparator monitors this pin and offers a means to latch the
converter in fault conditions.
The driver’s output to an external MOSFET gate.
Table 2. OPTIONS AND ORDERING INFORMATION
Controller
Frequency
OCP Latched
OCP Auto−recovery
NCP1254ASN65T1G
65 kHz
Yes
No
NCP1254BSN65T1G
65 kHz
No
Yes
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2
NCP1254
Vcc and logic
management
double hiccup
OPP
600−ns time
constant
Vdd
Up counter
RST
4
Vlatch
OVP
gone?
100% to
25% change
power
on reset
VOVP
Vcc
Vref
option
latch/AR
Q
Q
IpFlag,
PON reset
Rlimit
1−ms
blanking
R
Vcc
SC
20 ms
S
UVLO
Vcc
Power on
reset
65 kHz
clock
Jitter mod.
Clamp
S
Q
Q
R
Frequency
increase to
130 kHz
Vskip
VFswp
Frequency
foldback
Drv
Vfold
Rramp
vdd
SC
RFB
/4
VSC
4 ms
SS
The soft−start is
activated during:
Ip flag
− the startup sequence
− the auto−recovery burst mode
VFB < 1 V ? setpoint = 250 mV
FB
CS
LEB
VOPP
250 mV
peak current
freeze
Vlimit + VOPP
+
GND
Vlimit
Figure 2. Internal Circuit Architecture
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3
NCP1254
Table 3. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
Vcc
Power Supply voltage, Vcc pin, continuous voltage
−0.3 to 35
V
Maximum voltage on low−power pins CS, FB and OPP
−0.3 to 10
V
Maximum voltage on drive pin
−0.3 to Vcc+0.3
V
IOPP
Maximum injected current into the OPP pin
−2
mA
ISCR
Maximum continuous current into the Vcc pin while in latched mode
3
mA
RθJ−A
Thermal Resistance Junction−to−Air
360
°C/W
TJ,max
Maximum Junction Temperature
150
°C
Iscr
Maximum continuous current into Vcc pin when latched
3
mA
Storage Temperature Range
−60 to +150
°C
VDRV
HBM
Human Body Model ESD Capability (All pins except HV) per JEDEC JESD22−A114F
2
kV
MM
Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C
200
V
CDM
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
500
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted)
Rating
Pin
Min
Typ
Max
Unit
VCCON
VCC increasing level at which driving pulses are authorized
5
15.8
18
20
V
VCC(min)
VCC decreasing level at which driving pulses are stopped
5
8
8.8
9.4
V
VCCHYST
Hysteresis VccON−Vcc(min)
5
6
−
−
V
VZENER
Clamped Vcc when latched off @ ICC = 500 mA
5
−
7
−
V
ICC1
Start−up current
5
−
−
15
mA
ICC2
Internal IC consumption with VFB = 3.2 V, FSW = 65 kHz and CL = 0
5
−
1.4
2.2
mA
ICC3
Internal IC consumption with VFB = 3.2 V, FSW = 65 kHz and CL = 1 nF
5
−
2.1
3.0
mA
ICC4
Internal IC consumption with VFB = 4.5 V, FSW = 130 kHz and CL = 0
5
−
1.7
2.5
mA
ICC5
Internal IC consumption with VFB = 4.5 V, FSW = 130 kHz and CL = 1 nF
5
−
3.1
4.0
mA
ICCstby
Internal IC consumption while in skip mode
(Vcc = 12 V, driving a typical 6−A/600−V MOSFET)
ICCLATCH
Current flowing into VCC pin that keeps the controller latched:
Tj = −40°C to 125°C
5
Rlim
SCR current−limit series resistor
5
Tr
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
6
−
40
−
ns
Tf
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
6
−
30
−
ns
ROH
Source resistance
6
−
13
−
W
ROL
Sink resistance
6
−
6
−
W
Isource
Peak source current, VGS = 0 V (Note 2)
6
300
mA
Isink
Peak sink current, VGS = 12 V (Note 2)
6
500
mA
Symbol
SUPPLY SECTION
750
mA
mA
40
4
kW
DRIVE OUTPUT
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 3 below −300 mV.
4. A 1−MW resistor is connected from pin 4 to the ground for the measurement.
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4
NCP1254
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
VDRVlow
DRV pin level at VCC close to VCC(min)
with a 33−kW resistor to GND
6
8
−
−
V
VDRVhigh
DRV pin level at VCC = VOVP − 0.2 V – DRV unloaded
6
10
12
14
V
DRIVE OUTPUT
CURRENT COMPARATOR
IIB
Input Bias Current @ 0.8 V input level on pin 4
4
0.02
VLimit1
Maximum internal current setpoint – Tj = 25°C – pin 3 grounded
4
0.744
0.8
0.856
V
VLimit2
Maximum internal current setpoint –
Tj from −40° to 125°C – pin 3 grounded
4
0.72
0.8
0.88
V
VfoldI
Default internal voltage set point for frequency foldback
trip point ≈59% of Vlimit
4
475
mV
VfreezeI
Internal peak current setpoint freeze (≈31% of Vlimit)
4
250
mV
TDEL
Propagation delay from current detection to gate off−state
4
100
TLEB
Leading Edge Blanking Duration
4
300
ns
TSS
Internal soft−start duration activated upon startup, auto−recovery
−
4
ms
IOPPo
Setpoint decrease for pin 3 biased to –250 mV (Note 3)
4
31.3
%
IOOPv
Voltage setpoint for pin 3 biased to −250 mV (Note 3), Tj = 25°C
4
0.51
0.55
0.6
V
IOOPv
Voltage setpoint for pin 3 biased to −250 mV (Note 3),
Tj from −40° to 125°C
4
0.5
0.55
0.62
V
IOPPs
Setpoint decrease for pin 3 grounded
4
fOSC,nom
Oscillation frequency, VFB < VFbtrans, pin 3 grounded
−
VFBtrans
Feedback voltage above which Fsw increases
−
fOSC,max
Maximum oscillation frequency for VFB above VFBmax
−
120
130
140
kHz
VFBmax
Feedback voltage above which Fsw is constant
−
3.8
4.1
4.2
V
Dmax
Maximum duty ratio
−
76
80
84
%
fjitter
Frequency jittering in percentage of fOSC
−
±5
%
fswing
Swing frequency over the whole frequency range
−
240
Hz
Rup
Internal pull−up resistor
2
15
kW
Req
Equivalent ac resistor from FB to gnd
2
13
kW
Iratio
Pin 2 to current setpoint division ratio
−
4
VfreezeF
Feedback voltage below which the peak current is frozen
2
1
V
Frequency foldback level on the feedback pin –
≈59% of maximum peak current
−
1.9
V
−
mA
150
0
ns
%
INTERNAL OSCILLATOR
61
65
71
3.2
kHz
V
FEEDBACK SECTION
FREQUENCY FOLDBACK
VfoldF
Ftrans
Transition frequency below which skip−cycle occurs
Vfold,end
End of frequency foldback feedback level, Fsw = Fmin
Vskip
Skip−cycle level voltage on the feedback pin
Skip
hysteresis
Hysteresis on the skip comparator (Note 2)
22
26
30
V
−
400
mV
−
30
mV
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 3 below −300 mV.
4. A 1−MW resistor is connected from pin 4 to the ground for the measurement.
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5
kHz
1.5
NCP1254
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
Vramp
Internal ramp level @ 25°C (Note 4)
4
2.5
V
Rramp
Internal ramp resistance to CS pin
4
20
kW
Vlatch
Latching level input
3
Tlatch−blank
Blanking time after drive turn off
3
Tlatch−count
Number of clock cycles before latch confirmation
−
4
Tlatch−del
OVP detection time constant
3
600
Timer1
Default − Overload Fault timer duration
−
160
208
270
ms
Timer2
Default − Fault timer duration when VFB > 4.1 V is Timer1/4
−
40
52
68
ms
VSC
Feedback voltage beyond which a short−circuit is considered
2
3.9
4.1
4.3
V
VOVL
Feedback voltage beyond which an over load is considered –
OPP pin is grounded
2
VOVP(regular)
Latched Over voltage protection on the Vcc rail
5
30.7
32.3
34
V
VOVP(copack)
Latched Over voltage protection on the Vcc rail
5
26
27.5
29
V
TOVP−del
Delay before OVP on Vcc confirmation
5
INTERNAL SLOPE COMPENSATION
PROTECTIONS
2.7
3
3.3
1
ms
ns
3.2
V
20
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 3 below −300 mV.
4. A 1−MW resistor is connected from pin 4 to the ground for the measurement.
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6
V
ms
NCP1254
900
5.0
850
4.5
4.0
800
ICC@30V (mA)
ICCstby (mA)
TYPICAL CHARACTERISTICS
750
700
2.0
−25
0
25
50
75
100
1.5
−50
125
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
Figure 3.
Figure 4.
40
14
35
12
30
125
10
25
20
8
6
15
4
10
5
−50
−25
JUNCTION TEMPERATURE (°C)
ROL (W)
ICC(Latch1) (mA)
3.0
2.5
650
600
−50
3.5
−25
0
25
50
75
100
2
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 5.
Figure 6.
125
14.0
10
13.5
13.0
VDRVH (V)
VDRVL (V)
9.5
9.0
8.5
12.5
12.0
11.5
11.0
10.5
8.0
−50
−25
0
25
50
75
100
10.0
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 7.
Figure 8.
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7
125
NCP1254
TYPICAL CHARACTERISTICS
0.88
0.54
0.86
0.52
0.50
0.82
Vfold(CS) (V)
VILIM1 (V)
0.84
0.80
0.78
0.46
0.44
0.76
0.42
0.74
0.72
−50
0.48
−25
0
25
50
75
100
0.40
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 9.
Figure 10.
125
400
0.30
380
360
340
tLEB (nS)
0.26
0.24
320
300
280
260
0.22
240
0.20
−50
220
200
−50
−25
0
25
50
75
100
125
25
50
75
100
Figure 11.
Figure 12.
0.62
34.98
0.60
32.98
0.58
30.98
0.54
26.98
0.52
0
25
50
75
100
0.50
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 13.
Figure 14.
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8
125
0.56
28.98
−25
0
JUNCTION TEMPERATURE (°C)
36.98
24.98
−50
−25
JUNCTION TEMPERATURE (°C)
IOPPv (V)
IOPPo (%)
VFreeze(CS) (V)
0.28
125
NCP1254
TYPICAL CHARACTERISTICS
70.308
136.829
131.829
FOSC(max) (kHz)
fOSC(nom) (kHz)
68.308
66.308
126.829
64.308
121.829
62.308
60.308
−50
−25
0
25
50
75
100
116.829
−50
125
75
100
Figure 16.
83
14.5
125
14.0
13.5
81
Rupper (kW)
Dmax (%)
50
Figure 15.
82
80
79
13.0
12.5
12.0
11.5
78
11.0
77
−25
0
25
50
75
100
10.5
10.0
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 17.
Figure 18.
4.3
1.15
4.2
1.10
VFREEZE(FB) (V)
IRATIO (V/V)
25
JUNCTION TEMPERATURE (°C)
15.0
4.1
4.0
3.9
3.8
3.7
−50
0
JUNCTION TEMPERATURE (°C)
84
76
−50
−25
125
1.05
1.00
0.95
0.90
−25
0
25
50
75
100
0.85
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 19.
Figure 20.
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9
125
NCP1254
TYPICAL CHARACTERISTICS
30
1.65
29
1.60
Vfold_End(FB) (V)
Ftrans (kHz)
28
27
26
25
1.55
1.50
1.45
24
1.40
23
22
−50
−25
0
25
50
75
100
1.35
−50
125
75
100
Figure 22.
28
26
125
24
Rramp (kW)
420
Vskip (mV)
50
Figure 21.
430
410
400
390
380
22
20
18
16
370
14
−25
0
25
50
75
100
12
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 23.
Figure 24.
3.3
650
3.2
600
3.1
550
Timer1 (mS)
Vlatch (V)
25
JUNCTION TEMPERATURE (°C)
440
3.0
2.9
2.8
2.7
−50
0
JUNCTION TEMPERATURE (°C)
450
360
350
−50
−25
125
500
450
400
−25
0
25
50
75
100
350
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 25.
Figure 26.
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10
125
NCP1254
TYPICAL CHARACTERISTICS
158
33.7
148
33.2
32.7
VOVP (V)
Timer2 (ms)
138
128
118
31.7
108
31.2
98
88
−50
32.2
−25
0
25
50
75
100
30.7
−50
125
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 27.
Figure 28.
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125
NCP1254
APPLICATION INFORMATION
Introduction
The NCP1254 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count and cost effectiveness are
the key parameters, particularly in low−cost ac−dc adapters,
open−frame power supplies etc. The NCP1254 brings all the
necessary components normally needed in today modern
power supply designs, bringing several enhancements such
as a non−dissipative OPP or peak power excursion for loads
exhibiting variations over time.
• Current−mode operation with internal slope
compensation: implementing peak current mode
control at a fixed 65−kHz frequency, the NCP1254
offers an internal slope compensation signal that can
easily by summed up to the sensed current. Sub
harmonic oscillations can thus be compensated via the
inclusion of a simple resistor in series with the
current−sense information.
• Frequency excursion: when the power demand forces
the peak current setpoint to reach the internal limit
(0.8 V/Rsense typically), the frequency is authorized to
increase to let the converter deliver more power. The
frequency excursion stops when 130 kHz are reached at
a level of 4 V. This excursion can only be temporary
and its duration is set by the overload timer.
• Internal OPP: by routing a portion of the negative
voltage present during the on−time on the auxiliary
winding to the dedicated OPP pin (pin 3), the user has a
simple and non−dissipative means to alter the
maximum peak current setpoint as the bulk voltage
increases. If the pin is grounded, no OPP compensation
occurs. If the pin receives a negative voltage down to
–250 mV, then a peak current reduction down to 31.3%
typical can be achieved. For an improved performance,
the maximum voltage excursion on the sense resistor is
limited to 0.8 V.
• Low startup current: reaching a low no−load standby
power always represents a difficult exercise when the
controller draws a significant amount of current during
start−up. Thanks to its proprietary architecture, the
NCP1254 is guaranteed to draw less than 15 mA
maximum, easing the design of low standby power
adapters.
• EMI jittering: an internal low−frequency modulation
signal varies the pace at which the oscillator frequency
is modulated. This helps spreading out energy in
conducted noise analysis. To improve the EMI
signature at low power levels, the jittering will not be
disabled in frequency foldback mode (light load
conditions).
• Frequency foldback capability: a continuous flow of
pulses is not compatible with no−load/light−load
•
•
•
•
standby power requirements. To excel in this domain,
the controller observes the feedback pin and when it
reaches a level of 1.9 V, the oscillator then starts to
reduce its switching frequency as the feedback level
continues to decrease. When the feedback level reaches
1.5−V, the frequency hits its lower stop at 26 kHz.
When the feedback pin goes further down and reaches
1 V, the peak current setpoint is internally frozen.
Below this point, if the power continues to drop, the
controller enters classical skip−cycle mode.
Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start−up. In this
controller, the soft−start is internally fixed to 4 ms.
Soft−start is activated when a new startup sequence
occurs or during an auto−recovery hiccup.
OVP input: the NCP1254 includes a latch input (pin 3)
that can be used to sense an overvoltage condition on
the adapter. If this pin is brought higher than the
internal reference voltage Vlatch, then the circuit
permanently latches off. The Vcc pin is pulled down to
a fixed level, keeping the controller latched. The latch
reset occurs when the user disconnects the adapter from
the mains and lets the Vcc falls below the Vcc reset.
Vcc OVP: a latched OVP protects the circuit against
Vcc runaways. The fault must be present at least 20 ms
to be validated. When it happens, all pulses are stopped
and the Vcc is permanently brought to around 7 V via
an internal Zener−based SCR. Reset occurs when the
latch current goes below ICClatch.
Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (the aux winding level
does not properly collapse in presence of an output
short). Here, every time the internal 0.8−V maximum
peak current limit is activated (or less when OPP is
used), an error flag is asserted and a time period starts,
thanks to the internal timer. The controller can
distinguish between two faulty situations:
♦ There is an extra demand of power, still within the
power supply capabilities. In that case, the feedback
level is in the vicinity of 3.2−4 V (max peak current
is 0.8 V, no OPP). The timer duration is then 100%
of its internally programmed value. If the fault
disappears, e.g. the peak current no longer hits the
limit, the timer is reset.
♦ The output is frankly shorted. The feedback level is
thus pushed to its upper stop (4.5 V) and the timer is
reduced to 25% of its normal value. When it elapses,
protection occurs.
♦ In either mode, when the fault is validated, all pulses
are stopped and the controller enters an
auto−recovery burst mode, with a soft−start
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12
NCP1254
♦
Start−up Sequence
sequence at the beginning of each cycle. Please note
the presence of a divider by two which ignores one
hiccup cycle over two (double hiccup type of burst).
As soon as the fault disappears, the SMPS resumes
operation. Please note that some version offers an
auto−recovery mode as we just described, some do
not and latch off in case of a short circuit.
The NCP1254 start−up voltage is made purposely high to
permit large energy storage in a small Vcc capacitor value.
This helps to operate with a small start−up current which,
together with a small Vcc capacitor, will not hamper the
start−up time. To further reduce the standby power, the
start−up current of the controller is extremely low, below
15 mA. The start−up resistor can therefore be connected to
the bulk capacitor or directly to the mains input voltage if
you wish to save a few more mW.
R3
100 k
R2
100 k
D2
1N4007
D1
1N4007
R1
200 k
D6
1N4148
Cbulk
22 mF
input
mains
D5
1N4935
Vcc
D4
1N4007
D3
1N4007
C1
4.7 mF
C3
47 mF
aux.
Figure 29. The startup resistor can be connected to the input mains for further power dissipation reduction.
V ac,rmsǸ2
* VCC on
p
I CVcc,min +
R start−up
The first step starts with the calculation of the needed Vcc
capacitor which will supply the controller until the auxiliary
winding takes over. Experience shows that this time t1 can
be between 5 and 20 ms. Considering that we need at least
an energy reservoir for a t1 time of 10 ms, the Vcc capacitor
must be larger than:
To make sure this current is always greater than 49 mA, the
maximum value for Rstart−up can be extracted:
(eq. 4)
V ac,rmsǸ2
85 1.414 −18
− VCC on
p
p
R start−up v
v
v 413 kW
I CVcc,min
49 m
(eq. 1)
I cct 1
3 m 10 m
CV cc w
w
w 3.3 mF
9
VCC on * VCC min
Let us select a 4.7−mF capacitor at first and experiments
in the laboratory will let us know if we were too optimistic
for t1. The Vcc capacitor being known, we can now evaluate
the charging current we need to bring the Vcc voltage from
0 to the VCCon of the IC, 18 V typical. This current has to
be selected to ensure a start−up at the lowest mains (85 V
rms) to be less than 3 s (2.5 s for design margin):
I charge w
(eq. 3)
This calculation is purely theoretical, considering a
constant charging current. In reality, the take over time can
be shorter (or longer!) and it can lead to a reduction of the
Vcc capacitor. This brings a decrease in the charging current
and an increase of the start−up resistor, for the benefit of
standby power. Laboratory experiments on the prototype are
thus mandatory to fine tune the converter. If we chose the
400−kW resistor as suggested by Equation 4, the dissipated
power at high line amounts to:
VCC onC Vcc
18 4.7 m
w
w 34 mA (eq. 2)
2.5
2.5
If we account for the 15 mA that will flow inside the
controller, then the total charging current delivered by the
start−up resistor must be 49 mA. If we connect the start−up
network to the mains (half−wave connection then), we know
that the average current flowing into this start−up resistor will
be the smallest when Vcc reaches the VCCon of the controller:
P Rstartup,max +
V ac,peak 2
4R start−up
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13
+
ǒ230
4
Ǹ2Ǔ
2
105 k
+
+ 66 mW
1.6 Meg
400 k
(eq. 5)
NCP1254
Now that the first Vcc capacitor has been selected, we must
ensure that the self−supply does not disappear when in
no−load conditions. In this mode, the skip−cycle can be so
deep that refreshing pulses are likely to be widely spaced,
inducing a large ripple on the Vcc capacitor. If this ripple is
too large, chances exist to touch the VCCmin and reset the
controller into a new start−up sequence. A solution is to
grow this capacitor but it will obviously be detrimental to the
start−up time. The option offered in Figure 29 elegantly
solves this potential issue by adding an extra capacitor on the
auxiliary winding. However, this component is separated
from the Vcc pin via a simple diode. You therefore have the
ability to grow this capacitor as you need to ensure the
self−supply of the controller without affecting the start−up
time and standby power.
1 Meg
N
L1
1 Meg
Vcc
Figure 30. The full−wave connection ensures latch
current continuity as well as X2−discharge path.
In this case, the current is no longer made of 5−ms “holes”
and the part can be maintained at a low input voltage.
Experiments show that these 2−MW resistor help to maintain
the latch down to less than 50 V rms, giving an excellent
design margin. Standby power with this approach was also
improved compared to Figure 29 solution. Please note that
these resistors also ensure the discharge of the X2−capacitor
up to a 0.47−mF type.
The de−latch of the SCR occurs when the injected current
in the Vcc pin falls below the minimum stated in the
data−sheet (32 mA at room temp).
Triggering the SCR
The latched−state of the NCP1254 is maintained via an
internal thyristor (SCR). When the voltage on pin 3 exceeds
the latch voltage for four consecutive clock cycles, the SCR
is fired and immediately stops the output pulses. The same
SCR is fired when an OVP is sensed on the Vcc pin. When
this happens, all pulses are stopped and Vcc is discharged to
a fix level of 7 V typically: the circuit is latched and the
converter no longer delivers pulses. To maintain the
latched−state, a permanent current must be injected in the
part. If too low of a current, the part de−latches and the
converter resumes operation. This current is characterized to
32 mA as a minimum but we recommend to include a design
margin and select a value around 60 mA. The test is to latch
the part and reduce the input voltage until it de−latches. If
you de−latch at Vin = 70 V rms for a minimum voltage of
85 V rms, you are fine. If it precociously recovers, you will
have to increase the start−up current, unfortunately to the
detriment of standby power.
The most sensitive configuration is actually that of the
half−wave connection proposed in Figure 29. As the current
disappears 5 ms for a 10−ms period (50−Hz input source),
the latch can potentially open at low line. If you really reduce
the start−up current for a low standby power design, you
must ensure enough current in the SCR in case of a faulty
event. An alternate connection to the above is shown below
(Figure 30):
Internal Over Power Protection
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
swing present on the auxiliary diode anode. During the
turn−on time, this point dips to −NVin, N being the turns ratio
between the primary winding and the auxiliary winding. The
negative plateau observed on Figure 31 will have an
amplitude depending on the input voltage. The idea
implemented in this chip is to sum a portion of this negative
swing with the 0.8−V internal reference level. For instance,
if the voltage swings down to −150 mV during the on−time,
then the internal peak current set point will be fixed to
0.8−0.150 = 650 mV. The adopted principle appears in
Figure 32 and shows how the final peak current set point is
constructed.
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14
NCP1254
40.0
off−time
N1 (Vout + Vf)
Plot1
v(24) in volts
20.0
0
−N2Vbulk
−20.0
on−time
−40.0
464u
472u
480u
time in seconds
488u
496u
Figure 31. The signal obtained on the auxiliary
winding swings negative during the on−time.
Let’s assume we need to reduce the peak current from 2.5 A at low line, to 2 A at high line. This corresponds to a 20%
reduction or a set point voltage of 640 mV. To reach this level, then the negative voltage developed on the OPP pin must reach:
V OPP + 640 m * 800 m + −160 mV
(eq. 6)
RoppU
swings to:
Vout during toff
−NVin during ton
Vcc
aux
This point will
be adjusted to
reduce the ref
at hi line to the
desired level.
from FB
OPP
K1
SUM2
ref
K2
CS
+
Iopp
reset
−
Vdd
0.8 V
±5%
RoppL
ref = 0.8 V + VOPP
(VOPP is negative)
Figure 32. The OPP circuitry affects the maximum peak current set point by
summing a negative voltage to the internal voltage reference.
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NCP1254
Let us assume that we have the following converter
characteristics:
Vout = 19 V
Vin = 85 to 265 V rms
N1 = Np:Ns = 1:0.25
N2 = Np:Naux = 1:0.18
Given the turns ratio between the primary and the
auxiliary windings, the on−time voltage at high line
(265 Vac) on the auxiliary winding swings down to:
V aux + −N 2V in,max + −0.18
375 + −67.5 V
To obtain a level as imposed by Equation 6, we need to
install a divider featuring the following ratio:
Div + 0.16 [ 2.4 m
67.5
(eq. 8)
If we arbitrarily fix the pull−down resistor ROPPL to 1 kW,
then the upper resistor can be obtained by:
R OPPU + 67.5 * 0.16 [ 421 kW
0.16ń1 k
(eq. 9)
If we now plot the peak current set point obtained by
implementing the recommended resistor values, we obtain
the following curve (Figure 33):
(eq. 7)
Peak current setpoint
100%
80%
375
Vbulk
Figure 33. The peak current regularly reduces down to 20% at 375 V dc.
Frequency Foldback
The OPP pin is surrounded by Zener diodes stacked to
protect the pin against ESD pulses. These diodes accept
some peak current in the avalanche mode and are designed
to sustain a certain amount of energy. On the other side,
negative injection into these diodes (or forward bias) can
cause substrate injection which can lead to an erratic circuit
behavior. To avoid this problem, the pin is internal clamped
slightly below –300 mV which means that if more current is
injected before reaching the ESD forward drop, then the
maximum peak reduction is kept to 40%. If the voltage
finally forward biases the internal zener diode, then care
must be taken to avoid injecting a current beyond –2 mA.
Given the value of ROPPU , there is no risk in the present
example. Finally, please note that another comparator
internally fixes the maximum peak current set point to 0.8 V
even if the OPP pin is adversely biased above 0 V.
The reduction of no−load standby power associated with
the need for improving the efficiency, requires a change in
the traditional fixed−frequency type of operation. This
controller implements a switching frequency foldback when
the feedback voltage passes below a certain level, Vfold, set
around 1.9 V. Below this point, the frequency no longer
changes and the feedback level still controls the peak current
setpoint. When the feedback voltage reaches 1 V, the peak
current freezes to (250 mV or »31% of the maximum 0.8−V
setpoint). If the power continues to decrease, the part enters
skip cycle at a moderate peak current for the best noise−free
performance in no−load conditions. Figure 34 depicts the
adopted scheme for the part.
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NCP1254
Frequency
Peak current setpoint
Fsw
FB
VCS
max
130 kHz
26 kHz
min
max
0.8 V
65 kHz
≈0.47 V
skip
1.9 V
4V
400 mV
1.5 V
3.2 V
Vfold,end Vfold
≈0.25 V
VFB
min
Vskip Vfreeze
0.4 V 1 V
Vfold 3.2 V
1.9 V
VFB
Figure 34. By observing the voltage on the feedback pin, the controller reduces its
switching frequency for an improved performance at light load.
Auto−Recovery Short−Circuit Protection
up again thanks to the resistive starting network. When Vcc
reaches VCCON, the controller purposely ignores the
re−start and waits for another Vcc cycle: this is the so−called
double hiccup. By lowering the duty ratio in fault condition,
it naturally reduces the average input power and the rms
current in the output cable. Illustration of such principle
appears in Figure 35. Please note that soft−start is activated
upon re−start attempt.
In case of output short−circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. If the flag is
asserted longer than its internal value, the driving pulses are
stopped and Vcc falls down as the auxiliary pulses are
missing. When it crosses VCC(min), the controller
consumption is down to a few mA and the Vcc slowly builds
VCC(t)
18 V
8.8 V
VDRV(t)
No pulse
area
Figure 35. An auto−recovery hiccup mode is entered in case a faulty
event is acknowledged by the controller.
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NCP1254
Slope Compensation
during Continuous Conduction Mode (CCM) with a duty
ratio greater than 50%. To lower the current loop gain, one
usually mixes between 50 and 100% of the inductor
downslope with the current−sense signal. Figure 36 depicts
how internally the ramp is generated. Please note that the
ramp signal will be disconnected from the CS pin, during the
off−time.
The NCP1254 includes an internal ramp compensation
signal. This is the buffered oscillator clock delivered during
the on time only. Its amplitude is around 2.5 V at the
maximum authorized duty ratio. Ramp compensation is a
known means used to cure sub harmonic oscillations in
CCM−operated current−mode converters. These oscillations
take place at half the switching frequency and occur only
2.5 V
0V
ON
latch
reset
20 k
+
Rcomp
L.E.B
CS
−
Rsense
from FB setpoint
Figure 36. Inserting a resistor in series with the current sense information brings slope
compensation and stabilizes the converter in CCM operation.
In the NCP1254 controller, the oscillator ramp exhibits a
2.5−V swing reached at a 80% duty ratio. If the clock
operates at a 65−kHz frequency, then the available oscillator
slope corresponds to:
S ramp +
V ramp,peak
D maxT sw
divratio +
R comp + R rampdivratio + 20 k
In our flyback design, let’s assume that our primary
inductance Lp is 770 mH, and the SMPS delivers 19 V with
a Np :Ns turns ratio of 1:0.25. The off−time primary current
slope Sp is thus given by:
Sp +
s
Lp
Latching Off the Controller
(eq. 11)
+
(19 ) 0.8)
770 m
4
The OPP pin not only allows a reduction of the peak
current set point in relationship to the line voltage, it also
offers a means to permanently latch−off the part. When the
part is latched−off, the Vcc pin is internally pulled down to
around 7 V and the part stays in this state until the user cycles
the Vcc down and up again, e.g. by un−plugging the
converter from the mains outlet. The latch detection is made
by observing the OPP pin by a comparator featuring a 3−V
reference voltage. However, for noise reasons and in
particular to avoid the leakage inductance contribution at
turn off, a 1−ms blanking delay is introduced before the
output of the OVP comparator is checked. Then, the OVP
+ 103 kAńs
Given a sense resistor of 330 mW, the above current ramp
turns into a voltage ramp of the following amplitude:
(eq. 12)
S sense + S pR sense + 103k
0.082 [ 1.6 kW (eq. 14)
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small 100−pF capacitor, from the current sense pin
to the controller ground for improved noise immunity.
Please make sure both components are located very close to
the controller.
2.5
+ 208 kVńs or 208 mVńms
0.8 15 m
ǒVout ) VfǓ NNp
(eq. 13)
The series compensation resistor value is thus:
(eq. 10)
+
17 m
+ 0.082
208 m
0.33 + 34kVńs or 34mVńms
If we select 50% of the downslope as the required amount
of ramp compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
208 mV/ms, the divider ratio (divratio) between Rcomp and
the internal 20 kW resistor is:
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NCP1254
The first and easiest solution is the additional resistive
divider on top of the OPP one. This solution is simple and
inexpensive but requires the insertion of a diode to prevent
disturbing the OPP divider during the on−time.
comparator output is validated only if its high−state duration
lasts a minimum of 600 ns. Below this value, the event is
ignored. Then, a counter ensures that 4 successive OVP
events have occurred before actually latching the part. There
are several possible implementations, depending on the
needed precision and the parameters you want to control.
R3
D2
5k
1N4148
11
RoppU
421 k
Vcc
OPP
C1
100 p
10
4
ROPPL
1k
5
9
8
aux.
winding
1
OVP
Vlatch
OPP
Figure 37. A simple resistive divider brings the OPP pin above 3 V in case of
a Vcc voltage runaway above 18 V.
First, calculate the OPP network with the above equations.
Then, suppose we want to latch off our controller when Vout
exceeds 25 V. On the auxiliary winding, the plateau reflects
the output voltage by the turns ratio between the power and
the auxiliary windings. In case of voltage runaway for our
19−V adapter, the plateau will go up to:
V aux,OVP + 25
0.18 + 18 V
0.25
R OVP +
V latch * V VOP
+ 18 * 3 + 15 + 5 kW (eq. 16)
3m
V OVPńR OPPL
3ń1 k
In nominal conditions, the plateau establishes to around
14 V. Given the divide−by−6 ratio, the OPP pin will swing
to 14/6 = 2.3 V during normal conditions, leaving 700 mV
for the noise immunity. A 100−pF capacitor can be added to
improve it and avoids erratic trips in presence of external
surges. Do not increase this capacitor too much otherwise
the OPP signal will be affected by the integrating time
constant.
A second solution for the OVP detection alone, is to use
a Zener diode wired as recommended by Figure 38.
(eq. 15)
Since our OVP comparator trips at a 3−V level, across the
1−kW selected OPP pull−down resistor, it implies a 3−mA
current. From 3 V to go up to 18 V, we need an additional
15 V. Under 3 mA and neglecting the series diode forward
drop, it requires a series resistor of:
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NCP1254
D3
15 V
D2
1N4148
11
RoppU
421 k
Vcc
OPP
10
C1
22 pF
8
aux.
winding
4
ROPPL
1k
9
1
5
OVP
Vlatch
OPP
Figure 38. A Zener diode in series with a diode helps to improve the noise immunity of the system.
Over Temperature Protection
In this case, to still trip at a 18−V level, we have selected
a 15−V Zener diode. In nominal conditions, the voltage on
the OPP pin is almost 0 V during the off time as the Zener
is fully blocked. This technique clearly improves the noise
immunity of the system compared to that obtained from a
resistive string as in Figure 37. Please note the reduction of
the capacitor on the OPP pin to 10−22 pF. This is because of
the potential spike going through the Zener parasitic
capacitor and the possible auxiliary level shortly exceeding
its breakdown voltage during the leakage inductance reset
period (hence the internal 1−ms blanking delay at turn off).
This spike despite its very short time is energetic enough to
charge the added capacitor C1 and given the time constant,
could make it discharge slower, potentially disturbing the
blanking circuit. When implementing the Zener option, it is
important to carefully observe the OPP pin voltage (short
probe connections!) and check that enough margin exists to
that respect.
NTC
RoppU
D2
In a lot of designs, the adapter must be protected against
thermal runaways, e.g. when the temperature inside the
adapter box increases beyond a certain value. Figure 39
shows how to implement a simple OTP using an external
NTC and a series diode. The principle remains the same:
make sure the OPP network is not bothered by the additional
NTC hence the presence of this diode. When the NTC
resistor will diminish as the temperature increases, the
voltage on the OPP pin during the off time will slowly
increase and, once it crosses 3 V for 4 consecutive clock
cycles, the controller will permanently latch off.
1N4148
841 k
Vcc
OPP
aux.
winding
ROPPL
2.5 k
Vlatch
full latch
OPP
Figure 39. The internal circuitry hooked to pin 3 can be used to
implement over temperature protection (OTP).
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NCP1254
limit at the chosen output power level. Suppose we need a
200−mV decrease from the 0.8−V set point and the on−time
swing on the auxiliary anode is −67.5 V, then we need to drop
over ROPPU a voltage of:
Back to our 19−V adapter, we have found that the plateau
voltage on the auxiliary diode was 13 V in nominal
conditions. We have selected an NTC which offers a
470−kW resistor at 25°C and drops to 8.8 kW at 110 °C. If our
auxiliary winding plateau is 14 V and we consider a 0.6−V
forward drop for the diode, then the voltage across the NTC
in fault mode must be:
V NTC + 14 * 3 * 0.6 + 10.4 V
VR
Based on the 8.8−kW NTC resistor at 110 °C, the current
inside the device must be:
IR
3 + 2.5 kW
1.2 m
OPPL
+
200 m
+ 80 mA
2.5 k
(eq. 21)
R OPPU + 67.3 + 841 kW
80 m
(eq. 22)
Combining OVP and OTP
The OTP and Zener−based OVP can be combined
together as illustrated by Figure 40.
(eq. 19)
Now that the pull−down OPP resistor is known, we can
calculate the upper resistor value ROPPU to adjust the power
D3
(eq. 20)
The ROPPU value is therefore easily derived:
(eq. 18)
As such, the bottom resistor ROPPL , can easily be
calculated:
R OPPL +
+ 67.5 * 0.2 + 67.3 V
The current circulating in the pull down resistor ROPPL in
this condition will be:
(eq. 17)
I NTC + 10.4 [ 1.2 mA
8.8 k
OPPU
15 V
NTC
1N4148
D2
11
RoppU
841 k
Vcc
OPP
8
aux.
winding
4
10
9
1
ROPPL
2.5 k
5
Vlatch
OPP
OVP
Figure 40. with the NTC back in place, the circuit nicely combines OVP, OTP and OPP on the same pin
Filtering the Spikes
In nominal Vcc/output conditions, when the Zener is not
activated, the NTC can drive the OPP pin and trigger the
adapter in case of a fault. On the contrary, in nominal
temperature conditions, if the loop is broken, the voltage
runaway will be detected and acknowledged by the
controller.
In case the OPP pin is not used for either OPP or OVP, it
can simply be grounded.
The auxiliary winding is the seat of spikes that can couple
to the OPP pin via the parasitic capacitances exhibited by the
Zener diode and the series diode. To prevent an adverse
triggering of the Over Voltage Protection circuitry, it is
possible to install a small RC filter before the detection
network. Typical values are those given in Figure 41 and
must be selected to provide the adequate filtering function
without degrading the stand−by power by an excessive
current circulation.
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NCP1254
additional filter
D3
15 V
NTC
1N4148
D2
11
RoppU
C1
330 pF
2
841 k
220
R3
Vcc
9
3
OPP
10
aux.
winding
4
1
ROPPL
2.5 k
5
OVP
Vlatch
OPP
Figure 41. A small RC filter avoids the fast rising spikes from reaching the protection pin of
the NCP1254 in presence of energetic perturbations superimposed on the input line.
Latching Off with the Vcc Pin
Peak Power Excursions
The NCP1254 hosts a dedicated comparator on the Vcc
pin. When the voltage on this pin exceeds 25.5 V typically
for more than 20 ms, a signal is sent to the internal latch and
the controller immediately stops the driving pulses while
remaining in a lockout state. The part can be reset by cycling
down its Vcc, for instance by pulling off the power. This
technique offers a simple and cheaper means to protect the
converter against optocoupler failures without using the
OPP pin and a Zener diode.
There are applications where the load profile heavily
changes from a nominal to a peak value. For instance, it is
possible that a 30−W ac−dc adapter accepts power
excursions up to 60 W in certain conditions. Inkjet printers
typically fall in that category of peak power adapters.
However, to avoid growing the transformer size, an existing
technique consists in freezing the peak current to a
maximum value (0.8/Rsense in our case) but authorizes
frequency increase to a certain point. This point is internally
fixed at 130 kHz.
VFB (V)
4.5
4.0
Maximum frequency is FOSC,max
Peak current
is clamped
Fsw increases
3.2
1.9
1.5
Ipeak max
Fsw is fixed
65 kHz
Fsw decreases
26 kHz
Ipeak min
1
0.4
Peak current
can change
65 kHz
Peak current
is frozen
0 duty−ratio
t
Figure 42. The feedback pin modulates the frequency up to 130 kHz (short−circuit,
maximum power) or down to 26 kHz in frequency foldback.
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NCP1254
Figure 42 shows the voltage evolution from almost 0 V to
the open−loop level, around 4.5 V. At low power levels or in
no−load operation, the feedback voltage stays in the vicinity
of 400 mV and ensures skip−cycle operation. In this mode,
the peak current is frozen to 31% of its maximum value. This
freeze lasts as long as VFB stays below 1 V. Beyond 1 V, the
peak current is authorized to follow VFB through a ratio of
4. When the power demand goes up, the switching frequency
linearly increases from 26 kHz up to 65 kHz, a value reached
when the feedback voltage exceeds 1.5 V. Beyond 1.9 V, the
frequency no longer changes. As VFB still increases, we are
in a fixed−frequency variable peak current mode control
type of operation until the feedback voltage hits 3.2 V. At this
point, the maximum current is limited to 0.8 V/Rsense . If VFB
further increases, it means the converter undergoes an
overload and requires more power from the source. As the
peak current excursion is stopped, the only way to deliver
more power is to increase the switching frequency. From
3.2 V up to 4 V, the frequency linearly increases from
65 kHz to 130 kHz. The maximum power delivered by the
converter depends whether it operates in Discontinuous
Conduction Mode (DCM) or in Continuous Conduction
Mode (CCM):
P max,DCM + 1 L pF sw,maxI peak,max 2 h
2
P max,CCM + 1 L pF sw,maxǒI peak,max 2 * I valley 2Ǔ h
2
Where Ipeak,max is the maximum peak current authorized by
the controller and Ivalley the valley current reached just
before a new switching cycle begins. This current is
expressed by the following formula:
I valley + I peak *
V out ) V f
NL p
t off
(eq. 25)
In DCM, the valley current is equal to 0.
Two Levels of Protection
Once the feedback voltage asks for the maximum peak
current, the controller knows that an overload condition has
started. An internal timer is operated as soon as the
maximum peak current setpoint is reached. Its duration is
internally set to 200 ms. If the feedback voltage continues its
rise, it means that the converter output voltage is going down
further, close to a short−circuit situation. When the feedback
voltage approaches the open−loop level (above 4.0 V
typically), the original timer duration is divided by 4. For
instance, at start−up, even if the overload timer is
programmed to 200 ms, when the feedback voltage jumps
above 4.0 V, the controller will wait 50 ms before fault
detection occurs. Of course, if the feedback does not stay
that long in the region of concern, the timer is reset when
returning to a normal level. Figure 43 shows the timer values
versus the feedback voltage.
(eq. 23)
(eq. 24)
VFB (V)
4.5
4.0
max
Open loop voltage
25% timer − short−circuit
130 kHz
100% timer − overload
Max Ipeak
3.2
Fixed−frequency variable peak current
1.9
1
65 kHz
Frequency foldback variable peak current
1.5
Frozen current
Fixed frequency variable peak current
65 kHz
26 kHz
31% max Ipeak
Frozen peak current
0.4
Skip cycle
t
Figure 43. Depending on the feedback level, the timer will take two different values:
it will authorize a transient overload, but will reduce a short−circuit duration.
http://onsemi.com
23
NCP1254
2.4 V. When the maximum peak current situation is lifted,
the converter returns to a normal situation, the timer is reset.
The short circuit situation is detected by sensing a feedback
voltage beyond 3.6 V. For the sake of the explanation, we
have gathered two different events in Figure 44:
Please note that the overload situation (OVL) is detected
when the maximum peak current limit is hit. It can be 3.2 V
as indicated in the graph in case of no Over Power Protection
(OPP). If you have programmed an OPP level of −200 mV
for instance, the OVL threshold becomes (0.8 − 0.2) x 4 =
VFB
VFB
130 kHz
4.0 V
65 kHz
3.2 V
130 kHz
4.0 V
65 kHz
3.2 V
VCt
fault
fault
SC
SC
OVL
OVL
SC
OVL
Figure 44.
(VFB with no OPP). As the overload lasts less than 200 ms,
the feedback returns to its regulation level and resets the
timer.
In the second case, the overload occurs after regulation but
the feedback voltage quickly jumps into the short−circuit
area. At this point, the countdown is accelerated as the
charging slope changed to a steeper one. The load goes back
to an OVL mode and the counter slows down. Finally, back
to short circuit again and the timer trips the fault circuitry
after completion: all pulses are immediately stopped and an
auto−recovery double hiccup takes places.
When the feedback voltage exits a fault region before time
completion, the timer is reset. On the contrary, if the timer
elapses, the part enters an auto−recovery hiccup or latches
off depending on the operated version.
In the first case, the feedback is pushed to the maximum
upon start−up. The timer starts with a charging slope of the
short−circuit condition (SC). With an OVL timer internally
set to 200 ms, the timer duration in this start−up sequence is
50 ms. As soon as regulation occurs, the timer gets reset. An
overload occurs shortly after (OVL). The internal timer
immediately starts to count when the 3.2−V level is crossed
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24
NCP1254
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE U
D
ÉÉÉ
ÉÉÉ
6
E1
1
NOTE 5
5
2
H
L2
4
GAUGE
PLANE
E
3
L
b
C
DETAIL Z
e
0.05
M
A
SEATING
PLANE
c
A1
DETAIL Z
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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NCP1254/D