ONSEMI NCP1249AD65R2G

NCP1249A, NCP1249B
High-Voltage Current-Mode
PWM Controller Featuring
Peak Power Excursion and
Extremely Low Stand-by
Power Consumption
The NCP1249 is a highly integrated high−voltage PWM controller
capable of delivering a rugged and high performance offline power
supply with extremely low no−load consumption. With a supply range
up to 30 V, the controller hosts a jittered 65−kHz switching circuitry
operated in peak current mode control. When the power on the
secondary side starts to decrease, the controller automatically folds
back its switching frequency down to a minimum level of 26 kHz. As
the power further goes down, the part enters skip cycle while freezing
the peak current setpoint.
To help build rugged converters, the controller features several key
protective features: a internal brown−out, a non−dissipative Over
Power Protection for a constant maximum output current regardless of
the input voltage and two latched over voltage protection inputs −
either through a dedicated pin or via the VCC input.
The controller architecture is arranged to authorize a transient peak
power excursion when the peak current hits the limit. At this point, the
switching frequency is increased from 65 kHz to 130 kHz until the
peak requirement disappears. The timer duration is then modulated as
the converter crosses a peak power excursion mode (long) or
undergoes a short circuit (short).
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MARKING DIAGRAM
9
9
1
NCP1249x65
ALYW
G
SOIC−9 NB
D SUFFIX
CASE 751BP
1
NCP1249x65 = Specific Device Code
x
= A or B
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
X2
REM
FB
CS
OPP/LATCH
1
HV
VCC
DRV
GND
(Top View)
Features
• High−voltage Current Source for Lossless Start−up
• Frequency Jittering in Normal and Frequency Foldback
•
•
•
•
•
•
•
•
•
•
Sequence
Remote Input for Standby Operation Control
Automatic and Lossless X2 Capacitors Discharge
Function
65−kHz Fixed−frequency Current−mode Control
Operation with 130−kHz Excursion
Internal and Adjustable Over Power Protection (OPP)
Circuit
Internal Brown−Out Protection Circuit
Frequency Foldback down to 26 kHz and Skip−cycle in
Light Load Conditions
Adjustable Ramp Compensation
Internally Fixed 4−ms Soft−start
100% to 25% Timer Reduction from Overload to
Short−circuit Fault
•
•
•
•
•
•
Modes
Latched OVP Input for Improved Robustness and
Latched OVP on Vcc
Up to 30 V Vcc Maximum Rating
+300 mA/ −500 mA Source/Sink Drive Capability
Extremely Low No−load Standby Power
Option for Auto−Recovery or Latched Short−Circuit
Protection
Internal Thermal Shutdown with Hysteresis
These are Pb−Free Devices
Typical Applications
• Converters Requiring Peak−power Capability such as
Printers Power Supplies, ac−dc Adapters for Game
Stations
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 0
1
Publication Order Number:
NCP1249A/D
NCP1249A, NCP1249B
Figure 1. Typical Application Example
Table 1. PIN FUNCTIONS
Pin No
Pin Name
Function
Pin Description
1
X2
X2−capacitors discharge
When the voltage on this pin disappears,
the controller ensures the X2−capacitors discharge.
2
REM
Remote input
Initiates ultra low consumption mode (off−mode) when brought above 8 V.
3
FB
Feedback pin
Connecting an opto−coupler to this pin allows regulation.
4
CS
Current sense + ramp
compensation
This pin monitors the primary peak current but also offers
a means to introduce slope compensation.
5
OPP/Latch
Adjust the Over Power Protection
Latches off the part
A resistive divider from the auxiliary winding to this pin sets the OPP
compensation level. When brought above 3 V, the part is fully latched off.
6
GND
−
The controller ground.
7
DRV
Driver output
The driver’s output to an external MOSFET gate.
8
VCC
Supplies the controller
This pin is connected to an external auxiliary voltage and supplies the
controller. When above a certain level, the part fully latches off.
9
NC
−
Increases insulation distance between high and low voltage pins.
10
HV
High−voltage input
This pin provides a charging current during start−up and auto−recovery
faults but also a means to efficiently discharge the input X2 capacitors.
Table 2. OPTIONS AND ORDERING INFORMATION
Device
Overload
Protection
Switching
Frequency
Peak Frequency
Package
Shipping†
NCP1249AD65R2G
Latched
65 kHz
130 kHz
SOIC−9
(Pb−Free)
2500 / Tape &
Reel
NCP1249BD65R2G
Autorecovery
65 kHz
130 kHz
SOIC−9
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging.
Specifications Brochure, BRD8011/D.
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2
NCP1249A, NCP1249B
X2
HV
VHV
TSD
R
X2
timer
Q
S
Q
R
Brown−out
HV
startup
REM
BO _OK
REM
timer
Remote
timer
BO _bias EN
OPP/
Latch
Vcc management,
600 ns time
constant
logic and fault timer
UVLO
IpFlag
hiccup
Up
counter
RST
4
Vlatch
OVP
gone ?
S
R
VDD
Vdd
POR
20 s time
constant
VOVP
VCC
Idischarge
Q
Q
X2 & Vcc discharge
1 s
blanking
Resets
if Vcc < 3 V
65 kHz
clock
Clamp
Frequency
modulation
S
R
Q
Q
Frequency
foldback
DRV
Vfold
Vskip
Rramp
vdd
RFB
4 ms
SS
IpFlag
The soft−start is activated during :
−the startup sequence
−the auto−recovery burst mode
FB
VOPP
/PWM_ ON
CS
Vlimit + VOPP
+
300 mV
peak
Current
freeze
GND
LEB
Vlimit
Figure 2. Internal Circuit Architecture
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NCP1249A, NCP1249B
Table 3. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
Vcc
Power Supply voltage, VCC pin, continuous voltage
−0.3 to 30
V
VHV
High Voltage (HV) Pin (pin 10)
–0.3 to 500
V
Vpin_x
Maximum voltage on low power pins (X2, REM, FB, CS, OPP)
−0.3 to 10
V
VDRV
Maximum voltage on drive pin
−0.3 to Vcc+0.3
V
IOPP
Maximum injected current into the OPP pin
−2
mA
RθJ−A
Thermal Resistance Junction−to−Air
211
°C/W
TJ,max
Maximum Junction Temperature
150
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (All pins except HV) per JEDEC standard JESD22, Method A114E
2
kV
ESD Capability, Machine Model per JEDEC standard JESD22, Method A115A
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Rating
Symbol
Pin
Min
Typ
Max
Unit
HV STARTUP CURRENT SOURCE
VHV_min
Minimum voltage for current source operation (VCC = 4V)
10
−
30
60
V
Istart1
Current flowing out of VCC pin (VCC = 0 V)
8, 10
0.2
0.7
1
mA
Istart2
Current flowing out of VCC pin (VCC = VCC_ON – 0.5 V)
8, 10
6
10
15
mA
VCC_inhibit
VCC level for Istart1 to Istart2 transition
8
0.5
1
1.25
V
Istart_off
Off−state leakage current (VHV = 500 V, VCC = 15 V)
10
−
15
−
mA
IHV_off*mode_1
HV pin leakage current when off−mode is active (VHV = 141 V)
10
−
−
15
mA
IHV_off*mode_2
HV pin leakage current when off−mode is active (VHV = 325 V)
10
−
−
19
mA
VHV_min_off−mode
Minimum voltage on HV pin during off−mode (V_REM = 10V, VCC = 0V)
10
−
−
10
V
VCC_ON
VCC increasing level at which driving pulses are authorized
8
16
18
20
V
VCC_OFF
VCC decreasing level at which driving pulses are stopped
8
9.5
10
11
V
VCC_HYST
Hysteresis VCC_ON− VCC_OFF
8
6
−
−
V
VCC_bias
VCC level during a fault
8
4.7
5.5
6.5
V
ICC1
Internal IC consumption with IFB=75 mA, fSW=65 kHz and CL = 0
8
−
1.6
2.6
mA
ICC2
Internal IC consumption with IFB=75 mA, fSW=65 kHz and CL = 1 nF
8
−
2.3
3.4
mA
ICC3
Internal IC consumption with IFB=75 mA, fSW=130 kHz and CL = 0
8
−
1.9
2.9
mA
ICC4
Internal IC consumption with IFB=75 mA, fSW=130 kHz and CL = 1 nF
8
−
3.3
4.4
mA
ICC_skip
Internal IC consumption while in skip mode
8
660
960
1360
mA
ICC_latch
Internal IC consumption during Latch*off mode
8
−
350
520
mA
V_BO_on
Brown−Out turn−on threshold (VHV going up)
10
92
101
110
V
V_BO_off
Brown−Out turn−off threshold (VHV going down)
10
84
93
102
V
BO_Timer
Timer duration for line cycle drop−out
10
40
−
100
ms
SUPPLY SECTION
BROWN−OUT
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 5 below −300 mV.
4. A 1−MW resistor is connected from pin 4 to the ground for the measurement.
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NCP1249A, NCP1249B
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
Vth_X2
X2 timer disable switch threshold voltage
1
1
1.5
2
V
Vth_X2_hyst
Hysteresis on the X2 pin
1
−
100
−
mV
V_X2_clamp
X2 input clamp voltage
1
−
4
−
V
X2_Timer
X2 timer duration
1
70
−
140
ms
I_X2_leak
X2 input leakage current (V_X2 = 2.5 V)
1
−
−
0.3
mA
I_X2_dis
Maximum discharge switch current (VCC = 10V)
10
6
10
13
mA
Tr
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
7
−
40
80
ns
Tf
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
7
−
30
70
ns
ROH
Source resistance
7
−
13
−
W
ROL
Sink resistance
7
−
6
−
W
Isource
Peak source current, VGS = 0 V – note 1
7
300
mA
Isink
Peak sink current, VGS = 12 V – note 1
7
500
mA
VDRV_low
DRV pin level at VCC close to VCC_OFF with a 33−kW resistor to GND
7
8
−
−
V
VDRV_high
DRV pin level at VCC= VOVP −0.2 V, DRV unloaded
7
10
12
14
V
IIB
Input Bias Current @ 0.8 V input level on pin 4
4
Vlimit
Maximum internal current setpoint – Tj = 25 °C – pin 5 grounded
4
0.744
0.8
0.856
V
Vlimit
Maximum internal current setpoint –
Tj from −40° to 125°C – pin 5 grounded
4
0.72
0.8
0.88
V
Vfold_cs
Default internal voltage set point for
frequency foldback trip point ≈ 47% of Vlimit
4
475
mV
Vfreeze_cs
Internal peak current setpoint freeze (≈31% of Vlimit)
4
250
mV
TDEL
Propagation delay from current detection to gate off−state
4
100
TLEB
Leading Edge Blanking Duration
4
300
ns
TSS
Internal soft−start duration activated upon startup, auto−recovery
−
4
ms
IOPPo
Setpoint decrease for pin 5 biased to –250 mV – (Note 2)
4
31.3
%
IOOPv
Voltage setpoint for pin 5 biased to −250 mV – (Note 2)
Tj from −40° to 125 °C
4
IOPPs
Setpoint decrease for pin 5 grounded
4
fOSC_nom
Oscillation frequency, VFB < VFBtrans, pin 5 grounded
−
VFBtrans
Feedback voltage above which fsw increases
3
fOSC_max
Maximum oscillation frequency for VFB above VFBmax
−
115
VFBmax
Feedback voltage above which fsw is constant
3
Dmax
Maximum duty ratio
−
fjitter
Frequency jittering in percentage of fOSC
−
±5
%
fswing
Swing frequency over the whole frequency range
−
240
Hz
X2 DISCHARGE CIRCUITRY
DRIVE OUTPUT
CURRENT COMPARATOR
0.02
0.5
0.55
mA
150
0.62
0
ns
V
%
INTERNAL OSCILLATOR
57
65
71
3.2
V
130
140
3.8
4
4.2
V
76
80
84
%
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 5 below −300 mV.
4. A 1−MW resistor is connected from pin 4 to the ground for the measurement.
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5
kHz
kHz
NCP1249A, NCP1249B
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
V_REM_on
Remote pin voltage below which is the off−mode deactivated
(VREM going down) (VCC = 0 V)
2
1
1.5
2
V
V_REM_off
Remote pin voltage above which is the off−mode activated
(VREM going up)
2
7.2
8
8.8
V
REM_Timer
Remote timer duration
2
70
−
140
ms
R_SW_REM
Internal remote pull down switch resistance
2
1000
−
3000
W
I_REM_leak
Remote input leakage current (VREM = 9 V) (Note 1)
2
−
0.02
1
mA
Rup(FB)
Internal pull−up resistor
3
Req
Equivalent ac resistor from FB to gnd
3
Iratio
Pin 3 to current setpoint division ratio
3,4
4
−
Vfreeze_FB
Feedback voltage below which the peak current is frozen
3
1
V
1.9
V
REMOTE SECTION
FEEDBACK SECTION
17
10
15
kW
20
kW
FREQUENCY FOLDBACK
Vfold_FB
Frequency foldback level on the feedback pin –
≈47% of maximum peak current
3
ftrans
Transition frequency below which skip−cycle occurs
−
Vfold_end
End of frequency foldback feedback level, fsw = fmin
3
22
1.5
26
30
kHz
V
Vskip
Skip−cycle level voltage on the feedback pin
3
400
mV
Skip hysteresis
Hysteresis on the skip comparator – note 1
3
30
mV
INTERNAL SLOPE COMPENSATION
Vramp
Internal ramp level @ 25°C – note 3
4
2.5
V
Rramp
Internal ramp resistance to CS pin
4
20
kW
Vlatch
Latching level input
5
Tlatch−blank
Blanking time after drive turn off
5
1
ms
Tlatch−count
Number of clock cycles before latch confirmation
−
4
−
Tlatch−del
OVP detection time constant
5
600
ns
VOVL
Feedback voltage at which an overload is considered –
OPP pin is grounded
3
3.2
V
VSC
Feedback voltage above which a short−circuit is considered
3
3.9
4.1
4.3
V
Timer1
Fault timer duration when 3.2 < VFB < 4.1 V − overload
−
100
200
300
ms
Timer2
Fault timer duration when VFB > 4.1 V is Timer1/4 – short−circuit condition
−
25
50
75
ms
VOVP
Latched Over voltage protection on the Vcc rail
8
26
27.5
29
V
TOVP_del
Delay before OVP on Vcc confirmation
8
20
30
ms
TA−rec_timer
Auto−recovery timer duration
−
−
−
s
TTSD
Temperature shutdown TJ going up
−
150
°C
TTSD(HYS)
Temperature shutdown hysteresis
−
30
°C
PROTECTIONS
2.7
0.7
3
3.3
V
TEMPERATURE SHUTDOWN
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 5 below −300 mV.
4. A 1−MW resistor is connected from pin 4 to the ground for the measurement.
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
24
0.9
23
0.8
Istart1 (mA)
VHV_min (V)
22
21
20
19
0.7
0.6
18
17
−40 −25 −10
5
20
35
50
65
80
0.5
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. Minimum Current Source Operation,
VHV_min
Figure 4. High Voltage Startup Current
Flowing Out of VCC pin, Istart1
13
13
Istart_off (mA)
Istart2 (mA)
12
11
12
11
10
9
−40 −25 −10
5
20
35
50
65
80
10
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. High Voltage Startup Current
Flowing Out of VCC Pin, Istart2
Figure 6. Off−state Leakage Current, Istart_off
10.0
13
Ihv_off−mode_2 (mA)
Ihv_off−mode_1 (mA)
9.5
9.0
8.5
8.0
12
11
10
7.5
7.0
−40 −25 −10
5
20
35
50
65
80
9
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. HV Pin Current during Off−mode,
IHV_off_mode_1
Figure 8. HV Pin Current during Off−mode,
IHV_off_mode_2
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
18.0
10.2
10.1
VCC_OFF (V)
VCC_ON (V)
17.8
17.6
17.4
9.9
17.2
17.0
−40 −25 −10
5
20
35
50
65
80
9.8
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. VCC Increasing Level at which
Driving Pulses are Authorized, VCC_ON
Figure 10. VCC Decreasing Level at which
Driving Pulses are Stopped, VCC_OFF
8.0
6.0
7.9
5.8
VCC_bias (V)
VCC_HYST (V)
10.0
7.8
7.7
5.6
5.4
5.2
7.6
7.5
−40 −25 −10
5
20
35
50
65
80
5.0
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. VCC Hysteresis, VCC_HYST
Figure 12. VCC Level at Fault Modes, VCC_Bias
1.1
400
ICC_latch (mA)
VCC_inhibit (V)
1.0
0.9
350
300
0.8
0.7
−40 −25 −10
5
20
35
50
65
80
250
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. VCC Level for Istart1 to Istart2
Transition, VCC_inhibit
Figure 14. Internal IC Consumption during
Latch−off Mode, ICC_latch
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
91.0
103.5
V_BO_off (V)
V_BO_on (V)
90.5
103.0
102.5
90.0
89.5
5
20
35
50
65
80
89.0
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Brown−Out Turn−on Threshold,
V_BO_on
Figure 16. Brown−Out Turn−off Threshold,
V_BO_off
1.8
4.2
1.7
4.1
1.6
4.0
V_X2_Clamp (V)
Vth2_X2 (V)
102.0
−40 −25 −10
1.5
1.4
1.3
3.9
3.8
3.7
1.2
3.6
1.1
3.5
1.0
−40 −25 −10
5
20
35
50
65
80
3.4
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. X2 Timer Disable Switch Threshold,
Vth_X2
Figure 18. X2 Input Clamp Voltage, V_X2_clamp
11.0
1.8
10.5
10.0
V_REM_on (V)
IX2_dis (mA)
1.7
9.5
9.0
1.6
1.5
8.5
8.0
−40 −25 −10
5
20
35
50
65
80
1.4
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Maximum X2 Cap Discharge
Current, I_X2_dis
Figure 20. Off−mode Turn−off Threshold,
V_REM_on
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
2400
1.8
2300
R_SW_REM (W)
V_REM_off (V)
1.7
1.6
1.5
2200
2100
2000
1.4
−40 −25 −10
5
20
35
50
65
80
1900
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Off−mode Turn−on Threshold,
V_REM_off
Figure 22. Internal Remote Pull Down Switch
Resistance, R_SW_REM
50
40
35
Tf (ns)
Tr (ns)
45
30
40
25
35
−40 −25 −10
5
20
35
50
65
80
20
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Output Voltage Rise−time, Tr
Figure 24. Output Voltage Fall−time, Tf
11
16
10
15
ROH (W)
ROL (W)
9
8
7
14
13
12
6
5
−40 −25 −10
5
20
35
50
65
80
95 110 125
11
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. Source Resistance, ROL
Figure 26. Sink Resistance, ROH
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
14.0
11.0
13.5
VDRV_high (V)
VDRV_low (V)
10.5
10.0
13.0
12.5
12.0
9.5
11.5
9.0
−40 −25 −10
5
20
35
50
65
80
11.0
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. DRV Pin Level at VCC Close to
VCC_OFF, VDRVlow
Figure 28. DRV Pin Level at VCC Close to VOVP,
VDRVhigh
0.85
500
Vfold_CS (mV)
Vlimit (V)
0.83
0.81
0.79
490
480
0.77
0.75
−40 −25 −10
5
20
35
50
65
80
95
470
−40 −25 −10
110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. Maximum Internal Current
Set−point, Vlimit
Figure 30. Default Internal Voltage Set Point
for Frequency Foldback, Vfold_CS
55
250
54
53
TDEL (ns)
Vfreeze_cs (mV)
245
240
52
51
235
50
230
−40 −25 −10
5
20
35
50
65
80
95
110 125
49
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 31. Internal Peak Current Set−point
Freeze, Vfreeze_CS
Figure 32. Propagation Delay from Current
Detection to Gate Off−state, TDEL
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11
NCP1249A, NCP1249B
330
4.3
320
4.2
Tss (ms)
TLEB (ns)
TYPICAL CHARACTERISTICS
310
300
4.0
290
−40 −25 −10
5
20
35
50
65
80
95
3.9
−40 −25 −10
110 125
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 33. Leading Edge Blanking Duration,
TLEB
Figure 34. Internal Soft−start Duration, Tss
31.0
30.5
0.58
30.0
0.56
IOPPo (%)
IOPPv
5
TEMPERATURE (°C)
0.60
0.54
29.5
29.0
0.52
28.5
0.50
−40 −25 −10
5
20
35
50
65
80
28.0
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. CS Voltage Setpoint for OPP, IOPPv
Figure 36. Set−point Decrease for OPP, IOPPo
71
140
69
135
fOSC_max (Hz)
fOSC_nom (Hz)
4.1
67
65
130
125
63
61
−40 −25 −10
5
20
35
50
65
80
95 110 125
120
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. Oscillation Frequency, fOSC_nom
Figure 38. Maximum Oscilation Frequency,
fOSC_max
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
80.0
230
225
79.6
fswing (Hz)
Dmax (%)
79.8
79.4
220
215
79.2
79.0
−40 −25 −10
5
20
35
50
65
80
210
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. Maximum Duty−cycle, Dmax
Figure 40. Swing Frequency, fswing
4.10
14
4.05
Iratio (−)
Req (kW)
13
4.00
12
3.95
11
−40 −25 −10
5
20
35
50
65
80
3.90
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. Equivalent ac Resistor from FB to
GND, Req
Figure 42. FB to Current Set−point Division
Ratio, Iratio
26.5
2.00
26.0
ftrans (Hz)
Vfold_FB (V)
1.95
1.90
25.5
1.85
1.80
−40 −25 −10
5
20
35
50
65
80
95 110 125
25.0
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 43. Frequency Foldback Level, Vfold_FB
Figure 44. Transition Frequency below which
Skip−cycle Occurs, ftrans
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NCP1249A, NCP1249B
410
3.10
408
3.08
406
3.06
Vlatch (V)
Vskip (mV)
TYPICAL CHARACTERISTICS
404
402
3.02
400
−40 −25 −10
5
20
35
50
65
80
3.00
−40 −25 −10
95 110 125
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 45. Skip−cycle Level Voltage on the
Feedback Pin, Vskip
Figure 46. Latching Level Input, Vlatch
21.0
20.5
TOVP_del (ms)
27.3
VOVP (V)
5
TEMPERATURE (°C)
27.5
27.1
26.9
26.7
20.0
19.5
19.0
18.5
26.5
−40 −25 −10
5
20
35
50
65
80
18.0
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 47. Over Voltage Protection on VCC rail,
VOVP
Figure 48. OVP Detection Time Constant,
TOVP_del
206
52.0
205
51.5
Timer2 (ms)
Timer1 (ms)
3.04
204
203
51.0
50.5
202
−40 −25 −10
5
20
35
50
65
80
95 110 125
50.0
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 49. Fault Timer Duration − Overload,
Timer1
Figure 50. Fault Timer Duration − Short−circuit
Condition, Timer2
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NCP1249A, NCP1249B
TYPICAL CHARACTERISTICS
1.8
2.50
2.45
ICC2 (mA)
ICC1 (mA)
1.7
2.40
1.6
2.35
1.5
−40 −25 −10
5
20
35
50
65
80
2.30
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 51. Internal IC Consumption, ICC1
Figure 52. Internal IC Consumption, ICC2
3.3
1.8
ICC3 (mA)
ICC4 (mA)
1.7
3.2
1.6
1.5
−40 −25 −10
5
20
35
50
65
80
3.1
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 53. Internal IC Consumption, ICC3
Figure 54. Internal IC Consumption, ICC4
0.9
ICC_skip (mA)
0.8
0.7
0.6
0.5
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 55. Internal IC Consumption during
Skip Mode, ICC_skip
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NCP1249A, NCP1249B
APPLICATION INFORMATION
Introduction
The NCP1249 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count and cost effectiveness are
the key parameters, particularly in low−cost ac−dc adapters,
open−frame power supplies etc. The NCP1249 brings all the
necessary components normally needed in today modern
power supply designs, bringing several enhancements such
as a non−dissipative OPP, a brown−out protection or peak
power excursion for loads exhibiting variations over time.
Accounting for the new needs of extremely low standby
power requirements, the part includes an automatic
X2−capacitor discharge circuitry that prevents the designer
from installing power−consuming resistors across the
front−end filtering capacitors. The controller is also able to
enter a deep sleep mode via its dedicated remote pin.
• High−Voltage start−up: low standby power results
cannot be obtained with the classical resistive start−up
network. In this part, a high−voltage current−source
provides the necessary current at start−up and turns off
afterwards.
• Internal Brown−Out protection: a portion of the bulk
voltage is internally sensed via the high−voltage pin
monitoring (pin 10). When the voltage on this pin is too
low, the part stops pulsing. No re−start attempt is made
until the controller senses that the voltage is back
within its normal range. When the brown−out
comparator senses the voltage is acceptable, it sends a
general reset to the controller (de−latch occurs) and
authorizes to re−start.
• X2−capacitors discharge capability: per IEC−950
standard, the time constant of the front−end filter
capacitors and their associated discharge resistors must
be less than 1 s. This is to avoid electrical stress when
the user unplugs the converter and inadvertently
touches the power cord terminals. By providing an
automatic means to discharge the X2 capacitors, the
NCP1249 prevents the designer from installing the
discharge resistors, helping to further save power.
• Off−mode: Off−mode helps to achieve low power
consumption of an SMPS during no load conditions.
The IC goes into Off−mode when the REM pin is
brought higher than the internal reference voltage
V_REM_off. The disable input is pulled low, VCC
capacitor is discharged and consumption of all internal
blocks is reduced once the off−mode is activated. Off
mode is terminated when remote pin voltage crosses
V_REM_on threshold or application is unplugged from
the mains.
• Current−mode operation with internal slope
compensation: implementing peak current mode
control at a fixed 65−kHz frequency, the NCP1249
offers an internal ramp compensation signal that can
•
•
•
•
•
•
easily by summed up to the sensed current. Sub
harmonic oscillations can thus be compensated via the
inclusion of a simple resistor in series with the
current−sense information.
Frequency excursion: when the power demand forces
the peak current setpoint to reach the internal limit (0.8
V/Rsense typically), the frequency is authorized to
increase to let the converter deliver more power. The
frequency excursion stops when 130 kHz are reached.
Internal OPP: by routing a portion of the negative
voltage present during the on−time on the auxiliary
winding to the dedicated OPP pin (pin 5), the user has a
simple and non−dissipative means to alter the
maximum peak current setpoint as the bulk voltage
increases. If the pin is grounded, no OPP compensation
occurs. If the pin receives a negative voltage down to
–250 mV, then a peak current reduction down to 31.3%
typical can be achieved. For an improved performance,
the maximum voltage excursion on the sense resistor is
limited to 0.8 V.
EMI jittering: an internal low−frequency modulation
signal varies the pace at which the oscillator frequency
is modulated. This helps spreading out energy in
conducted noise analysis. To improve the EMI
signature at low power levels, the jittering will not be
disabled in frequency foldback mode (light load
conditions).
Frequency foldback capability: a continuous flow of
pulses is not compatible with no−load/light−load
standby power requirements. To excel in this domain,
the controller observes the feedback pin and when it
reaches a level of 1.5 V, the oscillator then starts to
reduce its switching frequency as the feedback level
continues to decrease. When the feedback pin reaches
1 V, the peak current setpoint is internally frozen and
the frequency continues to decrease. It can go down to
26 kHz (typical) reached for a feedback level of
450 mV roughly. At this point, if the power continues
to drop to 400 mV, the controller enters classical
skip−cycle mode.
Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start−up. In this
controller, the soft−start is internally fixed to 4 ms.
Soft−start is activated when a new startup sequence
occurs or during an auto−recovery hiccup.
Latch input: the NCP1249 includes a latch input (pin
5) that can be used to sense an overvoltage condition on
the adapter. If this pin is brought higher than the
internal reference voltage Vlatch, then the circuit
permanently latches off. The VCC pin is pulled down
to a fixed level, keeping the controller latched. The
latch reset occurs when the user disconnects the adapter
from the mains.
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NCP1249A, NCP1249B
• VCC OVP: a latched OVP protects the circuit against
•
♦
Vcc runaways. The fault must be present at least 20 ms
to be validated. Reset occurs when the user disconnects
the adapter from the mains.
Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (the aux winding level
does not properly collapse in presence of an output
short). Here, every time the internal 0.8−V maximum
peak current limit is activated (or less when OPP is
used), an error flag is asserted and a time period starts,
thanks to the programmable timer. The controller can
distinguish between two faulty situations:
♦ There is an extra demand of power, still within the
power supply capabilities. In that case, the feedback
level is in the vicinity of 3.2−4 V. It corresponds to
0.8 V as the maximum peak current setpoint without
OPP. The timer duration is then 100% of its normal
value. If the fault disappears, e.g. the peak current
setpoint no longer hits the maximum value (e.g.
0.8 V at no OPP), then the timer is reset.
♦
♦
The output is frankly shorted. The feedback level is
thus pushed to its upper stop (4.5 V) and the timer is
reduced to 25% of its normal value.
In either mode, when the fault is validated, all pulses
are stopped and the controller enters an
auto−recovery burst mode, with a soft−start
sequence at the beginning of each cycle. Please note
the presence of a divider by two which ignores one
hiccup cycle over two (double hiccup type of burst).
As soon as the fault disappears, the SMPS resumes
operation. Please note that some version offers an
auto−recovery mode as we just described, some do
not and latch off in case of a short circuit.
Start−up Sequence
The start−up sequence of the NCP1249 involves a
high−voltage current source whose input is in pin 10. As this
start−up source also performs line sensing for brown−out
operation, it is recommended to wire it according to
Figure 56 sketch.
Vbulk
to X2 discharge
L1
1
L2
2
10
9
8
3
7
6
5
Ic
.
4
Vcc
Figure 56. The startup resistor can be connected to the input mains for further power dissipation reduction
capacitor at first and experiments in the laboratory will let
us know if we were too optimistic for t1. The VCC capacitor
being known, we can now evaluate the charging time to
bring the VCC voltage from 0 to the VCC_ON of the IC, 18 V
typical. This time sequence can actually be split into two
events: 0 V to VCC_inhibit and VCC_inhibit to VCC_ON . This is
because the HV source is protected from short−circuits on
the VCC pin. In case this happens, the source detects that the
VCC voltage is less than VCC_inhibit and only delivers Istart1
which is below 1 mA: the die power consumption is
maintained to the lowest value. In normal operation, when
the voltage has normally reached VCC_inhibit, the source
toggles to the full current and charges the VCC capacitor at
a larger current, Istart2 . The first time duration involves Istart1
and VCC_inhibit.
In this drawing, the high−voltage pin is not connected to
the bulk, but to the full−wave rectified ac input. It is
important to keep this configuration as the X2 circuitry will
also use it.
The first step starts with the calculation of the needed VCC
capacitor which will supply the controller until the auxiliary
winding takes over. Experience shows that this time t1 can
be between 5 and 20 ms. Considering that we need at least
an energy reservoir for a t1 time of 10 ms, the VCC capacitor
must be larger than:
C Vcc w
(eq. 1)
I CC4 t 1
3 m 10 m
w
w 3.75 mF
18 * 10
V CC_ON * V CC_OFF
In this calculation, we adopted the consumption at the
highest switching frequency since this is the point at which
the IC will work in cold−start case. Let us select a 4.7 mF
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NCP1249A, NCP1249B
t start1 +
V CC_inhibit
C Vcc
I start1
+
1
4.7 m
[ 6.7 ms
700 m
(eq. 2)
The second duration involves VCC_ON and Istart2:
t start2 +
ǒVCC_ON * VCC_inhibitǓCVcc
I start2
+
(18 * 1) 4.7 m
[ 8 ms
10 m
(eq. 3)
The total start−up time is thus around 14−15 ms.
Vcc_bias level. The HV current source maintains VCC at
Vcc_bias level until the input voltage is back above V_BO_on .
The controller then fully discharges VCC capacitor first to
restart internal logic. Standard startup attempt is then placed
by the controller.
Figure 57. The VCC at start−up is made of two
segments given the short−circuit protection
implemented on the HV source
In case the VCC capacitor must be increased to cope with
no−load standby requirements, there is plenty of margin to
keep the total start−up sequence duration below 1 s. Assume
the VCC capacitor is 100 mF, then the total start−up time
would be below 400 ms.
Figure 58. Simplified Block Diagram of
Brown−out Detection Circuitry
Brown−out Circuitry
The NCP1249 features, on its HV pin, a true AC line
monitoring circuitry – refer to Figure 58. This system
includes a minimum start−up threshold and auto−recovery
brown−out protection; both of them independent of the input
voltage ripple. The thresholds are fixed, but they are
designed to fit most of the standard AC−DC converter
applications. When the HV pin voltage drops below V_BO_off
threshold for more than 50 ms, the brown−out condition is
detected and confirmed. Thus the controller stops operation
– refer to Figure 59. The VCC capacitor is discharged to
The Internal HV BO sensing network is formed by high
impedance resistor divider with minimum resistance of
20 MW. This solution reducing power losses during
off−mode and thus helps to pass maximum standby power
consumption limit. The internal BO network solution
provides excellent noise and PCB leakage currents
immunity that is hard to achieve when using external resistor
divider built from SMT chip resistors.
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NCP1249A, NCP1249B
Figure 59. Brown−out Event Detection
X2 and VCC Discharge Circuitry
consuming X2 timer disable circuitry. The internal X2 timer
with typical duration of 100 ms is used to overcome
unwanted activation of the X2 discharge switch in case of
AC line dropout. The internal X2 discharge switch is
activated once the X2 timer elapses. The HV startup current
source is enabled in the same time thus the discharge path for
X2 capacitor exists – refer to Figure 60.
The NCP1249 X2 discharge circuitry uses dedicated pin
(X2) together with external charge pump sensing network to
detect whether is application plugged into the mains or not.
Advantage of this solution is that the internal IC
consumption can be reduced to extremely low level by
keeping all internal blocks unbiased except simple and low
Figure 60. Simplified Block Diagram of X2 and Vcc Capacitor Discharge Circuitry
unwanted overheat that could occur in case the X2 pin is
opened and the high voltage is present on the HV pin (like
during open – short pins testing for instance).
The X2 discharge switch is also activated to discharge
VCC capacitor when entering into fault mode (latch mode,
auto−recovery mode or the HV pin voltage drops below
V_BO_off threshold for more than 50 ms), off−mode and also
before controller VCC restart.
The time duration of X2 capacitors discharging could be
calculated by:
t+
UC
X1,2
I _X2_dis
@ C X1,2
(eq. 4)
The X2 capacitor discharging process can be interrupted
by increasing voltage on X2 pin back above Vth_X2 .
The over temperature protection block is active during
discharging process to protect controller chip against
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NCP1249A, NCP1249B
Remote Input with Remote Timer
remote pin voltage exceeds V_REM_off threshold (8 V
typically). Normal operating mode (i.e. on−mode) is then
initiated again when remote input voltage drops back below
V_REM_on threshold (1.5 V typically) – refer to Figure 61 for
better understanding.
The NCP1249A/B features dedicated input (REM pin)
that allows user to activate ultra low consumption mode
during which the IC consumption is reduced to only very
low HV pin leakage current (refer to IHV_off−mode_1 and
IHV_off−mode_2 parameters). The off−mode is activated when
Figure 61. Simplified Block Diagram of Remote Control Input
• Restart after VCC has been lost while remote pin was at
The off−mode is activated when the remote input is pulled
up by auxiliary remote supply (refer to Figure 61.). The
normal operation mode is then activated when dedicated
opto−coupler pulls the remote input down. There could
occur situation, in the application, that the auxiliary remote
supply stays charged while the secondary bias has been lost.
The application then cannot restart until the auxiliary remote
supply capacitor fully discharges. Thus the remote input
hosts internal pull down switch and remote timer with
duration REM_timer. The controller pulls down remote pin
using this circuitry in order to allow correct application
restart in case the auxiliary bias capacitor (C1) stays charged
while the secondary side is fully discharged already. The
remote timer is activated each time the application starts
after these events:
• Start after application was plugged into the mains (X2
discharger signal resets remote timer latch in this case)
• Start after application has been un−latched by
re−plugging to the mains (X2 discharger signal resets
remote timer latch in this case)
• Restart from fault conditions in auto−recovery versions
low state
• Restart after BO event
• Restart after OVP/OTP event
The remote timer helps to assure correct application start
or re−start from fault conditions by forcing controller
operation for 100 ms typically. However, the secondary
controller drives remote pin via opto−coupler during normal
operating conditions in order to switch between on−mode
and off−mode states. The on−mode is activated for very
short time during no−load conditions − just to re−fill primary
and secondary capacitors to keep application biased. The
remote timer thus cannot be used in this case because it
would increase no−load power consumption by forcing
application on−mode operation for longer time than it is
naturally needed. The remote timer with internal pull down
switch is thus not activated in this case (i.e. when application
restarts from off−mode operation).
Operating Status Diagram
The NCP1249A/B VCC management behavior is clearly
described in status diagram on Figure 62.
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NCP1249A, NCP1249B
Efficient operating
mode
BO
Reset
Start
Vcc −> 5V
DRV = 0
(VCC > VCC_off) & BO &
(V_REM > V_REM_ON) &
Latch = 0
BO
BO
(V CC > VCCon) & BO
Charge VCC
Vcc −> 22V
DRV = 0
Operation
Vcc = Vcc_off –
Vcc_max
DRV = 1
V_REM> V_REM_off
TSD=1
Latch
Vcc = 5V
DRV = 0
X2 detect = 0
& X2_timer = 1
X2 cap
Discharge
X2_timer = 0
Vcc = 5V
REMOTE
Mode
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÏÏ
Vcc = floating
DRV = 0
V_REM >V_REM_ON
Vcc > 5V
X2 discharge = 0
Vcc = xV
DRV = x
X2_timer = 1
REMOTE
Discharge
Vcc −> 5V
DRV = 0
Vcc < Vcc_on
X2 Timer
Extra Low
Consumption
TA−rec_timer = 1
TSD
BO
Vcc = 5V
DRV = 0
TA −rec _timer = 1
Vcc = xV
DRV = 0
X2 detect = 1
VCC_fault
BO fault
Vcc = 5V
DRV = 0
Discharge VCC
DRV = 0
Vcc −> 0V
HV −> 0V
Vcc −> 0.7V
DRV = 0
X2 detect = 0
Vcc > 1V
Figure 62. VCC Management Status Diagram
Internal Over Power Protection
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
swing present on the auxiliary diode anode. During the
turn−on time, this point dips to −NVin, N being the turns ratio
between the primary winding and the auxiliary winding. The
negative plateau observed on Figure 63 will have amplitude
depending on the input voltage. The idea implemented in
this chip is to sum a portion of this negative swing with the
0.8 V internal reference level. For instance, if the voltage
swings down to −150 mV during the on time, then the
internal peak current set point will be fixed to 0.8 − 0.150 =
650 mV. The adopted principle appears in Figure 64 and
shows how the final peak current set point is constructed.
Figure 63. The signal obtained on the auxiliary
winding swings negative during the on−time
Let’s assume we need to reduce the peak current from
2.5 A at low line, to 2 A at high line. This corresponds to a
20% reduction or a set point voltage of 640 mV. To reach this
level, then the negative voltage developed on the OPP pin
must reach:
V OPP + 640 m * 800 m + −160 mV
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(eq. 5)
NCP1249A, NCP1249B
Figure 64. The OPP circuitry affects the maximum peak current set point by
summing a negative voltage to the internal voltage reference
Let us assume that we have the following converter
characteristics:
Vout = 19 V
Vin = 85 to 265 V rms
N1 = Np:Ns = 1:0.25
N2 = Np:Naux = 1:0.18
Given the turns ratio between the primary and the auxiliary
windings, the on−time voltage at high line (265 Vac) on the
auxiliary winding swings down to:
V aux + −N 2V in,max + −0.18
To obtain a level as imposed by (Eq. 5), we need to install
a divider featuring the following ratio:
Div + 0.16 [ 2.4 m
67.5
(eq. 7)
If we arbitrarily fix the pull−down resistor ROPPL to 1 kW,
then the upper resistor can be obtained by:
R OPPU + 67.5 * 0.16 [ 421 kW
0.16ń1 k
(eq. 8)
If we now plot the peak current set point obtained by
implementing the recommended resistor values, we obtain
the following curve (Figure 65):
375 + −67.5 V (eq. 6)
Peak current
setpoint
100%
80%
375
Vbulk
Figure 65. The peak current regularly reduces down to 20% at 375 V dc
maximum peak reduction is kept to 40%. If the voltage
finally forward biases the internal zener diode, then care
must be taken to avoid injecting a current beyond –2 mA.
Given the value of ROPPU , there is no risk in the present
example. Finally, please note that another comparator
internally fixes the maximum peak current set point to 0.8 V
even if the OPP pin is adversely biased above 0 V.
For optimum performance over temperature, we
recommend keeping the low−side OPP resistor below 3 kW.
The OPP pin is surrounded by Zener diodes stacked to
protect the pin against ESD pulses. These diodes accept
some peak current in the avalanche mode and are designed
to sustain a certain amount of energy. On the other side,
negative injection into these diodes (or forward bias) can
cause substrate injection which can lead to an erratic circuit
behavior. To avoid this problem, the pin is internal clamped
slightly below –300 mV which means that if more current is
injected before reaching the ESD forward drop, then the
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NCP1249A, NCP1249B
Frequency Foldback
feedback pin until its level reaches 1 V. Below this value, the
peak current freezes to Vfreeze_FB (250 mV or ≈31% of the
maximum 0.8 V setpoint) and the only way to further reduce
the transmitted power is to diminish the operating frequency
down to 26 kHz. This value is reached at a voltage feedback
level of 450 mV typically. Below this point, if the output
power continues to decrease, the part enters skip cycle for
the best noise−free performance in no−load conditions.
Figure 66 depicts the adopted scheme for the part.
The reduction of no−load standby power associated with
the need for improving the efficiency, requires a change in
the traditional fixed−frequency type of operation. This
controller implements a switching frequency foldback when
the feedback voltage passes below a certain level, Vfold_FB,
set around 1.9 V. At this point, the oscillator turns into a
Voltage−Controlled Oscillator and reduces its switching
frequency. The peak current setpoint is following the
fsw
0.80 V
Vfreeze_FB Vfold_FB
1.0 V
1.9 V
Vfold_end Vfold_FB
Figure 66. By observing the voltage on the feedback pin, the controller reduces
its switching frequency for an improved performance at light load
Auto−recovery Short−circuit Protection
thus to restart converter operation in case the input line
voltage is above V_BO_on threshold. The controller is then
checking for the absence of the fault. If the fault is still there,
the supply enters another cycle of so−called hiccup. If the
fault has disappeared, the power supply resumes operations.
Please note that the soft−start is activated during each of the
re−start sequence.
In case of output short−circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. If the flag is
asserted longer than fault timer duration, the driving pulses
are stopped and the VCC capacitor is discharged down to
10 V (VCC_OFF threshold) by controller Icc consumption. At
this point, the controller activates 2 s auto−recovery timer
that starts to count down the time to new restart attempt. The
total restart time from fault confirmation is thus given by
sum of two times: VCC capacitor discharge time from given
Vcc level (present at fault confirmation event) to VCC_OFF
level and 2 s internal auto−recovery timer duration. The VCC
capacitor is discharged to Vcc_bias level when
auto−recovery timer starts counting. The VCC is maintained
at Vcc_bias level during this operation to keep timer and
other internal circuitry running.
The VCC capacitor is fully discharged by X2 discharge
switch before controller tries for restart from fault condition.
The restart from fault condition is caused when
auto−recovery timer elapses or VCC is forced below 4 V
externally. The HV startup current source is activated to
charge the Vcc capacitor in fast manner to VCC_ON level and
Slope Compensation
The NCP1249 includes an internal ramp compensation
signal. This is the buffered oscillator clock delivered during
the on time only. Its amplitude is around 2.5 V at the
maximum authorized duty−ratio. Ramp compensation is a
known means used to cure sub harmonic oscillations in
CCM−operated
current−mode
converters.
These
oscillations take place at half the switching frequency and
occur only during Continuous Conduction Mode (CCM)
with a duty−ratio greater than 50%. To lower the current
loop gain, one usually mixes between 50 and 100% of the
inductor downslope with the current−sense signal.
Figure 67 depicts how internally the ramp is generated.
Please note that the ramp signal will be disconnected from
the CS pin, during the off−time.
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NCP1249A, NCP1249B
2.5 V
0V
ON
latch
reset
20k
+
Rcomp
L.E.B
CS
−
Rsense
from FB
setpoint
Figure 67. Inserting a resistor in series with the current sense information
brings slope compensation and stabilizes the converter in CCM operation
In the NCP1249 controller, the oscillator ramp exhibits a
2.5 V swing reached at a 80% duty−ratio. If the clock
operates at a 65−kHz frequency, then the available oscillator
slope corresponds to:
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small 100 pF capacitor, from the current sense pin
to the controller ground for improved noise immunity.
Please make sure both components are located very close to
the controller.
(eq. 9)
V ramp
2.5
S ramp+
+
+208kVńs or 208mVńms
D max T sw 0.8 15 m
Latching Off the Controller
In our flyback design, let’s assume that our primary
inductance Lp is 770 mH, and the SMPS delivers 19 V with
a Np :Ns turns ratio of 1:0.25. The off−time primary current
slope Sp is thus given by:
Sp +
ǒVout ) VfǓ NNp
Lp
The OPP pin not only allows a reduction of the peak
current set point in relationship to the line voltage, it also
offers a means to permanently latch−off the part. When the
part is latched−off, the VCC pin is internally pulled down to
VCC_bias and the part stays in this state until the user
un−plugs the converter from the mains outlet or VCC is
forced below 4 V externally. The latch detection is made by
observing the OPP pin by a comparator featuring a 3 V
reference voltage. However, for noise reasons and in
particular to avoid the leakage inductance contribution at
turn off, a 1 ms blanking delay is introduced before the
output of the OVP comparator is checked. Then, the OVP
comparator output is validated only if its high−state duration
lasts a minimum of 600 ns. Below this value, the event is
ignored. Then, a counter ensures that only four successive
OVP events have occurred before actually latching the part.
There are several possible implementations, depending on
the needed precision and the parameters you want to control.
The first and easiest solution is the additional resistive
divider on top of the OPP one. This solution is simple and
inexpensive but requires the insertion of a diode to prevent
disturbing the OPP divider during the on−time.
(eq. 10)
(19 ) 0.8)
s
+
770 m
4
+ 103 kAńs
Given a sense resistor of 330 mW, the above current ramp
turns into a voltage ramp of the following amplitude:
(eq. 11)
S sense +S pR sense +103 k
0.33+34 kVńs or 34 mVńms
If we select 50% of the downslope as the required amount
of ramp compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
208 mV/ms, the divider ratio (divratio) between Rcomp and
the internal 20 kW resistor is:
divratio +
17 m
+ 0.082
208 m
(eq. 12)
The series compensation resistor value is thus:
(eq. 13)
R comp + R ramp divratio + 20 k
0.082 [ 1.64 kW
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NCP1249A, NCP1249B
D2
1N4148
R3
5k
11
RoppU
421k
Vcc
9
8
OPP
10
C1
100p
aux.
winding
4
1
ROPPL
1k
5
OVP
Vlatch
OPP
Figure 68. Simple resistive divider brings the OPP pin above 3 V in case of a Vcc voltage runaway above 18 V
First, calculate the OPP network with the above equations.
Then, suppose we want to latch off our controller when Vout
exceeds 25 V. On the auxiliary winding, the plateau reflects
the output voltage by the turns ratio between the power and
the auxiliary windings. In case of voltage runaway for our
19 V adapter, the plateau will go up to:
V aux,OVP + 25
0.18 + 18 V
0.25
R OVP +
In nominal conditions, the plateau establishes to around
14 V. Given the divide−by ratio 6, the OPP pin will swing to
14/6 = 2.3 V during normal conditions, leaving 700 mV for
the noise immunity. A 100 pF capacitor can be added to
improve it and avoids erratic trips in presence of external
surges. Do not increase this capacitor too much otherwise
the OPP signal will be affected by the integrating time
constant.
A second solution for the OVP detection alone, is to use
a Zener diode wired as recommended by Figure 69.
(eq. 14)
Since our OVP comparator trips at a 3 V level, across the
1 kW selected OPP pull−down resistor, it implies a 3 mA
current. From 3 V to go up to 18 V, we need an additional
15 V. Under 3 mA and neglecting the series diode forward
drop, it requires a series resistor of:
D3
15V
V latch * V VOP
+ 18 * 3 + 15 + 5 kW (eq. 15)
3m
V OVPńR OPPL
3ń1 k
D2
1N4148
11
RoppU
421k
Vcc
OPP
10
C1
22pF
9
8
aux.
winding
4
1
ROPPL
1k
5
Vlatch
OVP
OPP
Figure 69. Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System
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NCP1249A, NCP1249B
ended and VCC is between VCC_ON and VCC_OFF levels, the
controller immediately stops driver pulses. After the
temperature falls back below the lower threshold, the VCC
capacitor is fully discharged by X2 discharge switch to
restart the controller.
The TSD protection can be activated at some other cases
(charging VCC capacitor − start−up sequence and
discharging X2 or VCC capacitors). The TSD protection
only interrupts current operating sequence – i.e. the
operation sequence continue after the temperature falls back
below the lower threshold. The controller is not reset by
TSD activation in these cases.
In a lot of designs, the adapter must be protected against
thermal runaways, e.g. when the temperature inside the
adapter box increases beyond a certain value. Figure 70
shows how to implement a simple OTP using an external
NTC and a series diode. The principle remains the same:
make sure the OPP network is not bothered by the additional
NTC hence the presence of this diode. When the NTC
resistor will diminish as the temperature increases, the
voltage on the OPP pin during the off time will slowly
increase and, once it crosses 3 V for 4 consecutive clock
cycles, the controller will permanently latch off.
In this case, to still trip at a 18 V level, we have selected
a 15 V Zener diode. In nominal conditions, the voltage on
the OPP pin is almost 0 V during the off time as the Zener
is fully blocked. This technique clearly improves the noise
immunity of the system compared to that obtained from a
resistive string as in Figure 68. Please note the reduction of
the capacitor on the OPP pin to 10−22 pF. This is because of
the potential spike going through the Zener parasitic
capacitor and the possible auxiliary level shortly exceeding
its breakdown voltage during the leakage inductance reset
period (hence the internal 1 ms blanking delay at turn off).
This spike despite its very short time is energetic enough to
charge the added capacitor C1 and given the time constant,
could make it discharge slower, potentially disturbing the
blanking circuit. When implementing the Zener option, it is
important to carefully observe the OPP pin voltage (short
probe connections!) and check that enough margin exists to
that respect.
Internal and External Over Temperature Protection
The NCP1249 includes a temperature shutdown
protection. When the temperature rises above the high
threshold during stable operation − i.e. start−up sequence is
NTC
D2
1N4148
RoppU
841k
Vcc
OPP
aux.
winding
ROPPL
2.5k
Vlatch
full latch
OPP
Figure 70. The internal circuitry hooked to pin 1 can be used to implement over temperature protection (OTP)
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NCP1249A, NCP1249B
Back to our 19 V adapter, we have found that the plateau
voltage on the auxiliary diode was 13 V in nominal
conditions. We have selected an NTC which offers a 470 kW
resistor at 25°C and drops to 8.8 kW at 110°C. If our
auxiliary winding plateau is 14 V and we consider a 0.6 V
forward drop for the diode, then the voltage across the NTC
in fault mode must be:
V NTC + 14 * 3 * 0.6 + 10.4 V
limit at the chosen output power level. Suppose we need a
200 mV decrease from the 0.8 V set point and the on−time
swing on the auxiliary anode is −67.5 V, then we need to drop
over ROPPU a voltage of:
VR
Based on the 8.8 kW NTC resistor at 110°C, the current
inside the device must be:
IR
3 + 2.5 kW
1.2 m
(eq. 19)
OPPL
+
200 m
+ 80 mA
2.5 k
(eq. 20)
The ROPPU value is therefore easily derived:
(eq. 17)
R OPPU + 67.3 + 841 kW
80 m
As such, the bottom resistor ROPPL , can easily be calculated:
R OPPL +
+ 67.5 * 0.2 + 67.3 V
The current circulating in the pull down resistor ROPPL in
this condition will be:
(eq. 16)
I NTC + 10.4 [ 1.2 mA
8.8 k
OPPU
(eq. 21)
Combining OVP and OTP
(eq. 18)
The OTP and Zener−based OVP can be combined
together as illustrated by Figure 71.
Now that the pull−down OPP resistor is known, we can
calculate the upper resistor value ROPPU to adjust the power
D3
15V
D2
1N4148
NTC
11
RoppU
841k
Vcc
OPP
8
aux.
winding
4
10
9
1
ROPPL
2.5k
5
Vlatch
OVP
OPP
Figure 71. With the NTC back in place, the circuit nicely combines OVP, OTP and OPP on the same pin
Filtering the Spikes
In nominal VCC/output conditions, when the Zener is not
activated, the NTC can drive the OPP pin and trigger the
adapter in case of a fault. On the contrary, in nominal
temperature conditions, if the loop is broken, the voltage
runaway will be detected and acknowledged by the
controller.
In case the OPP pin is not used for either OPP or OVP, it
can simply be grounded.
The auxiliary winding is the seat of spikes that can couple
to the OPP pin via the parasitic capacitances exhibited by the
Zener diode and the series diode. To prevent an adverse
triggering of the Over Voltage Protection circuitry, it is
possible to install a small RC filter before the detection
network. Typical values are those given in Figure 72 and
must be selected to provide the adequate filtering function
without degrading the stand−by power by an excessive
current circulation.
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NCP1249A, NCP1249B
D3
15V
additional filter
D2
1N4148
NTC
11
C1
330pF
2
RoppU
841k
R3
220
Vcc
OPP
9
3
aux.
4
10
winding
1
ROPPL
2.5k
5
Vlatch
OVP
OPP
Figure 72. A small RC filter avoids the fast rising spikes from reaching the protection pin of the
NCP1249 in presence of energetic perturbations superimposed on the input line
Latching Off with the VCC pin
Peak Power Excursions
The NCP1249 hosts a dedicated comparator on the VCC
pin. When the voltage on this pin exceeds 27.5 V typically
for more than 20 ms, a signal is sent to the internal latch and
the controller immediately stops the driving pulses while
remaining in a lockout state. The part can be reset when the
user disconnects the adapter from the mains. This technique
offers a simple and cheaper means to protect the converter
against optocoupler failures without using the OPP pin and
a Zener diode.
There are applications where the load profile heavily
changes from a nominal to a peak value. For instance, it is
possible that a 30 W ac−dc adapter accepts power
excursions up to 60 W in certain conditions. Inkjet printers
typically fall in that category of peak power adapters.
However, to avoid growing the transformer size, an existing
technique consists in freezing the peak current to a
maximum value (0.8/Rsense in our case) but authorizes
frequency increase to a certain point. This point is internally
fixed at 130 kHz.
Figure 73. The feedback pin modulates the frequency up to 130 kHz
(short−circuit, maximum power) or down to 26 kHz in frequency foldback
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NCP1249A, NCP1249B
Figure 73 shows the voltage evolution from almost 0 V to
the open−loop level, around 4.5 V. At low power levels or in
no−load operation, the feedback voltage stays in the vicinity
of 400 mV and ensures skip−cycle operation. In this mode,
the peak current is frozen to 31% of its maximum value and
the operating frequency is 26 kHz. This freeze lasts as long
as VFB stays below 1 V. Beyond 1 V, the peak current is
authorized to follow VFB through a ratio of 4. When the
power demand goes further up, the feedback pin crosses a
level of 1.5 V where the switching frequency linearly
increases from 26 kHz up to 65 kHz, a value reached when
the feedback voltage exceeds 1.9 V. Beyond 1.9 V, the
frequency no longer changes. As VFB still increases, the
controller is in a fixed−frequency variable peak current
mode control type of operation until the feedback voltage
hits 3.2 V. At this point, the maximum current is limited to
0.8 V/Rsense . If VFB further increases, it means the converter
undergoes an overload and requires more power from the
source. As the peak current excursion is stopped, the only
way to deliver more power is to increase the switching
frequency. From 3.2 V up to 4.1 V, the frequency linearly
increases from 65 kHz to 130 kHz. Beyond 4.1 V, the
frequency is fixed to 130 kHz. The maximum power
delivered by the converter depends whether it operates in
Discontinuous Conduction Mode (DCM) or in Continuous
Conduction Mode (CCM):
P max,DCM + 1 L p f OSC_max I peak,max 2 h
2
(eq. 22)
P max,CCM + 1 L p f OSC_max ǒI peak,max 2 * I valley 2Ǔ h (eq. 23)
2
Where Ipeak,max is the maximum peak current authorized
by the controller and Ivalley the valley current reached just
before a new switching cycle begins. This current is
expressed by the following formula:
I valley + I peak *
V out ) V f
NL p
t off
(eq. 24)
In DCM, the valley current is equal to 0.
Two Levels of Protection
Once the feedback voltage asks for the maximum peak
current, the controller knows that an overload condition has
started. An internal timer is operated as soon as the
maximum peak is reached. If the feedback voltage continues
its rise, it means that the converter output voltage is going
down further, close to a short−circuit situation. When the
feedback voltage reaches the open−loop level (above 4.1 V
typically), the original timer duration is divided by 4. Of
course, if the feedback does not stay that long in the region
of concern, the timer is reset when returning to a normal
level. Figure 74 shows the timer values versus the feedback
voltage.
Figure 74. Depending on the feedback level, the timer will take two different values: it will
authorize a transient overload, but will reduce a short−circuit duration
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NCP1249A, NCP1249B
the converter returns to a normal situation, the timer is reset.
The short circuit situation is detected by sensing a feedback
voltage beyond 4.1 V. For the sake of the explanation, we
have gathered two different events in Figure 75 (VCt is
voltage on internal capacitor which defines fault timer
duration).
Please note that the overload situation (OVL) is detected
when the maximum peak current limit is hit. It can be 3.2 V
as indicated in the graph in case of no Over Power Protection
(OPP). If you have programmed an OPP level of −200 mV
for instance, the OVL threshold becomes (0.8 − 0.2) x 4 =
2.4 V. When the maximum peak current situation is lifted,
Figure 75.
lasts less than the fault timer elapses, the feedback returns to
its regulation level and resets the timer.
In the second case, the overload occurs after regulation but
the feedback voltage quickly jumps into the short−circuit
area. At this point, the countdown is accelerated as the
charging slope changed to a steeper one. The load goes back
to an OVL mode and the counter slows down. Finally, back
to short circuit again and the timer trips the fault circuitry
after completion: all pulses are immediately stopped.
When the feedback voltage exits a fault region before time
completion, the timer is reset. On the contrary, if the timer
elapses, the part enters an auto−recovery hiccup or latches
off depending on the operated version.
In the first case, the feedback is pushed to the maximum
upon start−up. The timer starts with a charging slope of the
short−circuit condition (SC). As soon as regulation occurs,
the timer gets reset. An overload occurs shortly after (OVL).
The internal timer immediately starts to count when the
3.2 V level is crossed (VFB with no OPP). As the overload
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NCP1249A, NCP1249B
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
2X
0.10 C A-B
D
D
A
0.20 C
2X
4 TIPS
F
0.10 C A-B
10
6
H
E
1
5
0.20 C
9X
B
5 TIPS
L2
b
0.25
A3
L
C
DETAIL A
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
C A-B D
M
TOP VIEW
9X
h
X 45 _
0.10 C
0.10 C
M
A
A1
e
C
SIDE VIEW
DETAIL A
SEATING
PLANE
END VIEW
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
9X
1.00
PITCH
0.58
6.50
9X
1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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http://onsemi.com
31
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For additional information, please contact your local
Sales Representative
NCP1249A/D