NCP1562A D

NCP1562A, NCP1562B
High Performance Active
Clamp/Reset PWM Controller
The NCP1562x is a family of voltage mode controllers designed
for dc-- dc converters requiring high-- efficiency and low parts count.
These controllers incorporate two in phase outputs with an overlap
delay to prevent simultaneous conduction and facilitates soft
switching. The main output is designed for driving a forward
converter primary MOSFET. The secondary output is designed for
driving an active clamp circuit MOSFET, a synchronous rectifier on
the secondary side, or an asymmetric half bridge circuit.
The NCP1562 family reduces component count and system size by
incorporating high accuracy on critical specifications such as
maximum duty cycle limit, undervoltage detector and overcurrent
threshold. Two distinctive features of the NCP1562 are soft-- stop and
a cycle skip current limit with a time threshold. Soft-- stop circuitry
powers down the converter in a controlled manner if a severe fault is
detected. The cycle skip detector enables a soft-- stop sequence if a
continuous overcurrent condition is present.
Additional features found in the NCP1562 include line feed-forward, frequency synchronization up to 1.0 MHz, cycle-- by-- cycle
current limit with leading edge blanking (LEB), independent under
and overvoltage detectors, adjustable output overlap delay,
programmable maximum duty cycle, internal startup circuit and
soft-- start.
Features















Dual Control Outputs with Adjustable Overlap Delay
>2.0 A Output Drive Capability
Soft-- Stop Powers Down Converter in a Controlled Manner
Cycle-- by-- Cycle Current Limit
Cycle Skip Initiated if Continuous Current Limit Condition Exists
Voltage Mode Operation with Input Voltage Feedforward
Fixed Frequency Operation up to 1.0 MHz
Bidirectional Frequency Synchronization
Independent Line Undervoltage and Overvoltage Detectors
Accurate Programmable Maximum Duty Cycle Limit
Programmable Maximum Volt-- Second Product
Programmable Soft-- Start
Internal 100 V Startup Circuit
Precision 5.0 V Reference
These are Pb-- Free Devices
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MARKING
DIAGRAMS
NCP
562x
ALYWG
G
TSSOP-- 16
DT SUFFIX
CASE 948F
16
1
SO-- 16
D SUFFIX
CASE 751B
x
A
WL, L
Y
WW, W
G or G
NCP1562xG
AWLYWW
= Current Limit (A, B)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb--Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 24 of this data sheet.
Typical Applications
 Telecommunications Power Converters
 Low Output Voltage Converters using Control Driven Synchronous
Rectifier
 Industrial Power Converters
 42 V Automotive System
 ATX Power Supplies
 Semiconductor Components Industries, LLC, 2010
November, 2010 - Rev. 5
1
Publication Order Number:
NCP1562A/D
NCP1562A, NCP1562B
1
Vin
16
CAUX
Istart
VAUX
Disable
VAUX(on)
Iinhibit
VAUX
+
+
--
+
Central
Logic
Vin
R1
Thermal
Shutdown
2
UVOV
R2
VUV
UVOV
Detector
RT
2V
CT
6
Oscillator
DMAX
SYNC
RTCT
Clock
VREF
SYNC
+
ICSKIP(C)
--
CSKIP
Control
Logic
CSKIP
ICSKIP(D)
+
--
0.2 V = A ver.
(0.5 V = B ver.)
+
Delay
Logic
13
OUT2
+
-
VCSKIP
PGND
VAUX
11
Saturation
Comparator
tD
+
--
Not
Saturated
3.6 V
RD
VREF
20 kΩ
9
+
VX
PWM
Comparator
VEA
270 kΩ
OUT
Not
Saturated
Clock
14
FF Reset
+
-
Clock
Ilimit
Comparator
4
CS
VAUX
OUT1
S
Q
Dominant
Reset
Latch
Q
R
CSKIP
Comparator
7
12
CCSKIP
Enable_Output
15
Vref
3V
Soft--Stop
Complete
STOP
Clock
500 mA
VREF
S
Dominant
Reset Q
Latch
R
--
VAUX(on)/
VAUX(off1)/
VAUX(off2)
5.0 V Reference
Disable_VREF
One Shot
Pulse
1V
8
P.O.R.
Bias
+
Fixed 80 ns LEB
- +
Soft--Start
Comparator
Enable
Soft--Stop
Complete
VREF
10
CSS
ISS(C)
SS
ISS(D)
Soft--Start
Soft--Stop
Control Logic
Vin
FF
Comparator
STOP
VX
Soft--Start
Complete
+
- +
--
3
+
3V
FF
--
Enable_Output
RFF
0.2 V
FF Reset
5
GND
Figure 1. Detailed Block Diagram
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2
CFF
NCP1562A, NCP1562B
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
1
Vin
Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant
current source supplies current from this pin to the capacitor connected to the VAUX pin, eliminating the
need for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 100 V.
2
UVOV
Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used
for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).
The minimum and maximum input supply voltage thresholds are adjusted independently. A UV
condition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage
exceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain 3% accuracy
allowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis.
3
FF
An external R--C divider from the input line generates the Feedforward Ramp. This ramp is used by the
PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown
transistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively
grounded until the next cycle begins.
4
CS
Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0.5 V in the NCP1562B) the converter
operates in cycle--by--cycle current limit. Once a current limit pulse is detected, the cycle skip timer is
enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation.
The leading edge blanking is disabled during soft--start and output overload conditions to improve the
response to faults.
5
GND
Control circuit ground. All control and timing components that connect to GND should have the shortest
loop possible to this pin to improve noise immunity.
6
RTCT
An external RT--CT divider from VREF sets the operating frequency and maximum duty cycle of OUT1.
The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is
generated by sequentially charging and discharging CT. The peak and valley of the Ramp are
accurately controlled to provide precise control of the duty cycle and frequency. The outputs are
disabled during the CT discharge time.
7
SYNC
Proprietary bidirectional frequency synchronization architecture allows two NCP1562 devices to
synchronize together. The lower frequency device becomes the slave. It can also synchronize to an
external signal.
8
VREF
Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference
with a capacitor. The recommended capacitance range is between 0.047 mF and 1.0 mF.
9
VEA
The error signal from an external error amplifier is fed to this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM
Comparator inverting input. An internal pullup resistor allows direct connection to an optocoupler.
10
SS
A 10 mA current source charges the external capacitor connected to this pin. Duty cycle is limited
during startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state
conditions, the SS voltage is approximately 3.8 V. Once a UV, OV, overtemperature or cycle skip fault
is detected, the SS capacitor is discharged in a controlled manner with a 100 mA current source. The
duty cycle is then slowly reduced until reaching 0%.
11
tD
An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2
transitions.
12
CSKIP
The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault
and the time the converter is disabled are programmed by the capacitor (CCSKIP) connected to this pin.
The cycle skip timer is enabled after a current limit fault is detected. Once enabled, CCSKIP is charged
with a 100 mA source. If the overcurrent fault is removed before entering the soft--stop mode, the
capacitor is discharged with a 10 mA source. Once CCSKIP reaches 3.0 V, the converter enters a
soft--stop mode and CCSKIP is discharged with a 10 mA source. The converter is re--enabled once
CCSKIP reaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, CCSKIP
discharges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation.
13
OUT2
Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a
synchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay
against OUT1. OUT2 has source and sink resistances of 12 Ω (typ.). OUT2 is designed to handle up
to 1.0 A.
14
PGND
Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.
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3
NCP1562A, NCP1562B
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
Description
15
OUT1
Main output of the PWM Controller. OUT1 has a source resistance of 4.0 Ω (typ.) and a sink resistance
of 2.5 Ω (typ.). OUT1 is designed to handle up to 2.5 A. OUT1 trails OUT2 during a low to high
transition and leads OUT2 during a high to low transition.
16
VAUX
Positive input supply. This pin connects to an external capacitor for energy storage. An internal current
source supplies current from Vin to this pin. Once the voltage on VAUX reaches approximately 10.3 V,
the current source turns OFF and the outputs are enabled. It turns ON again once VAUX falls to 8.0 V. If
the bias current consumption exceeds the startup current, VAUX will continue to discharge. Once VAUX
reaches 7.0 V, the outputs are disabled allowing VAUX to charge. During normal operation, power is
supplied to the IC via this pin by means of an auxiliary winding. The startup circuit is disabled once the
voltage on the VAUX pin exceeds 10.3 V. If the VAUX voltage drops below 1.2 V (typ), the startup
current is reduced to 200 mA.
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4
NCP1562A, NCP1562B
MAXIMUM RATINGS (Notes 1 and 2)
Symbol
Value
Unit
Vin
100
V
VAUX, Voutx
20
V
All Other Inputs/Outputs Voltage
VIO
10
V
All Other Inputs/Outputs Current
IIO
5.0
mA
5.0 V Reference Output Current
IREF
10
mA
5.0 V Reference Output Voltage
VREF
--0.3 to 6.0
V
OUT1 Peak Output Current (D = 2%)
Iout1
2.5
A
OUT2 Peak Output Current (D = 2%)
Iout2
1.0
A
TJ
–40 to +125
_C
Storage Temperature Range
Tstg
–55 to +150
_C
Power Dissipation (TA = 25_C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)
DT Suffix, Plastic Package Case 948F (TSSOP--16)
D Suffix, Plastic Package Case 751B (SO--16)
PD
Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)
DT Suffix, Plastic Package Case 948F (TSSOP--16)
0.36 Sq In
1.0 Sq In
D Suffix, Plastic Package Case 751B (SO--16)
0.36 Sq In
1.0 Sq In
RθJA
Rating
Line Voltage
Auxiliary Supply, OUT1, OUT2
Operating Junction Temperature
W
0.75
0.95
_C/W
155
133
120
105
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 2--16:
Human Body Model 2000 V per MIL–STD–883, Method 3015.
Machine Model Method 160 V.
Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 100 V.
2. This device contains Latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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5
NCP1562A, NCP1562B
ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V, VCS = 0 V, VSS = open,
RT = 13.3 kΩ, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF, RD = 25 kΩ, RSYNC = 5.0 kΩ,
CREF = 0.1 mF, RFF = 29.4 kΩ, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is – 40C to 125C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Vinhibit
VAUX(on)
VAUX(off1)
VAUX(off2)
–
9.65
7.42
6.50
1.15
10.3
8.0
7.0
1.5
10.97
8.48
7.42
–
–
23.2
Unit
STARTUP CONTROL AND VAUX REGULATOR
VAUX Regulation (VUVOV = 0 V)
Inhibit Threshold Voltage
Startup Threshold/VAUX Regulation Peak (VAUX Increasing)
Operating VAUX Valley Voltage
Minimum Operating VAUX Valley Voltage after Turn--On
(VUVOV = 2.3 V, VEA = 0 V)
V
Minimum Startup Voltage (Pin 1)
IAUX = 1.0 mA, VAUX = VAUX(on) – 0.2 V
Vstart(min)
V
Inhibit Bias Current
VAUX = 0 V
Iinhibit
70
170
300
Startup Circuit Output Current
VAUX = Vinhibit + 0.2 V
VAUX = VAUX(on) – 0.2 V
Istart1
Istart2
7.16
4.03
9.3
6.1
11.3
8.1
–
–
25
–
50
100
100
–
–
mA
mA
Startup Circuit Off--State Leakage Current (Vin = 200 V, VUVOV = 0 V)
TJ = 25_C
TJ = –40_C to 125_C
Istart(off)
Startup Circuit Breakdown Voltage (Note 3)
Istart(off) = 50 mA, TJ = 125_C
VBR(DS)
Auxiliary Supply Current after VAUX Turn--On
Outputs Disabled
VUVOV = 0 V
VEA = 0 V
Outputs Enabled
VEA = 4.0 V
mA
V
mA
IAUX1
IAUX2
–
–
3.0
4.2
3.6
4.94
IAUX3
–
5.5
7.0
VUV
1.979
2.05
2.116
V
VUV(H)
0.074
0.093
0.118
V
VUV(ratio)
3.65
4.50
5.62
%
VOV
2.80
2.95
3.10
V
LINE UNDER/OVERVOLTAGE DETECTOR
Undervoltage Threshold (Vin Increasing)
Undervoltage Hysteresis
Undervoltage Ratio (VUV(H)/VUV)
Overvoltage Threshold (Vin Increasing)
Overvoltage Hysteresis
VOV(H)
0.075
0.093
0.127
V
Offset Current (VUVOV = 2.8 V)
Ioffset(UVOV)
38
48
58
mA
Offset Current Turn ON Threshold (5%, Ioffset(UVOV) = 40 mA)
Voffset(UVOV)
2.4
2.6
2.8
V
LINE FEEDFORWARD
VFF(peak)
2.8
3.0
3.2
V
Discharge Current (VFF = 0.5 V, VSS = 0 V)
IFF(D)
8.5
–
–
mA
Offset Voltage (VFF = 0 V, Ramp Down VSS)
Voffset(FF)
0.118
0.185
0.268
V
Feedforward Offset Minus Soft--Stop Reset Voltage
Δ(FF--SS)
7
70
183
mV
Peak Voltage (Volt--Second Clamp)
3. Guaranteed by design only.
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NCP1562A, NCP1562B
ELECTRICAL CHARACTERISTICS (continued) (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V,
VCS = 0 V, VSS = open, RT = 13.3 kΩ, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF,
RD = 25 kΩ, RSYNC = 5.0 kΩ, CREF = 0.1 mF, RFF = 29.4 kΩ, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is – 40C to
125C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
191
472
203
495
217
512
Unit
CURRENT LIMIT AND THERMAL SHUTDOWN
Cycle–by–Cycle Threshold Voltage (Vout = 10 V)
NCP1562A
NCP1562B
VILIM
Propagation Delay to Output
(VCS = VILIM to 1.0 V, LEB Disabled, Vout = 10 V)
TJ = 25_C
TJ = –40_C to 125_C
tILIM
mV
ns
–
–
78
–
90
110
TSHDN
–
160
–
_C
TH
–
25
–
_C
Offset Voltage
VLEB(offset)
–
10
–
mV
Blanking Time
tLEB
50
80
110
ns
VLEB(dis)
4.1
–
–
V
Charge Current (VCSKIP = 1.25 V)
ICSKIP(C)
70
90
111
mA
Discharge Current (VCSKIP = 1.25 V)
ICSKIP(D)
6.5
8.6
11
mA
Thermal Shutdown Threshold (Junction Temperature Increasing, Note 4)
Thermal Shutdown Hysteresis (Temperature Decreasing, Note 4)
LEADING EDGE BLANKING
VEA Threshold the Disables LEB (Measured together with tLEB)
CYCLE SKIP CURRENT LIMIT MODE
Number of Pulses to Exit Cycle Skip Mode
PulseCSKIP
–
3
–
--
Upper Threshold Voltage (Ramp up VCSKIP, VCS = 1.0 V)
VCSKIP(peak)
2.83
3.03
3.24
V
Lower Threshold Voltage (Ramp down VCSKIP)
VCSKIP(valley)
0.39
0.465
0.52
V
VCSKIP(H)
–
2.5
–
V
VREF
4.9
5.0
5.1
V
Load Regulation (IREF = 0 to 5.0 mA)
VREF(Load)
–
16
50
mV
Line Regulation (VAUX = 7.5 to 20 V, IREF = 0 mA)
VREF(line)
–
10
50
mV
IREF(D)
3.8
–
–
mA
222
211.2
246
–
272.2
277.2
Threshold Voltage Hysteresis
5.0 V REFERENCE
Output Voltage (IREF = 0 mA)
Discharge Current (VUVOV = 0 V, VREF = 2.5 V)
OSCILLATOR
fOSC
Frequency
TJ = 25_C
TJ = --40_C to 125_C
kHz
Peak Voltage
VRTCT(peak)
--
2.95
--
V
Valley Voltage
VRTCT(valley)
--
2.1
--
V
Discharge Current (VRTCT = 2.3 V)
IRTCT
--
490
--
mA
Maximum Operating Frequency (Note 4)
fMAX
1.0
–
–
MHz
D
58.5
62.0
64.7
%
DMAX
85
--
--
%
Duty Cycle (RD = 25 kΩ)
Adjustable Maximum Duty Cycle (Note 4)
4. Guaranteed by design only.
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7
NCP1562A, NCP1562B
ELECTRICAL CHARACTERISTICS (continued) (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V,
VCS = 0 V, VSS = open, RT = 13.3 kΩ, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF,
RD = 25 kΩ, RSYNC = 5.0 kΩ, CREF = 0.1 mF, RFF = 29.4 kΩ, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is – 40C to
125C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Pulse Width
tO(SYNC)
70
110
--
ns
Output Voltage High (RSYNC = ∞)
VH(SYNC)
–
4.3
–
V
Sync Threshold Voltage (Note 5)
VSYNC
3.5
–
–
V
Sync Input Pulse Width (VSYNC = 3.5 V)
tSYNC
--
–
tO(SYNC)min
ns
Maximum Sync Frequency (Note 5)
fSYNC
–
–
1.0
MHz
ISYNC(D)
–
1.0
–
mA
Charge Current (VSS = 1.6 V)
ISS(C)
8.3
10.2
13.1
mA
Discharge Current (VUVOV = 0 V, VSS = 1.6 V)
ISS(D)
72
95
115
mA
Vreset(SS)
–
115
--
mV
tD(leading)
tD(trailing)
37
72
45
90
---
VOL
VOH
–
11.8
–
–
0.25
–
SYNCHRONIZATION
Source Current (Note 5)
SOFT-- START/STOP
Soft--Stop Reset Voltage (VFF = 0 V)
OUTPUTS
ns
Overlap Time Delay (Tested at 50% of Waveform)
Leading
Trailing
Output Voltage (IOUT = 0 mA, Note 5)
Low State
High State
V
Drive Resistance (FT ONLY)
OUT1 Sink (VRTCT = 4.0 V, Vout1 = 1.0 V)
TJ = 25_C
TJ = –40_C to 125_C
OUT1 Source (VRTCT = 2.5 V, Vout1 = 11 V)
TJ = 25_C
TJ = –40_C to 125_C
OUT2 Sink (VRTCT = 4.0 V, Vout2 = 1.0 V)
TJ = 25_C
TJ = –40_C to 125_C
OUT2 Source (VRTCT = 2.5 V, Vout2 = 11 V)
TJ = 25_C
TJ = –40_C to 125_C
Ω
RSNK1
RSRC1
RSNK2
RSRC2
–
–
2.8
–
3.6
5.03
–
–
4.7
–
5.75
7.45
–
–
11.4
–
12.7
20.0
–
–
11.6
–
13.5
20.0
Rise Time (10% to 90%, Cout1 = 2200 pF, Cout2 = 220 pF)
OUT1
OUT2
tr1
tr2
–
–
26
19
–
–
ns
Fall Time (90% to 10%, Cout1 = 2200 pF, Cout2 = 220 pF)
OUT1
OUT2
tf1
tf2
–
–
10
10
–
–
RIN(VEA)
11
25
58
Lower Input Threshold
VEA(L)
0.48
0.83
1.04
V
Delay to Output (From VOH to 0.5 VOH)
tPWM
–
100
–
ns
ns
PWM COMPARATOR
Input Resistance
5. Guaranteed by design only.
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8
kΩ
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
--50
--25
0
25
50
75
100
125
150
VAUX, AUXILIARY SUPPLY VOLTAGE (V)
Vinhibit, INHIBIT THRESHOLD VOLTAGE (V)
NCP1562A, NCP1562B
11.0
10.0
9.5
9.0
8.5
VAUX(off1)
8.0
7.5
VAUX(off2)
7.0
6.5
6.0
--50
--25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 2. Startup Circuit Inhibit Voltage Threshold
vs. Junction Temperature
Figure 3. Auxiliary Supply Voltage Thresholds
vs. Junction Temperature
12
10
11
Istart, STARTUP CURRENT (mA)
Vin = 48 V
VAUX = Vinhibit + 0.2 V
10
9
8
7
VAUX = VAUX(on) -- 0.2 V
6
5
4
3
2
--50
--25
0
25
50
75
100
125
150
Vin = 48 V
TJ = 25C
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (C)
VAUX, SUPPLY VOLTAGE (V)
Figure 4. Startup Current vs. Junction Temperature
Figure 5. Startup Current vs. Supply Voltage
100
Istart(off), STARTUP CIRCUIT LEAKAGE
CURRENT (mA)
Istart, STARTUP CURRENT (mA)
VAUX(on)
10.5
90
VAUX = 12 V
80
70
60
50
TJ = --40C
40
30
TJ = 25C
20
TJ = 125C
10
0
0
25
50
75
100
125
150
175
Vin, INPUT VOLTAGE (V)
Figure 6. Startup Circuit Leakage Current
vs. Input Voltage
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9
200
12
VAUX = 12 V
8
7
6
VUVOV = 2.3 V, Cout1 = Cout2 = 100 pF
5
VUVOV = 2.3 V, VEA = 0 V
4
3
VUVOV = 0 V
2
--25
0
25
50
75
100
125
150
7.0
6.5
6.0
5.5
5.0
4.0
3.5
3.0
10
11
12
13
14
15
16
17
18
19
20
VAUX, POWER SUPPLY VOLTAGE (V)
Figure 7. Auxiliary Supply Current
vs. Junction Temperature
Figure 8. Supply Current vs. Supply Voltage
3.1
3.0
2.9
2.8
OVERVOLTAGE
2.7
2.6
2.5
2.4
2.3
UNDERVOLTAGE
--25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
150
140
130
120
OVERVOLTAGE
110
100
90
UNDERVOLTAGE
80
70
60
50
--50
--25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 10. Line Under/Overvoltage Hysteresis
vs. Junction Temperature
Figure 9. Line Under/Overvoltage Thresholds
vs. Junction Temperature
50
75
70
VAUX = 12 V
VUVOV = 2.8 V
65
60
55
50
45
40
35
30
25
--50
Vin = 48 V
TJ = 25C
fOSC ≈ 230 kHz
Cout1 = Cout2 = 100 pF
4.5
TJ, JUNCTION TEMPERATURE (C)
3.2
2.2
2.1
2.0
--50
7.5
VUV/OV(H), UNDER/OVERVOLTAGE HYSTERESIS (mV)
1
0
--50
IFF(D), DISCHARGE CURRENT (mA)
Ioffset(UVOV), UVOV OFFSET CURRENT (mA)
9
8.0
IAUX3, POWER SUPPLY CURRENT (mA)
10
VUV/OV, LINE UNDER/OVERVOLTAGE THRESHOLDS (V)
IAUX, AUXILIARY SUPPLY CURRENT (mA)
NCP1562A, NCP1562B
--25
0
25
50
75
100
125
150
VCC = 12 V
VSS = 0 V
VFF = 0.5 V
45
40
35
30
25
20
15
10
5
0
--50
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. UVOV Offset Current
vs. Junction Temperature
Figure 12. FF Discharge Current
vs. Junction Temperature
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10
125
150
NCP1562A, NCP1562B
3.5
225
VFF(peak), FF PEAK VOLTAGE (V)
Voffset(FF)/Vreset(SS), FF OFFSET AND
SS RESET VOLTAGES (mV)
250
FF--Offset
200
175
150
SS Reset
125
100
75
50
25
0
--50
--25
0
25
50
75
100
125
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
--50
150
--25
TJ, JUNCTION TEMPERATURE (C)
tILIM, CURRENT LIMIT PROPAGATION DELAY (ns)
NCP1562B
450
400
350
300
250
NCP1562A
200
150
--50
--25
0
25
50
75
100
25
125
150
TJ, JUNCTION TEMPERATURE (C)
125
150
130
120
110
100
90
80
70
60
50
--50
--25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 16. Current Limit Propagation Delay
vs. Junction Temperature
90
80
70
60
50
40
30
20
0
100
140
100
--25
75
150
Figure 15. Current Limit Threshold Voltage
vs. Junction Temperature
10
0
--50
50
Figure 14. Feedforward Peak Voltage
vs. Junction Temperature
550
tLEB, LEB TIME (ns)
VILIM, CURRENT LIMIT THRESHOLD VOLTAGE (mV)
Figure 13. FF Offset and SS Reset Voltages
vs. Junction Temperature
500
0
TJ, JUNCTION TEMPERATURE (C)
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
Figure 17. Leading Edge Blanking Time
vs. Junction Temperature
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150
ICSKIP(D), CYCLE SKIP DISCHARGE CURRENT (mA)
ICSKIP(C), CYCLE SKIP CHARGE CURRENT (mA)
NCP1562A, NCP1562B
150
140
VCSKIP = 1.25 V
130
120
110
100
90
80
70
60
50
--50
--25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
15
13
12
11
10
9
8
7
6
5
--50
3.4
0.9
3.3
0.8
3.2
0.7
3.1
0.6
UPPER THRESHOLD
0.5
3.0
LOWER THRESHOLD
0.4
2.8
0.3
2.7
0.2
2.6
2.5
--50
0.1
25
50
75
100
125
0
150
7
6
5
4
3
VCC = 12 V
VUVOV = 0 V
VREF = 2.5 V
50
75
100
150
5.15
5.10
5.05
VREF = 0 mA
5.00
VREF = 5 mA
4.95
4.90
4.85
4.80
4.75
--50
fOSC, OSCILLATOR FREQUENCY (kHz)
IREF(D), VREF DISCHARGE CURRENT (mA)
8
25
125
--25
0
25
50
75
100
125 150
Figure 21. Reference Voltage
vs. Junction Temperature
9
0
100
TJ, JUNCTION TEMPERATURE (C)
10
--25
75
VAUX = 12 V
Figure 20. Cycle Skip Voltage Thresholds
vs. Junction Temperature
1
0
--50
50
5.20
TJ, JUNCTION TEMPERATURE (C)
2
25
5.25
VCSKIP(valley), LOWER THRESHOLD (V)
VREF, REFERENCE VOLTAGE (V)
VCSKIP(peak), UPPER THRESHOLD (V)
1.0
0
0
Figure 19. Cycle Skip Discharge Current
vs. Junction Temperature
3.5
--25
--25
TJ, JUNCTION TEMPERATURE (C)
Figure 18. Cycle Skip Charge Current
vs. Junction Temperature
2.9
VCSKIP = 1.25 V
14
125
150
750
700
CT = 150 pF
650
VAUX = 12 V
RT = 14 kΩ
RD = 69.8 kΩ
600
550
CT = 220 pF
500
450
400
350
300
250
200
--50
TJ, JUNCTION TEMPERATURE (C)
CT = 470 pF
--25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)
Figure 22. VREF Discharge Current
vs. Junction Temperature
Figure 23. Oscillator Frequency
vs. Junction Temperature
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12
125
150
90
900
85
VAUX = 12 V
TJ = 25C
700
80
CT = 150 pF
600
500
CT = 220 pF
400
CT = 470 pF
300
200
75
CT = 220 pF
70
65
CT = 150 pF
60
55
VAUX = 12 V
TJ = 25C
RD = 69.8 kΩ
50
100
45
CT = 470 pF
0
10
30
50
70
90
RT, TIMING RESISTOR (kΩ)
40
110
10
30
50
Figure 24. Oscillator Frequency
vs. Timing Resistor
80
ISS(C), CHARGE CURRENT (mA)
D, DUTY CYCLE (%)
110
150
15
VAUX = 12 V
RD = 69.8 kΩ
85
75
70
RT = 20 kΩ, CT = 150 pF
65
RT = 15.8 kΩ, CT = 220 pF
60
RT = 11.8 kΩ, CT = 470 pF
55
50
45
40
--50
--25
0
25
50
75
100
125
14
13
130
12
120
11
100
DISCHARGE (VUVOV = 0 V)
9
80
7
70
6
5
--50
150
--25
400
350
TRAILING
250
LEADING
150
VAUX = 12 V
TJ = 25C
80
160
240
320
RD, DELAY RESISTOR (kΩ)
tD, OVERLAP TIME DELAY (ns)
350
0
25
50
75
100
125
Figure 27. Soft--Start/Stop Charge and Discharge
Currents vs. Junction Temperature
450
50
0
60
50
150
TJ, JUNCTION TEMPERATURE (C)
400
100
90
8
500
200
110
CHARGE
10
Figure 26. Duty Cycle
vs. Junction Temperature
300
140
VAUX = 12 V
TJ, JUNCTION TEMPERATURE (C)
tD, OVERLAP TIME DELAY (ns)
90
Figure 25. Duty Cycle
vs. Timing Resistor
90
0
70
RT, TIMING RESISTOR (kΩ )
ISS(D), DISCHARGE CURRENT (mA)
800
D, DUTY CYCLE (%)
fOSC, OSCILLATOR FREQUENCY (kHz)
NCP1562A, NCP1562B
VAUX = 12 V
RD = 200 kΩ
300
tD(lead)
250
200
tD(trail)
150
tD(lead)
100
tD(trail)
50
0
--50
400
tD(trail)
RD = 69.8 kΩ
RD = 20 kΩ
tD(lead)
--25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
Figure 29. Overlap Time Delay
vs. Junction Temperature
Figure 28. Overlap Time Delay
vs. Delay Resistor
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150
RSNK/SRC, OUTPUT 2 DRIVE RESISTANCE (Ω)
RSNK/SRC, OUTPUT 1 DRIVE RESISTANCE (Ω)
NCP1562A, NCP1562B
10
9
VAUX = 12 V
8
7
6
5
SOURCE, Vout1 = 11 V
4
3
SINK, Vout1 = 1 V
2
1
0
--50
--25
0
25
50
75
100
125
150
18
17
VAUX = 12 V
16
15
14
13
SOURCE, Vout2 = 11 V
12
11
10
SINK, Vout2 = 1 V
9
8
7
6
--50
--25
TJ, JUNCTION TEMPERATURE (C)
50
75
100
125
150
Figure 31. Output 2 Drive Resistance
vs. Junction Temperature
1.5
50
45
VEA = 0 V
40
35
30
25
20
15
10
5
--25
0
25
50
75
100
125
VEA(L), PWM COMPARATOR LOWER
INPUT THRESHOLD (V)
RIN(VEA), VEA INPUT RESISTANCE (kΩ)
25
TJ, JUNCTION TEMPERATURE (C)
Figure 30. Output 1 Drive Resistance
vs. Junction Temperature
0
--50
0
150
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
--50
--25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 32. VEA Input Resistance
vs. Junction Temperature
Figure 33. PWM Comparator Lower Input Threshold
vs. Junction Temperature
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NCP1562A, NCP1562B
DETAILED OPERATING DESCRIPTION
The NCP1562x is a family of voltage mode controllers
designed for dc-- dc converters requiring high-- efficiency
and low parts count. These controllers incorporate two in
phase outputs with an adjustable overlap delay. The main
output is designed for driving a forward converter primary
MOSFET. The secondary output is designed for driving an
active clamp circuit MOSFET, a synchronous rectifier on
the secondary side, or an asymmetric half bridge circuit.
Two distinctive features of the NCP1562 are the
soft-- stop and a cycle skip overcurrent detector with a time
threshold. The soft-- stop powers down the converter in a
controlled manner after a fault is detected. The cycle skip
timer disables the converter if a continuous overcurrent
condition is present.
The NCP1562 reduces component count and system size
by incorporating high accuracy on critical specifications
such as programmable maximum duty cycle, undervoltage
detector and overcurrent threshold. Additional features
found in the NCP1562 include line feedforward,
bidirectional frequency synchronization up to 1.0 MHz,
cycle-- by-- cycle current limit with leading edge blanking
(LEB), independent under and overvoltage detectors,
internal startup circuit and soft-- start.
current does not exceed 100 mA. Otherwise the converter
will not be able to complete a soft-- stop sequence.
Depending on the converter state, a soft-- stop sequence
is handled differently to ensure the fastest response time
and prevent system malfunction. If a soft-- stop sequence
starts before VSS exceeds the maximum voltage clamp of
the FF Ramp (typ. 3.0 V) and the PWM Comparator (VEA)
is not yet controlling the duty cycle, a controlled discharge
of CSS commences immediately, as shown in Figure 34.
However, if VEA is controlling the duty cycle, CSS is
discharged until soft-- stop sets a duty cycle equal to the duty
cycle set by VEA. A controlled discharge commences
afterwards, as shown in Figure 35. If VSS exceeds the FF
Ramp and the VEA is not controlling the duty cycle, VSS is
forced to the peak voltage of the FF Ramp, before starting
a controlled discharge of CSS, as shown in Figure 36. The
duty cycle set at the beginning of the soft-- stop event never
exceeds the duty cycle prior to the soft-- stop event.
(VEA is not controlling the duty cycle)
VEA
SOFT--STOP AND SOFT--START
The NCP1562 incorporates a novel soft-- stop and
soft-- start architecture that combines soft-- start and
soft-- stop functions on a single pin.
Soft-- stop reduces the duty cycle until it reaches 0% once
a fault is detected. By slowly reducing the duty cycle during
power down, the active clamp capacitor (Cclamp) is
discharged. This prevents oscillations between the power
transformer and Cclamp, and ensures the converter turns off
in a predictable state.
Soft-- start slowly increases the duty cycle during power
up allowing the controller to gradually reach steady state
operation. Combined, both features reduce system stress
and power surges.
The duty cycle is controlled by comparing the SS
capacitor voltage (VSS) to the Feedforward (FF) Ramp.
Soft-- start or soft-- stop is implemented by slowly charging
or discharging the capacitor on the SS pin. OUT1 is
disabled once the FF Ramp exceeds VSS. The soft-- start
charge current is 10 mA and the soft-- stop discharge current
is 100 mA, guaranteeing a faster turn OFF time.
The converter enters a soft-- stop sequence if an
undervoltage, overvoltage, cycle skip or thermal shutdown
condition is detected. Once the converter enters the
soft-- stop mode, it will stay in soft-- stop mode until VSS
reaches 0.2 V even if the fault is removed prior to reaching
0.2 V.
The preset 1:10 charge:discharge ratio can be reduced by
placing an external resistor between the VREF and SS pins.
The resistor should be sized such that the total charge
VSS
FF Ramp
Figure 34. Soft--Stop Before Soft--Start
is Complete and VEA is Open.
VSS
VEA
VX = VEA -- Vf
Figure 35. Soft--Stop Behavior when VEA
Controls the Duty Cycle.
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15
NCP1562A, NCP1562B
Cycle Skip
Traditionally, a voltage on the CS higher than VILIM has
been used to trigger a cycle skip fault. Unfortunately, the
fast response time of modern controllers makes it hard to
reach a voltage on the CS pin higher than VILIM.
Instead of using a higher voltage threshold to detect a
cycle skip fault, the NCP1562 uses a timer. It monitors the
current limit comparator and if a continuous
cycle-- by-- cycle current limit condition exists the converter
is disabled. The time to disable the converter and the time
the converter is disabled are programmed by the capacitor
on the CSKIP pin, CCSKIP.
The cycle skip detection circuit charges CCSKIP with a
continuous 100 mA current once cycle-- by-- cycle current
limit fault is detected. If the current limit fault persists,
CCSKIP continues to charge until reaching the cycle skip
upper threshold (VCSKIP(peak)) of 3.0 V. Once reached, the
converter enters the soft–stop mode and CCSKIP is
discharged with a constant 10 mA current. A new soft-- start
sequence commences once CCSKIP reaches the lower cycle
skip threshold (VCSKIP(valley)) of 0.5 V. If the overcurrent
condition is still present, the capacitor starts charging on
the next current limit event. Otherwise, CCSKIP is
discharged down to 0 V.
The cycle skip capacitor provides a means of
remembering previous overcurrent conditions. If a
continuous overcurrent condition is removed before
reaching VCSKIP(peak), CCSKIP starts a controlled
discharge. If the continuous overcurrent fault is once again
detected before CCSKIP is completely discharged, CCSKIP
charges from its existing voltage level, taking less time to
reach VCSKIP(peak). Figure 37 shows operating waveforms
during a continuous overcurrent condition. For optimal
operation, the cycle skip discharge time should be longer
than the soft-- stop period.
(VEA is not controlling the duty cycle)
VEA
VSS
FF Ramp
Figure 36. Soft--Stop Behavior After Soft--Start
is Complete and VEA is Open.
If the voltage on the VAUX pin reaches VAUX(off2), CSS is
immediately discharged and the outputs are disabled. VSS
should not be pulled up or down externally.
CURRENT LIMIT
The NCP1562 has two overcurrent modes,
cycle-- by-- cycle and cycle skip, providing the best
protection during momentary and continuous overcurrent
conditions.
Cycle--by--Cycle
In cycle-- by-- cycle, the conduction period ends once the
voltage on the CS pin reaches the current limit voltage
threshold (VILIM). The NCP1562A has a VILIM of 0.2 V
and the NCP1562B has a VILIM of 0.5 V.
VILIM
CS
VCSKIP(peak)
VCSKIP
VCSKIP(valley)
VSS
Figure 37. Cycle Skip Waveforms
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NCP1562A, NCP1562B
In some instances it may be desired to latch (instead of
auto re-- start) the NCP1562 after a cycle skip event is
detected. This can be easily achieved by adding an external
latch. Figures 35 and 36 show an implementation of an
integrated and a discrete latch, respectively. In general the
circuits work by pulling CSKIP to VREF, preventing it from
reaching VCSKIP(valley) once the CSKIP voltage reaches the
turn on threshold of the latch. The external latch is cleared
by bringing the UVOV voltage below VUV and disabling
VREF.
A latch implemented using discrete N and P-- channel
MOSFETs is shown in Figure 39. The latch is enabled once
the CSKIP voltage reaches the threshold of M1. Once M1
turns on, it pulls low the gate of M2. CSKIP is then pulled
to VREF by M2. It is important to size Rpull--up correctly. If
Rpull--up is too big, it will not keep M2 off while VREF
charges. This will cause the controller to latch during initial
power-- up. In this particular implementation the turn on
threshold of M1 is 2 V and Rpull--up is sized to 24.9 k.
Leading Edge Blanking
The current sense signal is prone to leading edge spikes
caused by the power switch transitions. The current signal
is usually filtered using an RC low–pass filter to avoid
premature triggering of the current limit circuit. However,
the low pass filter will inevitably change the shape of the
current pulse and also add cost and complexity. The
NCP1562 uses LEB circuitry that blocks out the first 70 ns
(typ) of each current pulse. This removes the leading edge
spikes without altering the current waveform. The blanking
period is disabled during soft-- start as the blanking period
may be longer than the startup duty cycle. It is also disabled
if the output of the Saturation Comparator is low, indicating
that the output is not yet in regulation. This occurs during
power up or during an output overload condition.
VREF
VCC
CREF
OUTY
CSKIP
INA
OE
MC74VHC1GT126
CCSKIP
Figure 38. External Latch Implemented using
ON Semiconductor’s MiniGatet Buffer
The latch in Figure 38 consists of a TTL level tri-- state
output buffer from ON Semiconductor’s MiniGatet
family. The enable (OE) and output (OUTY) terminals are
connected to CSKIP and the VCC and INA pins are
connected to VREF. The output of the buffer is in a high
impedance mode when OE is low. Once a continuous
current limit condition is detected, the CSKIP timer is
enabled and CSKIP begins charging. Once the voltage on
CSKIP reaches the enable threshold of the buffer, the
output of the buffer is pulled to VREF, latching the CSKIP
timer. The OE threshold of the buffer is typically 1.5 V.
Supply Voltage and Startup Circuit
The NCP1562 internal startup regulator eliminates the
need for external startup components. In addition, this
regulator increases the efficiency of the supply as it uses no
power when in the normal mode of operation, but instead
uses power supplied by an auxiliary winding. The
NCP1562 incorporates an optimized startup circuit that
reduces the requirement of the supply capacitor,
particularly important in size constrained applications.
The startup regulator consists of a constant current
source that supplies current from the input line voltage
(Vin) to the supply capacitor on the VAUX pin (CAUX). The
startup current (Istart) is typically 10 mA.
Once CAUX is charged to 10.3 V (VAUX(on)), the startup
regulator is disabled and the outputs are enabled if there are
no UV, OV, cycle skip or thermal shutdown faults. The
startup regulator remains disabled until the lower voltage
threshold (VAUX(off1)) of 8.0 V is reached. Once reached,
the startup circuit is enabled. If the bias current requirement
out of CAUX is greater than the startup current, VAUX will
discharge until reaching the lower voltage threshold
(VAUX(off2)) of 7.0 V. Upon reaching VAUX(off2), the
outputs are disabled. Once the outputs are disabled, the bias
current of the IC is reduced, allowing VAUX to charge back
up. This mode of operation allows a dramatic reduction in
the size of CAUX as not all the power required for startup
needs to be stored by CAUX. This mode of operation is
known as Dynamic Self Supply (DSS). Figure 40 shows the
relationship between VAUX(on), VAUX(off1), VAUX(off2) and
UV. As shown in Figure 40, the outputs are not enabled
until the UV fault is removed and VAUX reaches VAUX(on).
VREF
CREF BSS84L
24.9 kΩ
Rpull--up
M2
M1
CSKIP
2N7002L
CCSKIP
Figure 39. External Latch Implemented using
Discrete N and P--Channel MOSFETs
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NCP1562A, NCP1562B
VAUX(on)
VAUX(off1)
VAUX
Vinhibit
VUVOV
VREF
VSS
Vout1
Figure 40. Startup Circuit Waveforms
The startup regulator is disabled by biasing VAUX above
VAUX(on). This feature allows the NCP1562 to operate from
an independent 12 V supply. If operating from an
independent supply, the Vin and VAUX pins should be
connected together. The independent supply should
maintain VAUX above VAUX(on). Otherwise, the Output
Latch will not be SET and the outputs will remain OFF after
a fault condition is removed.
The startup circuit sources current into the VAUX pin. It
is recommended to place a diode between CAUX and the
auxiliary supply as shown in Figure 41. This allows the
NCP1562 to charge CAUX while preventing the startup
regulator from sourcing current into the auxiliary supply.
ON. The IC bias current, gate charge load on the outputs,
and the 5.0 V reference load must be considered to
correctly size CAUX. The current consumption due to
external gate charge is calculated using Equation 1.
IAUX(gate charge) = f ⋅ QG
where, f is the operating frequency and QG is the gate
charge.
An internal supervisory circuit monitors VAUX and
prevents excessive power dissipation if the VAUX pin is
accidentally shorted. While VAUX is below 1.2 V, the
startup circuit is disabled and a current source (Iinhibit)
charges VAUX with a minimum current of 50 mA. Once
VAUX reaches 1.2 V the startup circuit is enabled.
Therefore it is imperative that VAUX is not loaded (driver,
resistor divider, etc.) with more than 50 mA while VAUX is
below 1.2 V. Otherwise, VAUX will not charge. If a load
greater than 50 mA is present, a resistor can be placed
between the Vin and VAUX pins to help charge VAUX to
1.2 V.
The startup circuit is rated at a maximum voltage of
100 V. If the device operates in the DSS mode, power
dissipation should be controlled to avoid exceeding the
maximum power dissipation of the controller. If dissipation
on the controller is excessive, a resistor can be placed in
series with the Vin pin. This will reduce power dissipation
on the controller and transfer it to the series resistor.
Auxiliary Supply or
Independent Supply
Vin
Istart
VAUX
IAUX
CAUX
(eq. 1)
Isupply
Disable
Figure 41. Recommended VAUX Configuration
CAUX provides power to the controller while operating
in the self-- bias or DSS mode. During the converter
powerup, CAUX must be sized such that a VAUX voltage
greater than VAUX(off2) is maintained while the auxiliary
supply voltage is building up. Otherwise, VAUX will
collapse and the controller will turn OFF. Also, the VAUX
discharge time (from 10.3 V to 7.0 V) must be greater that
the soft-- start charge period to assure the converter turns
Line Under/Overvoltage Detector
The same pin is used for both line undervoltage (UV) and
overvoltage (OV) detection using a novel architecture
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18
NCP1562A, NCP1562B
(patent pending). This architecture allows both the UV and
OV levels to be set independently. Both the UV and OV
detectors have a 100 mV hysteresis.
The line voltage is sampled using a resistor divider as
shown in Figure 42.
+
--
+
-
+
UVOV
CUVOV
R2
--
+
--
Vin(UV) = VUV ×
OV Comparator
VOVCOMP
Vin(OV) = VOV
+
-
(R1 + R2)
R2
(R1 + R2)
(eq. 1)
R2
+ (Ioffset(UVOV) × R1)
(eq. 2)
The undervoltage threshold is trimmed during
manufacturing to obtain 3% accuracy allowing a tighter
power stage design.
Once the line voltage is within the operating range, and
VAUX reaches VAUX(on), the outputs are enabled and a
soft-- start sequence commences. If a UV or OV fault is
detected afterwards, the converter enters a soft-- stop mode.
A small capacitor is required (>1000 pF) from the
UVOV pin to GND to prevent oscillation of the UVOV pin
and filter line transients.
3.0 V
Vin
R1
Equation 1. Once the internal current source is enabled, the
absolute value of R1 together with the ratio of R1 and R2
determine the turn OFF threshold as shown in Equation 2.
UV Comparator
VUVCOMP
2.0 V
+
2.5 V
Line Feedforward
The NCP1562 incorporates line feedforward (FF) to
limit the maximum volt-- second product. It is the line
voltage times the ON time. This limit prevent saturation of
the transformer in forward and flyback topologies. Another
advantage of feedforward is a controller frequency gain
independent of line voltage. A constant gain facilitates
frequency compensation of the converter.
Feedforward is implemented by generating a ramp
proportional to Vin and comparing it to the error signal. The
error signal solely controls the duty cycle while the input
voltage is fixed. If the line voltage changes, the FF Ramp
slope changes and duty cycle is immediately adjusted instead
of waiting for the change to propagate around the feedback
loop and be reflected back on the error signal.
The FF Ramp is generated with an R-- C (RFFCFF) divider
from the input line as shown in Figure 44. The divider is
selected such that the FF Ramp reaches 3.0 V in the desired
maximum ON time. The FF Ramp terminates by
effectively grounding CFF during the converter OFF time.
This can be triggered by the FF Ramp reaching 3.0 V, or
any other condition that limits the duty cycle.
Ioffset(UVOV)
Figure 42. Line UVOV Detectors
Vin (V)
A UV condition exists if the UVOV voltage is below
VUV, typically 2.0 V. The ratio of R1 and R2 determines the
UV turn threshold. Once the UVOV voltage exceeds 2.5 V,
an internal current source (Ioffset(UVOV)) sinks 50 mA into
the UVOV pin. This will clamp the UVOV voltage at 2.5 V
while the current across R1 is less than Ioffset(UVOV). If the
input voltage continues to increase, the 50 mA source will
be overridden and the voltage at the UVOV pin will
increase. An OV condition exists if the UVOV voltage
exceeds VOV, typically 3.0 V. Figure 43 shows the
relationship between UVOV and Vin.
VUVOV (V)
Vin
To PWM and VS
Comparators
VUVCOMP
RFF
IRFF
3V
FF
VUVOV
VOVCOMP
FF Reset
IFF(D)
0V
CFF
ton
T
Time
Figure 43. UVOV Detectors Typical Waveforms
Figure 44. Feed Forward Ramp Generation
While the internal current source is disabled, the UVOV
voltage is solely determined by the ratio of R1 and R2. The
input voltage at which the converter turns ON is given by
The FF pin is effectively grounded during power or
during standby mode to prevent the FF pin from charging
up to Vin.
http://onsemi.com
19
NCP1562A, NCP1562B
The minimum value of RFF is determined by the FF
Ramp discharge current (IFF(D)). The current through RFF
(IRFF) should be at least ten times smaller than IFF(D) for a
sharp FF Ramp transition. Equations 3 and 4 are used to
determine RFF and CFF.
Vin
≤ RFF
0.1 × IFF(D)
CFF =
ln

VAUX
(eq. 3)
Output
D
Vin
Vin --3 V
1.0 A. If a higher drive capability is required, an external
driver stage can be easily added as shown in Figure 46.
OUT1
or
OUT2
(eq. 4)
 × f × RFF
where, f is the operating frequency. It is recommended to
bias the FF circuit with enough current to provide good
noise immunity.
Figure 46. Discrete Boost Drive Stage
PWM Comparator
OUT1 drives the main MOSFET, and OUT2 drives a low
side P-- Channel active clamp MOSFET. A high side
N-- Channel active clamp MOSFET or a synchronous
rectifier can also be driven by inverting OUT2. OUT2 is
purposely sized smaller than OUT1 because the active
clamp MOSFET only sees the magnetizing current.
Therefore, a smaller active clamp MOSFET with less input
capacitance can be used compared to the main switch.
Once VAUX reaches VAUX(on) (typically 10.3 V), the
internal startup circuit is disabled and the outputs are
enabled if no faults are present. Otherwise, the outputs
remain disabled until the fault is removed and VAUX
reaches VAUX(on). The outputs are disabled after a soft-- stop
sequence if VAUX is below VAUX(on) or if VAUX reaches
7.0 V.
The outputs are biased directly from VAUX and their high
state voltage is approximately VAUX. Therefore, the
auxiliary supply voltage should not exceed the maximum
gate voltage of the main or active clamp MOSFET.
The high current drive capability of the outputs will
generate inductance-- induced spikes if inductance is not
reduced on the outputs. This can be done by reducing the
connection length between the drivers and their loads and
using wide connections.
In steady state operation, the PWM Comparator adjusts
the duty cycle by comparing the error signal to the FF
Ramp. The error signal is fed into the VEA pin. The VEA pin
can be driven directly with an optocoupler without the need
of an external pullup resistor as shown in Figure 45. In
some instances, it may be required to have a pullup resistor
smaller than the internal resistor (R4) to adjust the gain of
the isolation stage. This is easily accomplished by
connecting an external resistor (REA) in parallel with R4.
REA is connected between the VREF and VEA pins. The
effective pullup resistance is the parallel combination of
R4 and REA.
VREF
PWM
Comparator
+
0.2 V
REA (Optional)
20 kΩ
2 kΩ
VEA
Feedback
Signal
270 kΩ
+
--
FF
3V
FF Ramp
0V
Figure 45. Optocoupler Driving VEA Input
Overlap Delay
The overlap delay prevents simultaneous conduction of
the main and active clamp MOSFETs. The secondary
output, OUT2, precedes OUT1 during a low to high
transition and trails OUT1 during a high to low transition.
Figure 47 shows the relationship between OUT1 and
OUT2.
The drive of the VEA pin is simplified by internally
incorporating a series diode and resistor. The series diode
provides a 0.7 V offset between the VEA input and the
PWM Comparator inverting input. It allows reaching zero
duty cycle without the need of pulling the VEA pin all the
way to GND. The outputs are enabled if the VEA voltage is
approximately 0.5 V above the valley of the FF Ramp.
tD (Leading)
Outputs
tD (Trailing)
OUT1
The NCP1562 has two in-- phase output drivers with an
adjustable overlap delay (tD). The main output, OUT1, has
a source resistance of 4.0 Ω (typ) and a sink resistance of
2.5 Ω (typ). The secondary output, OUT2, has a source and
a sink resistance of 12 Ω (typ). OUT1 is rated at a
maximum of 2.0 A and OUT2 is rated at a maximum of
OUT2
Figure 47. Output Timing Diagram
http://onsemi.com
20
NCP1562A, NCP1562B
voltage (VRTCT(valley)), typically 2.0 V, IRTCT turns OFF
allowing CT to charge back up through RT. The resulting
waveform on the RTCT pin has a sawtooth like shape.
The output overlap delay is adjusted by connecting a
resistor, RD, from the tD pin to ground. The overlap delay
is proportional to RD. A minimum delay of 20 ns is
obtained by grounding the tD pin.
The leading delay is purposely made longer than the
trailing delay. This allows the user to optimize the delay for
the turn on transition of the main switch and ensures the
active clamp switch always exhibits zero volt switching.
VREF
RT
3V
RTCT
Analog and Power Ground (PGND)
2V
The NCP1562 has an analog ground, GND, and a power
ground, PGND, terminal. GND is used for analog
connections such as VREF, RTCT, feedforward among
others. PGND is used for high current connections such as
the internal output drivers. It is recommended to have
independent analog and power ground planes and connect
them at a single point, preferably at the ground terminal of
the system. This will prevent high current flowing on
PGND from injecting noise in GND. The PGND
connection should be as short and wide as possible to
reduce inductance-- induced spikes.
IRTCT
Enable
Figure 48. Oscillator Configuration
OUT2 is set high once VRTCT(valley) is reached, followed
by OUT1 delayed by the overlap delay. Once VRTCT(peak)
is reached, OUT1 goes low, followed by OUT2 delayed by
t D.
The duty cycle is the CT charge time (tRTCT(C)) minus the
overlap delay over the total charge and discharge (tRTCT(D))
times. The charge and discharge times are calculated using
Equations 5 and 6. However, these equations are an
approximation as they do not take into account the
propagation delays of the internal comparator.
Oscillator
The oscillator frequency and maximum duty cycle are
set by an RTCT divider from VREF as shown in Figure 48.
A 500 mA current source (IRTCT) discharges the timing
capacitor (CT) upon reaching its peak threshold
(VRTCT(peak)), typically 3.0 V. Once CT reaches its valley

VRTCT(valley)--VREF
tRTCT(C) = RTCT × ln
VRTCT(peak)--VREF

(IRTCT × RT) + VRTCT(peak)--VREF
tRTCT(D) = RTCT × ln
(IRTCT × RT) + VRTCT(valley)--VREF
The duty cycle, D, is given by Equation 7.
D=
tRTCT(C)--tD
tRTCT(C) + tRTCT(D)
D=
ln


VRTCT(peak)--VREF
VRTCT(peak)--VREF
RTCT × ln

tD
RTCT
(IRTCT×RT)+VRTCT(peak)--VREF
× (I
(eq. 5)
(eq. 6)
(eq. 8)

RTCT×RT)+VRTCT(valley)--VREF
It can be observed that D is set by RT, CT and tD. This
equation has two variables and can be solved iteratively. In
general, the time delay is a small portion of the ON time and
can be ignored as a first approximation. RT is then selected
f=
--
VRTCT(valley)--VREF
VRTCT(valley)--VREF


Substituting Equations 5, 6, and 7, and after a little
algebraic manipulation and replacing values, it simplifies
to:
(eq. 7)
ln
CT
to achieve a given duty cycle. Once the RT is selected, CT
is chosen to obtain the desired operating frequency using
Equation 9.
1
VRTCT(valley)--VREF
VRTCT(peak)--VREF
(IRTCT×RT)+VRTCT(peak)--VREF
× (I

(eq. 9)
RTCT×RT)+VRTCT(valley)--VREF
Synchronization
Figures 23 through 26 show the frequency and duty cycle
variation vs RT for several CT values. RT should not be less
than 6.0 kΩ. Otherwise, the RTCT charge current will
exceed the pulldown current and the oscillator will be in an
undefined state.
A proprietary bidirectional frequency synchronization
architecture allows multiple NCP1562 to synchronize in a
master-- slave configuration. It can synchronize to
frequencies above or below the free running frequency.
http://onsemi.com
21
NCP1562A, NCP1562B
The SYNC pin is in a high impedance mode during the
charging of the RTCT Ramp. In this period the oscillator
accepts an external SYNC pulse. If no pulse is detected
upon reaching the peak of the RTCT Ramp, a 100 ns SYNC
pulse is generated. The SYNC pulse is generated by
internally pulling the SYNC pin to VREF. The peak voltage
of the SYNC pin is typically 4.3 V. Once the 100 ns timer
expires, the pin goes back into a high impedance mode and
an external resistor is required for pulldown as shown in
Figure 49.
MASTER
CONTROLLER
SYNC
SYNC
RSYNC1
RSYNC2
SLAVE
CONTROLLER
Figure 50. Master--Slave Configuration
5.0 V Reference
The NCP1562 has a precision 5.0 V reference output. It
is a buffered version of the internal reference. The 5.0 V
reference is biased directly from VAUX and it can supply up
to 5.0 mA. Load regulation is 50 mV and line regulation is
100 mV within the specified operating range.
It is required to bypass the reference with a capacitor.
The capacitor is used for compensation of the internal
regulator and high frequency noise filtering. The capacitor
should be placed across the VREF and GND pins. In most
applications a 0.1 mF will suffice. A bigger capacitor may
be required to reduce the voltage ripple caused by the
oscillator current. The recommended capacitor range is
between 0.047 mF and 1.0 mF.
During powerup, the 5.0 V reference is enabled once
VAUX reaches VAUX(on) and a UV fault is not present.
Otherwise, the reference is enabled once the UV fault is
removed and VAUX reaches VAUX(on).
Once a UV fault is detected after the reference has been
enabled, the reference is disabled after the soft-- stop
sequence is complete if the UV fault is still present. If the
UV fault is removed before soft-- stop is complete, the
reference is not disabled.
VREF
RT
RTCT
CT
SYNC
RSYNC
Figure 49. SYNC Pulse
The slew rate of the sync pin is determined by the pin
capacitance and external pulldown resistor. The maximum
source current of the SYNC pin is 1.0 mA. The resistor is
sized to allow the SYNC pin to discharge before the start
of the next cycle.
If an external pulse is received on the SYNC pin before
the internal pulse is generated, the controller enters the
slave mode of operation. Once operation in slave mode
commences, CT begins discharging and the RTCT Ramp
upper threshold is increased to 4.0 V.
If a controller in slave mode does not receive a sync pulse
before reaching the RTCT Ramp peak voltage (4.0 V), the
upper threshold is reset back to 3.0 V and the converter
reverts to operation in master mode. To guarantee the
converter stays in slave mode, the minimum clock period
of the master controller has to be less than the RTCT charge
time from 2.0 V to 4.0 V.
Two NCP1562’s are synchronized by connecting their
SYNC pins together. The first device that generates a sync
pulse during powerup becomes the master. A diode
connected as shown in Figure 50 can be used to
permanently set one controller as the master. The diode
prevents the master from receiving the SYNC pulse of the
slave controller.
Application Information
ON Semiconductor provides an electronic design tool, a
demonstration board and an application note to facilitate
design of the NCP1562 and reduce development cycle
time. All the tools can be downloaded or ordered at
www.onsemi.com.
The electronic design tool allows the user to easily
determine most of the system parameters of an active
clamp forward converter. The tool evaluates the power and
active clamp stages as well as the frequency response of the
system. The tool is used to design a converter for a 48 V
telecom system. The converter delivers 100 W at 3.3 V.
The circuit schematic is shown in Figure 51. The converter
design is described in Application Note AND8273/D.
http://onsemi.com
22
23
Figure 51. Circuit Schematic
http://onsemi.com
270 p
R8
32.4k
C24
D1
D2-- D7
X1
X2
X3-- X6
C12
C30
R9
15 k
0.01
C16
Vref
=
=
=
=
=
2.2
2.2
2.2
R1
523 k
C3
C2
C1
L1
1.5 m
27 p
R4
32.4 k
J5
J2
+
36-- 72 V
-
J1
3
BC817
2
R11
4.22 k
1
Q1
R18
3.01 k
U1
Vin
VAUX
UVOV OUT1
PGND
FF
OUT2
CS
GND CSKIP
RTCT
tD
SS
SYNC
VREF VEA
NCP1562A
16
15
14
13
12
11
10
9
22
0.1
R6
10 k
1
2
3
4
5
6
7
8
C7
47
47
C23
MBRM120ET1G
MMSD914T1G
FDD2582
IRF6217PBF
NTMFS4835NT1G
0.1
C8
CS
470 p
R3
45.3 k
2.2
C4
C22
+
C31
+
0.1
C28
CS
1
C10
R5
44.2 k
X1
7
6T
4
4T
2
0.018
C14
D4
0.01
PS2703-- I-- M-- A
3
2200 p
C27
U2
R17
10 k
4
X2
2
1
U4B
7
1,2,3
SEC_PWR2
R2
5,6,7,8
33 m
4 C26
9
1T
8
TX1
51665
4
R16
10 k 3
100
100 p
R10
C13 0.01
C11
4.75
D1
R15
D2
1
5,6,7,8
5,6,7,8
C5
5
6
X4
X3
R23
2.0
1000 p
+
-
D7
4
4
1,2,3
1,2,3
R24
10 k
3
C15
2.2
SEC_PWR2
SEC_PWR1
D6
D3
4
4
R25
10 k
1,2,3
X6
5,6,7,8
X5
2
Q2 1
BC807
R14
953
348
R13
2.0
R29
SEC_PWR1
24.9
R26
1
49.9
C9
0.1
R12
5.9 k
3
2
4.22 k
C6 3
0.1
5
R7
4
150
8 LM258G
4
0.056
C25
47 150
D5
U4A
47
R30
348
R19
10
R28
2.49 k
R27
4.22 k
1000 p
C29
150
C17 C18 C19 +C20 +C21 +
R20
1,2,3
5,6,7,8
L2
1.5 m
+
-
L3
1000 m
R22
open
R21
16.2 k
J4
+
3.3 V
-
J3
NCP1562A, NCP1562B
NCP1562A, NCP1562B
ORDERING INFORMATION
Device
Package
Current Limit
NCP1562ADBR2G
TSSOP--16
(Pb--Free)
200 mV
NCP1562BDBR2G
TSSOP--16
(Pb--Free)
500 mV
NCP1562ADR2G
SO--16
(Pb--Free)
200 mV
NCP1562BDR2G
SO--16
(Pb--Free)
500 mV
Shipping†
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
http://onsemi.com
24
NCP1562A, NCP1562B
PACKAGE DIMENSIONS
TSSOP--16
CASE 948F--01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
S
V
S
S
K
K1
2X
L/2
16
9
J1
B
- U--
L
SECTION N-- N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
- V--
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE --W--.
N
F
DETAIL E
- W--
C
0.10 (0.004)
- T--
SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
25
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
-- -- -1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
-- -- -- 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007 0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
NCP1562A, NCP1562B
PACKAGE DIMENSIONS
SOIC--16
CASE 751B--05
ISSUE K
- A-16
9
1
8
- B--
P
8 PL
0.25 (0.010)
B
M
S
G
R
K
F
X 45 _
C
- T--
SEATING
PLANE
J
M
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0_
7_
0_
7_
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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26
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For additional information, please contact your loca
Sales Representative
NCP1562A/D