NCP1561 Push−Pull PWM Controller for 48 V Telecom Systems The NCP1561 Push−Pull PWM controller contains all the features and flexibility needed to implement high efficiency dc−dc converters using voltage or current−mode control. This device can be configured in any dual ended topology such as push−pull or half−bridge. It can also be used for forward topologies requiring a 50% maximum duty cycle. This device is ideally suited for 48 V telecom, 42 V automotive systems and 12 V input applications. The NCP1561 cost effectively reduce system part count by incorporating a high voltage start−up regulator, line undervoltage detector, single resistor oscillator setting, dual mode overcurrent protection, soft start and single resistor feedforward ramp generator. The oscillator frequency can be adjusted up to 250 kHz. http://onsemi.com MARKING DIAGRAM 16 SO−16 D SUFFIX CASE 751B 16 1 1 Features • • • • • • • • • • • • NCP1561 AWLYWW NCP1561 = Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week Internal High Voltage Start−up Regulator Minimum Operating Voltage of 21.5 V Voltage or Current−Mode Control Capability Single Resistor Oscillator Frequency Setting Adjustable Frequency up to 250 kHz Fast Line Feedforward Line Undervoltage Lockout Dual Mode Overcurrent Protection Programmable Maximum Duty Cycle Control Maximum Duty Cycle Proportional to Line Voltage Programmable Soft Start Precision 5.0 V Reference PIN ASSIGNMENTS Vin VAUX UV OUT1 RAMP_OUT GND FF OUT2 CS RAMP_IN CSKIP VREF RT VEA DCMAX SS Typical Applications • 48 V Telecommunication Power Converters • Industrial Power Converters • 42 V Automotive Systems Device NCP1561DR2 M4 + C1 − C2 Start−up OUT2 OUT1 Shipping† SO−16 2500 Units/Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. OUT1 Feedforward NCP1561 Package TX1 M2 Vin ORDERING INFORMATION Lout M3 Cout High Side Driver Driver M1 OUT2 Opto Error Amplifier Figure 1. Half−Bridge Block Diagram Semiconductor Components Industries, LLC, 2004 February, 2004 − Rev. 2 1 Publication Order Number NCP1561/D NCP1561 Vin VAUX High Voltage Start−up Regulator 5.0 V Reference VREF Thermal Shutdown UV CS UV Fault Detection OUT1 Modulator Output Stage OUT2 CSKIP RT Oscillator VEA FF SS GND DCMAX RAMP_OUT RAMP_IN Figure 2. Simplified Block Diagram http://onsemi.com 2 NCP1561 VAUX 1 Vin 5.0 V Reference DIS Disable IAUX VAUX(on) − + VREF 11 Disable_VREF 16 One Shot Pulse (250 ns) VAUX CAUX + Output Latch S VAUX(on)/VAUX(off) Dominant Reset Q Latch − Vin R Thermal Shutdown 2 UV + − STOP − + Enable_ss 1.52 V VAUX VREF 15 12 A − + S Clock 6 − + + 2V − CCSKIP One Shot Pulse (600 ns) CS 2 k + − + 6 A Enable_ss VEA RAMP_IN 2V Max DC Comparator − Oscillator Ramp I1 2 I1 9 2V 29 k VREF RMDP + 29 k 8 VDC(inv) − SS CSS DCMAX RP 38 k STOP + − 10 pF 7 + 2V − + * Trimmed during manufacturing to obtain 1.3 V with RT = 101 k − 2V Clock Vin FF I 5.3 k IFF REA 10 12 Softstart Comparator CURRENT MIRROR 4 OUT2 20 k VREF RFF 13 PWM Comparator − + 1.0 V − RT VAUX VREF + − + 1.3 V* − OUT1 Q + − + 1.2 V − 5 RT TF/F Q Q Dominant Reset Latch R + CSKIP Disable 6.7 k V 125 k + + V − One Shot Pulse FF Ramp (Adjustable) 3 Buffer − 10.8 pF CFF Figure 3. NCP1561 Block Diagram http://onsemi.com 3 RAMP_OUT NCP1561 PIN DESCRIPTION Pin Name Application Information 1 Vin This pin is connected to the bulk DC input voltage supply. A constant current source supplies current from this pin to the capacitor connected on the VAUX pin. The charge current is typically 13.0 mA. Input voltage range is 21.5 V to 150 V. 2 UV Input supply voltage is scaled down and sampled by means of a resistor divider. The supply voltage must be scaled such that the voltage on the UV pin is 1.54 V at the minimum input voltage. 3 RAMP_OUT 4 FF An external resistor between Vin and this pin adjusts the amplitude of the FF Ramp inversely proportional to Vin. By varying the Feedforward Ramp amplitude in proportion to the input voltage, changes in loop bandwidth resulting from Vin changes are eliminated. 5 CS Overcurrent sense input. If the CS voltage exceeds 0.95 V or 1.15 V, the converter enters the Cycle by Cycle or Cycle Skip current limit mode, respectively. 6 CSKIP The capacitor connected to this pin sets the Cycle Skip period. Once a cycle skip fault is detected, the capacitor connected to this pin is discharged. The capacitor is then charged with a constant current of 12 A. The cycle skip period expires, once the voltage on this capacitor reaches 2.0 V. A soft start sequence follows at the conclusion of the fault period. 7 RT 8 DCMAX 9 SS An internal 6.0 µA current source charges the external capacitor connected to this pin. The duty cycle is limited during start−up by comparing the voltage on this pin to the Oscillator Ramp. The soft start comparator limits the duty cycle while the SS voltage is below 2.0 V. 10 VEA The error signal from an external error amplifier is fed into this input and compared to the Feedforward Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Comparator inverting input. 11 VREF Precision 5.0 V reference output. Maximum output current is 6.0 mA. 12 RAMP_IN 13 OUT2 Output 2. 14 GND Control circuit ground. 15 OUT1 Output 1. 16 VAUX Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An internal current source supplies current from Vin to this pin. Once the voltage on VAUX reaches approximately 10.3 V, the current source turns OFF. It turns ON again once VAUX falls to 7 V. During normal operation, power is supplied to the IC via this pin, by means of an auxiliary winding. The start−up circuit is disabled if the voltage on the VAUX pin exceeds 10.3 V. Internal Feedforward (FF) Ramp Output. This signal can be externally routed to the RAMP_IN pin for voltage−mode control operation. A single external resistor between this pin and GND sets the fixed oscillator frequency. An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting input. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the Feedforward Ramp. This pin configures the NCP1561 for voltage or current−mode control. The internal Feedforward Ramp (voltage−mode) or a signal proportional to the inductor current (current−mode) is fed into this input and compared to the signal in the VEA pin. http://onsemi.com 4 NCP1561 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Vin −0.3 to 150 V Auxiliary Supply Voltage VAUX −0.3 to 16 V Auxiliary Supply Input Current IAUX 35 mA OUT1 and OUT2 Voltage VOUT −0.3 to (VAUX + 0.3 V) V OUT1 and OUT2 Output Current IOUT 10 mA 5.0 V Reference Voltage VREF −0.3 to 6.0 V 5.0 V Reference Output Current IREF 6.0 mA All Other Inputs/Outputs Voltage VIO −0.3 to VREF V All Other Inputs/Outputs Current IIO 10 mA Operating Junction Temperature TJ −40 to 150 C Storage Temperature Range Tstg −55 to 150 C Power Dissipation at TA = 25°C PD 0.77 W RθJA 130 C/W Input Line Voltage Thermal Resistance, Junction to Ambient 1. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Functional operation should be restricted to the Recommended Operating Conditions. A. This device series contains ESD protection and exceeds the following tests: Pin 1: Pin 1 is the HV start−up of the device and is rated to the max rating of the part, or 150 V. Machine Model Method 150 V. Pins 2−16: Human Body Model 2000 V per MIL−STD−883, Method 3015. Machine Model Method 200 V. http://onsemi.com 5 NCP1561 ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF, RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = −40°C to 125°C, unless otherwise noted) Symbol Min Typ Max VAUX(on) VAUX(off) VH 9.7 6.6 − 10.3 7.0 3.3 10.8 7.4 − VSTART(min) − 18.3 21.5 Characteristic Unit START−UP CONTROL AND VAUX REGULATOR VAUX Regulation Startup Threshold/VAUX Regulation Peak (VAUX increasing) Minimum Operating VAUX Valley Voltage After Turn−On Hysteresis V Minimum Start−up Voltage (Pin 1) ISTART = 1.0 mA, IREF = 0 mA, VAUX = VAUX(on) − 0.2 V Start−up Circuit Output Current VAUX = 0 V TJ = 25°C TJ = −40°C to 125°C VAUX = VAUX(on) − 0.2 V TJ = 25°C TJ = −40°C to 125°C ISTART Start−up Circuit Off−State Leakage Current (Vin = 150 V) TJ = 25°C TJ = −40°C to 125°C mA 13 10 17 − 21 25 10 8.0 13 − 17 19 − − 23 − 50 100 150 − − A ISTART(off) Start−up Circuit Breakdown Voltage (Note 2) ISTART(off) = 50 A, TJ = 25°C VBR(DS) Auxilliary Supply Current After VAUX Turn−On Outputs Disabled VEA = 0 V VUV = 0 V Outputs Enabled V V mA IAUX1 IAUX2 IAUX3 − − − 3.3 1.8 4.1 5.0 2.5 6.5 VUV 1.40 1.54 1.64 V VUV(H) 0.080 0.095 0.120 V tUV − 250 − ns Cycle by Cycle Threshold Voltage ILIM1 0.89 0.95 1.03 V Propagation Delay to Output (VEA = 2.0 V) VCS = ILIM1 to 2.0 V, measured when OUT1 reaches 10 V. tILIM − 86 150 ns Cycle Skip Threshold Voltage ILIM2 1.05 1.15 1.24 V Cycle Skip Charge Current (VCSKIP = 0 V) ICSKIP 8.0 12.3 15 A Thermal Shutdown Threshold (Junction Temperature Increasing, Note 2) TSHDN − 180 − °C Thermal Shutdown Hysteresis (Junction Temperature Decreasing, Note 2) TH − 17 − °C LINE UNDERVOLTAGE DETECTOR Undervoltage Threshold (Vin Increasing) Undervoltage Hysteresis Undervoltage Propagation Delay to Output CURRENT LIMIT AND THERMAL SHUTDOWN 2. Guaranteed by design only. http://onsemi.com 6 NCP1561 ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF, RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = −40°C to 125°C, unless otherwise noted) (continued) Symbol Characteristic Min Typ Max 143 137 150 − 157 163 228 220 240 − 252 260 Unit CONTROL OUTPUTS Frequency (RT = 101 k) TJ = 25°C TJ = −40°C to 125°C fOSC1 Frequency (RT = 59 k) TJ = 25°C TJ = −40°C to 125°C fOSC2 kHz kHz Output Voltage (IOUT = 0 mA) Low State High State VOL VOH − − 0.25 11.8 − − V Drive Resistance (Vin = 15 V) Sink (VEA = 0 V, VOUT = 2 V) Source (VEA = 3 V, VOUT = 10 V) RSNK RSRC 20 50 36 88 80 170 Rise Time (CL = 100 pF, 10% to 90% of VOH) ton − 32 − ns Fall Time (CL = 100 pF, 90% to 10% of VOH) toff − 19 − ns 34 48 38 − 44 50 MAXIMUM DUTY CYCLE COMPARATOR Maximum Duty Cycle (Vin = 36 V) RP = 0 , RMDP = open RP = open, RMDP = open (Note 3) DCMAX % Open Circuit Voltage VDCMAX 0.49 0.74 0.90 V Charge Current (VSS = 1.0 V) ISS(C) 5.0 6.2 7.4 A Discharge Current (VSS = 5.0 V, VUV = 1.0 V) ISS(D) 20 50 − mA RIN(VEA) 8.0 22 60 k Lower Input Threshold VEA(L) 0.7 0.92 1.1 V Delay to Output (from VOH to 0.5 VOH) tPWM − 200 − ns 4.9 4.8 4.96 − 5.1 5.1 SOFT START PWM COMPARATOR Input Resistance (V1 = 1.25 V, V2 = 1.50 V) RIN(VEA) = (V2 − V1) / (I2 − I1) 5.0 V REFERENCE Output Voltage (IREF = 0 mA) TJ = 25°C TJ = −40°C to 125°C VREF V Load Regulation (IREF = 0 to 6 mA) VREF(Load) − 10 50 mV Line Regulation (VAUX = 7.5 V to 16 V) VREF(Line) − 50 100 mV 3. 50% Maximum Duty Cycle guaranteed by design. http://onsemi.com 7 NCP1561 19 ISTART, START−UP CIRCUIT OUTPUT CURRENT (mA) 12 11 10 START−UP THRESHOLD 9 8 7 MINIMUM OPERATING THRESHOLD 6 5 −50 −25 0 25 50 75 100 125 150 18 Vin = 48 V 17 16 VAUX = 0 V 15 14 13 12 VAUX = VAUX(on) − 0.2 V 11 10 9 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 4. Auxiliary Supply Voltage Thresholds versus Junction Temperature Figure 5. Start−up Circuit Output Current versus Junction Temperature ISTART, START−UP CIRCUIT OUTPUT CURRENT (mA) 17.5 Vin = 48 V 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 0 2 4 6 8 10 TJ = −40°C 12 TJ = 25°C TJ = 125°C 8 4 VAUX = VAUX(on) − 0.2 V 0 0 25 50 75 100 125 Vin, LINE VOLTAGE (V) Figure 6. Start−up Circuit Output Current versus Auxiliary Supply Voltage Figure 7. Start−up Circuit Output Current versus Line Voltage VAUX = 12 V TJ = −40°C 35 30 25 TJ = 25°C 20 TJ = 125°C 15 10 5 0 0 16 VAUX, AUXILIARY SUPPLY VOLTAGE (V) 40 25 50 75 100 125 150 150 4.5 VAUX = 12 V 4.0 3.5 VEA = 0 V 3.0 2.5 2.0 VUV = 0 V 1.5 1.0 0.5 −50 −25 0 25 50 75 100 125 150 Vin, LINE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 8. Start−up Circuit Off−State Leakage Current versus Line Voltage Figure 9. Auxiliary Supply Current versus Junction Temperature http://onsemi.com 8 150 20 12 IAUX, AUXILIARY SUPPLY CURRENT (mA) ISTART(off), START−UP CIRCUIT OFF− STATE LEAKAGE CURRENT (A) ISTART, START−UP CIRCUIT OUTPUT CURRENT (mA) VAUX, AUXILIARY SUPPLY VOLTAGE (V) TYPICAL CHARACTERISTICS NCP1561 TYPICAL CHARACTERISTICS 1.70 VAUX = 12 V DC 50% 5.5 VUV, LINE UNDERVOLTAGE THRESHOLD (V) IAUX3, OPERATING AUXILIARY SUPPLY CURRENT (mA) 6.0 fOSC = 250 kHz 5.0 4.5 fOSC = 150 kHz 4.0 3.5 3.0 −25 0 25 50 75 100 125 1.50 1.45 1.40 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 10. Operating Auxiliary Supply Current versus Junction Temperature Figure 11. Line Undervoltage Threshold versus Junction Temperature ILIM, CURRENT LIMIT THRESHOLDS (V) VUV(H), LINE UNDERVOLTAGE THRESHOLD HYSTERESIS (mV) 1.55 1.30 −50 150 140 130 120 110 100 90 80 70 −50 −25 0 25 50 75 100 125 150 1.25 1.20 CYCLE SKIP 1.15 1.10 1.05 1.00 CYCLE BY CYCLE 0.95 0.90 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Line Undervoltage Hysteresis versus Junction Temperature Figure 13. Current Limit Thresholds versus Junction Temperature VAUX = 12 V 110 Measured from VOH to 0.5 VOH fosc, OSCILLATOR FREQUENCY (kHz) 115 105 100 95 90 85 80 75 70 −50 −25 0 25 50 75 100 125 150 300 275 RT = 50.6 k 250 225 200 175 RT = 101 k 150 125 RT = 148 k 100 75 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 14. Current Limit Propagation Delay versus Junction Temperature Figure 15. Oscillator Frequency versus Junction Temperature http://onsemi.com 9 150 1.30 TJ, JUNCTION TEMPERATURE (°C) 120 tILIM, CURRENT LIMIT PROPAGATION DELAY (ns) 1.60 1.35 fOSC = 100 kHz 2.5 −50 1.65 150 NCP1561 fosc, OSCILLATOR FREQUENCY (kHz) 157.5 RT = 101 k 155.0 152.5 150.0 147.5 145.0 142.5 −50 −25 0 25 50 75 100 125 300 200 150 100 50 0 50 100 250 300 350 RT, TIMING RESISTOR (k) Figure 17. Oscillator Frequency versus Timing Resistor 80 70 100 90 RSRC (VEA = 0 V, VOUT = 10 V) 80 70 60 50 40 RSNK (VEA = 3 V, VOUT = 2 V) Measured from 10% to 90% of VOH VAUX = 12 V 60 400 TJ = 125°C TJ = 25°C 50 40 30 TJ = −40°C 20 10 0 −25 0 25 50 75 100 125 150 0 25 TJ, JUNCTION TEMPERATURE (°C) TJ = 25°C 20 TJ = −40°C 15 10 5 0 25 50 75 100 125 150 175 200 FEEDFORWARD INTERNAL RESISTANCE (k) Measured from 90% to 10% of VOH 30 VAUX = 12 V TJ = 125°C 75 100 125 150 175 200 Figure 19. Outputs Rise Time versus Load Capacitance 35 25 50 CL, LOAD CAPACITANCE (pF) Figure 18. Outputs Drive Resistance versus Junction Temperature toff, OUTPUTS FALL TIME (ns) 200 TJ, JUNCTION TEMPERATURE (°C) 110 VAUX = 12 V 0 150 Figure 16. Oscillator Frequency versus Junction Temperature 120 30 20 −50 TJ = 25°C DC 50% 250 150 ton, OUTPUTS RISE TIME (ns) RSNK/SRC OUTPUTS DRIVE RESISTANCE () fosc, OSCILLATOR FREQUENCY (kHz) TYPICAL CHARACTERISTICS 19 18 17 16 15 14 13 12 11 10 9 −50 −25 0 25 50 75 100 125 CL, LOAD CAPACITANCE (pF) TJ, JUNCTION TEMPERATURE (°C) Figure 20. Outputs Fall Time versus Load Capacitance Figure 21. Feedforward Internal Resistance versus Junction Temperature http://onsemi.com 10 150 NCP1561 VEA = 3.0 V DCMAX PIN = OPEN 45 40 35 30 TJ = 125°C 25 20 15 TJ = −40°C 10 5 0 0 75 150 225 300 450 375 525 40 RP = 0 , RMDP = OPEN 35 30 25 20 −50 −25 0 25 50 75 100 125 Figure 23. Maximum Duty Cycle versus Junction Temperature 6.5 65 CHARGE 6.0 60 5.5 55 DISCHARGE 50 4.5 45 4.0 40 3.5 35 −25 0 25 50 75 30 125 150 100 TJ, JUNCTION TEMPERATURE (°C) 40 30 20 10 0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 25. VEA Input Resistance versus Junction Temperature 5.01 1.00 VREF, REFERENCE VOLTAGE (V) RFF = 432 k Vin = 48 V 0.95 0.90 0.85 0.80 0.75 −50 150 50 Figure 24. Soft Start Charge/Discharge Currents versus Junction Temperature VEA(L), PWM COMPARATOR LOWER INPUT THRESHOLD (V) Vin = 36 V RFF = 432 k Figure 22. Maximum Duty Cycle versus Feedforward Current 70 3.0 −50 RP = OPEN, RMDP = OPEN 45 IFF, FEEDFORWARD CURRENT (A) 7.0 5.0 50 TJ, JUNCTION TEMPERATURE (°C) ISS(D), SOFT START DISCHARGE CURRENT (mA) ISS(C), SOFT START CHARGE CURRENT (A) DCMAX, MAXIMUM DUTY CYCLE (%) 50 RIN(VEA), VEA INPUT RESISTANCE (k) DCMAX, MAXIMUM DUTY CYCLE (%) TYPICAL CHARACTERISTICS −25 0 25 50 75 100 125 150 4.99 4.97 IREF = 0 mA 4.95 IREF = 6 mA 4.93 4.91 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 26. PWM Comparator Lower Input Threshold versus Junction Temperature Figure 27. Reference Voltage versus Junction Temperature http://onsemi.com 11 NCP1561 DETAILED OPERATING DESCRIPTION The NCP1561 is a push−pull PWM controller for use in 48 V telecom power converters or 42 V automotive systems. This controller contains all the features and flexibility required in high density isolated dc−dc modules and on−board designs for telecom and automotive systems. It can be configured for operation in voltage−mode with feedforward or current−mode control. The extensive set of features included in the NCP1561 facilitates system design and reduces overall system cost and component count by incorporating supervisory functions and components traditionally found outside the controller. Features of the NCP1561 include a high voltage start−up regulator, fast line feedforward, a line undervoltage lockout, dual mode overcurrent protection, programmable maximum duty cycle limit, programmable soft start and external voltage reference. Voltage−mode operation with line feedforward provides better line regulation without some of the traditional problems associated with current−mode control. The controller is configured for voltage−mode operation by routing the internal Feedforward Ramp output (RAMP_OUT) to the PWM Comparator non−inverting input (RAMP_IN). The amplitude of the Feedforward Ramp varies inversely proportional to the input voltage. Operation in current−mode control is obtained by routing a signal proportional to the inductor current into the PWM Comparator non−inverting input (VEA pin). In either mode, the maximum duty cycle is inversely proportional to the line voltage, as configured by the DCMAX pin and FF pins. reaches approximately 10.3 V, the start−up regulator turns OFF and the outputs are enabled. When VAUX reaches 7 V, the outputs are disabled and the start−up regulator turns ON. This mode of operation is known as Dynamic Self Supply (DSS). The start−up circuit sources current out of the VAUX pin. It is recommended to place a diode between CAUX and the auxiliary supply as shown in Figure 28. This will allow the NCP1561 to charge CAUX while preventing the start−up regulator from sourcing current into the auxiliary supply. ISTART Vin ISTART To auxiliary supply VAUX IAUX CAUX Isupply Disable Figure 28. Recommended VAUX Configuration Power to the controller while operating in the self−bias or DSS mode is provided by CAUX. Therefore, CAUX must be sized such that a VAUX voltage greater than 7 V is maintained while the outputs are enabled and the converter reaches regulation. Also, the VAUX discharge time (from 10.3 V to 7 V) must be greater than the soft start charge period to assure the converter turns ON. The start−up circuit is rated at a maximum voltage of 150 V. If the device operates in the DSS mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. The start−up regulator is disabled by biasing VAUX above 7 V once the outputs are enabled. It can also be disabled by biasing VAUX above VAUX(on) (typically 10.3 V). This feature allows the NCP1561 to operate from an independent 12 V (±10%) supply. The independent supply should keep VAUX above VAUX(on). Otherwise the Output Latch will not be SET and the outputs will remain OFF after a fault condition is cleared. If operating from an independent supply, the Vin and VAUX pins should be connected together. High Voltage Start−up Regulator The NCP1561 contains an internal high voltage start−up regulator that eliminates the need for external start−up components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The start−up regulator consists of a constant current source that supplies current from the input line voltage (Vin) to the capacitor on the VAUX pin (CAUX). The start−up current is typically 13.0 mA. Once VAUX http://onsemi.com 12 NCP1561 Line Undervoltage Shutdown The NCP1561 incorporates a line undervoltage shutdown (UV) circuit. The undervoltage threshold is approximately 1.54 V. The UV circuit can be biased using an external resistor divider from the input line. The resistor divider must be sized to enable the controller once Vin is within the required operating range. Once the UV condition is removed and VAUX reaches VAUX(on), the controller initiates a soft start cycle, as shown in Figure 29. The UV pin can also be used to implement a remote enable/disable function. Biasing the UV pin below its UV threshold disables the converter. SOFT START VAUX(on) VAUX VAUX(off) 0V 2V 0V 2V 0V UV Voltage Soft Start Voltage OUT2 0V OUT1 0V Figure 29. Soft Start Timing Diagram (Using Auxiliary Winding) If the UV threshold is reached, once in normal operation, the soft start capacitor is discharged, and the outputs are immediately disabled as shown in Figure 30. Also, if an UV condition is detected, the 5.0 V Reference Supply is disabled. VAUX(on) VAUX VAUX(off) 0V UV Fault UV Voltage VUV 0V Propagation Delay to Outputs (tUV) OUT1 0V OUT2 0V Figure 30. UV Fault Timing Diagram http://onsemi.com 13 NCP1561 Feedforward Ramp Generator The NCP1561 incorporates line feedforward (FF) to compensate for changes in line voltage. A FF Ramp proportional to Vin is generated and compared to the error signal. If the line voltage changes, the FF Ramp slope changes accordingly. The duty cycle will be adjusted immediately instead of waiting for the line voltage change to propagate around the system and be reflected back on VEA. A resistor between Vin and the FF pin (RFF) sets the feedforward current (IFF). The FF Ramp is generated by charging an internal 10.8 pF capacitor (CFF) with a constant current proportional to IFF. The FF Ramp is finished (capacitor is discharged) once the Oscillator Ramp reaches 2.0 V. Please refer to Figure 3 for a functional drawing of the Feedforward Ramp generator. IFF is usually a few hundred microamps, depending on the operating frequency and the required duty cycle. If the operating frequency and maximum duty cycle are known, IFF is calculated using the equation below: IFF For example, if a system is designed to operate at an oscillator frequency of 150 kHz, with a 45% maximum duty cycle at 36 V, the DCMAX pin can be grounded and IFF is calculated as follows: 1 T1 6.66 s 150 kHz f ton(max) DCMAX T 0.45 6.66 s 3.0 s IFF CFF VDC(inv) 125 k 6.7 k ton(max) 10.8 pF 1.0 V 125 k 67.2 A 6.7 k 3.0 s As the minimum line voltage is 36 V, the required feedforward resistor is calculated using the equation below: V RFF in 12.0 k 36 V 12.0 k 523 k IFF 67.2 A From the above calculations it can be observed that IFF is controlled predominantly by the value of RFF, as the resistance seen into the FF pin is only 12 k. If a tight maximum duty cycle control over temperature is required, RFF should have a low thermal coefficient. If current−mode control is used and the FF Ramp generator is not used for maximum duty cycle control, the FF Ramp generator can be disabled grounding the FF pin. CFF VDC(inv) 125 k 6.7 k ton(max) where VDC(inv) is the voltage on the inverting input of the Max DC Comparator and ton(max) is the maximum ON time. Figure 22 shows the relationship between IFF and DCMAX. http://onsemi.com 14 NCP1561 Current Limit The NCP1561 has two overcurrent protection modes, cycle by cycle and cycle skip. It allows the NCP1561 to handle momentary and hard shorts differently for the best tradeoff in system performance and safety. The outputs are disabled typically 86 ns after a current limit fault is detected. The cycle by cycle mode terminates the conduction cycle (reducing the duty cycle) if the voltage on the CS pin exceeds 0.95 V. The cycle skip mode is enabled if the voltage on the CS pin reaches 1.15 V. Once a cycle skip fault is detected, the outputs are disabled, the soft start and cycle skip capacitors are discharged, and the cycle skip period (TCSKIP) commences. NORMAL OPERATION ILIM Faults The cycle skip period is set by an external capacitor (CCSKIP). Once a cycle skip fault is detected, the cycle skip capacitor is discharged followed by a charge cycle. The charge current is 12.3 A. The cycle skip period ends when the voltage on the cycle skip capacitor reaches 2.0 V. If the cycle skip period is known, the cycle skip capacitor is calculated using the equation below: CCSKIP TCSKIP 12.3 A 2V Using the above equation, a cycle skip period of 11.0 s requires a cycle skip capacitor of 68 pF. The differences between the cycle by cycle and cycle skip modes are shown in Figure 31. RESET SOFT START VAUX(on) VAUX VAUX(off) 0V OUT1 0V OUT2 0V ILIM2 ILIM1 CS Voltage 0V TCSKIP Cycle Skip Voltage 2V 0V Figure 31. Overcurrent Faults Timing Diagram Once the cycle skip period is complete and VAUX reaches VAUX(on), a soft start sequence commences. The possible minimum OFF time is set by CCSKIP. The actual OFF time is generally greater than the cycle skip period if operating in DSS because it is the cycle skip period added to the time it takes VAUX to cycle between VAUX(off) and VAUX(on). If operating from an independent supply, the OFF time is the cycle skip period. The voltage on the RT pin is laser trim adjusted during manufacturing to 1.3 V for an RT of 101 k. A current set by RT generates an Oscillator Ramp by charging an internal 10 pF capacitor as shown in Figure 3. The period ends (capacitor is discharged) once the Oscillator Ramp reaches 2.0 V. If RT increases, the current and the Oscillator Ramp slope decrease, thus reducing the frequency. If RT decreases, the opposite effect is obtained. Figure 17 shows the relationship between RT and the oscillator frequency. Oscillator The NCP1561 oscillator frequency is set by a single external resistor connected between the RT pin and GND. The oscillator is designed to operate up to 250 kHz. http://onsemi.com 15 NCP1561 5.0 V Reference The NCP1561 includes a precision 5.0 V reference output. The reference output is biased directly from VAUX and it can supply up to 6 mA. Load regulation is 50 mV and line regulation is 100 mV within the specified operating range. It is recommended to bypass the reference output with a 0.1 F ceramic capacitor. The reference output is disabled when an UV fault is present. Maximum Duty Cycle A dedicated internal comparator limits the maximum ON time by comparing the FF Ramp to VDC(inv) as shown in Figure 3. If the FF Ramp voltage exceeds VDC(inv), the output of the Max DC Comparator goes high. This will reset the Output Latch, thus turning OFF the outputs and limiting the duty cycle. Duty cycle is defined as: t DC on ton f T PWM Comparator In steady state operation, the PWM Comparator adjusts the duty cycle by comparing the error signal to the FF Ramp (voltage−mode) or a ramp proportional to the inductor current (current−mode). The error signal is fed into the VEA input. The FF Ramp or the inductor ramp is fed into the RAMP_IN pin. If operating in voltage−mode, the connection between the RAMP_OUT and RAMP_IN pins should be as close as possible to minimize parasitic inductance. It can be easily routed underneath the package. The VEA input can be driven directly with an optocoupler and a pull up resistor (REA) from VREF as shown in Figure 33. The drive of the control pin is simplified by internally incorporating a series diode and resistor. The series diode provides a 0.7 V offset between the VEA input and the PWM Comparator inverting input. The outputs are enabled if the VEA voltage is approximately 0.7 V above the valley voltage of the ramp (Vvalley) in the RAMP_IN pin. Therefore, the maximum ON time can be set to yield the desired DC if the operating frequency is known. The maximum ON time is set by adjusting the FF Ramp to reach VDC(inv) in a time equal to ton(max) as shown in Figure 32. The maximum ON time should be set for the minimum line voltage. As line voltage increases, the slope of the FF Ramp increases. This reduces the duty cycle below DCMAX, which is a desirable feature as the duty cycle is inversely proportional to line voltage. Oscillator Ramp 2V 0V T FF Ramp VREF VDC(inv) 11 0V REA ton(max) PWM Comparator − + Figure 32. Maximum ON Time Limit Waveforms An internal resistor divider from a 2.0 V reference is used to set VDC(inv). If the DCMAX pin is grounded, VDC(inv) is 1.0 V. If the pin is floating, VDC(inv) is 1.4 V. This is equivalent to 71% (36% DC) or 100% (50% DC) of a FF Ramp, with a peak voltage of 1.4 V. VDC(inv) can be adjusted to other values by placing an external resistor network on the DCMAX pin. For example, if the minimum line voltage is 36 V, RFF is 432 k, oscillator frequency is 150 kHz and a maximum duty cycle of 45% is required, VDC(inv) is calculated as follows: VDC(inv) VDC(inv) 2 k VEA + 10 Feedback Signal 20 k VEA − Vpeak RAMP_IN 12 Vvalley 0V FF Ramp or Inductor Ramp Figure 33. Optocoupler driving VEA input IFF 6.7 k ton(max) CFF 125 k The pull−up resistor is selected such that in the absence of the error signal, the voltage on the VEA pin exceeds the peak amplitude of the ramp in the RAMP_IN pin. Otherwise, the converter may not be able to reach maximum duty cycle. If operating in voltage−mode, REA is calculated using the equation below: 81.0 A 6.7 k 3.0 s 1.2 V 10.8 pF 125 k This can be achieved by connecting a 23.44 k resistor from the DCMAX pin to GND. The maximum duty cycle limit can be disabled connecting a 100 k resistor between the DCMAX and VREF pins. REA 22 k VREF 0.7 V 1 0.0515I Vvalley C fFF FF where, CFF is the internal FF capacitor, typically 10.8 pF. http://onsemi.com 16 NCP1561 Control Outputs The NCP1561 has two off−phase control outputs, OUT1 and OUT2. Figure 35 shows the relationship between OUT1 and OUT2. Soft Start Soft start (SS) allows the converter to gradually reach steady state operation, thus reducing start−up stress and surges on the system. The duty cycle is limited during a soft start sequence by comparing the Oscillator Ramp to the SS voltage (VSS) by means of the Soft Start Comparator. Once faults are removed and VAUX reaches VAUX(on), a 6.2 A current source starts to charge the capacitor on the SS pin. The Soft Start Comparator controls the duty cycle while the SS voltage is below 2.0 V. Once VSS reaches 2.0 V, it exceeds the Oscillator Ramp voltage and the Soft Start Comparator does not limit the duty cycle. Figure 34 shows the relationship between the outputs duty cycle and the soft start voltage. Oscillator Ramp OUT1 OUT2 Figure 35. Control Outputs Timing Diagram Once VAUX reaches VAUX(on), the internal start−up circuit is disabled and the One Shot Pulse Generator is enabled. If no faults are present, the outputs turn ON. Otherwise, the outputs remain OFF until the fault is removed and VAUX reaches VAUX(on) again. The control outputs are biased from VAUX. The outputs can supply up to 10 mA each and their high state voltage is usually 0.2 V below VAUX. Therefore, the auxiliary supply voltage should not exceed the maximum input voltage of the driver stage. If the control outputs need to drive a large capacitive load, a driver should be used between the NCP1561 and the load. Figures 19 and 20 show the relationship between the output’s rise and fall times vs capacitive load. VSS OUT1 OUT2 Figure 34. Soft Start Timing Diagram Thermal Protection Internal Thermal Shutdown Circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 180C, the controller is forced into a low power reset state, discharging the soft start capacitor and disabling the output drivers and the bias regulator. Once the junction temperature falls below 163C, the NCP1561 enters a soft start mode and it is allowed to resume normal operation. This feature is provided to prevent catastrophic failures from accidental device overheating. If the soft start period is too long, VAUX may discharge to 7 V before the converter output is completely in regulation causing the outputs to be disabled. If the converter output is not completely discharged when the outputs are re−enabled, the converter will eventually reach regulation exhibiting a non−monotonic start−up behavior. But, if the converter output is completely discharged when the outputs are re−enabled, the cycle may repeat and the converter will not start. In the event of an UV or cycle skip fault, the soft start capacitor is discharged. Once the fault is removed, a soft start cycle commences. The soft start steady state voltage is approximately 4.1 V. http://onsemi.com 17 NCP1561 PACKAGE DIMENSIONS SO−16 D SUFFIX CASE 751B−05 ISSUE J −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 The product described herein (NCP1561) may be covered by one or more U.S. patents. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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