NCP1560 Full Featured Voltage Mode PWM Controller The NCP1560 PWM controller contains all the features and flexibility needed to implement voltage- mode control in high performance single ended DC/DC converters. This device cost effectively reduces system part count with the inclusion of a high voltage start-up regulator that operates over a wide input range of 21.5 V to 150 V. The NCP1560 provides two control outputs, OUT1 which controls the main PWM switch and OUT2 with adjustable over-lap delay, which can control a synchronous rectifier switch or an active clamp/reset switch. Other distinctive features include: two mode over current protection, line under/over voltage lockout, fast line feedforward, soft start and a maximum duty cycle limit. MARKING DIAGRAM 16 SO-16 D SUFFIX CASE 751B 16 NCP1560 AWLYWW 1 Features • • • • • • • • • • • http://onsemi.com 1 Minimum Operating Voltage of 21.5 V Internal High Voltage Start-up Regulator Dual Control Outputs with Adjustable Overlap Delay Single Resistor Oscillator Frequency Setting Fast Line Feedforward Line Under/Over Voltage Lockout Dual Mode Over Current Protection Programmable Maximum Duty Cycle Control Maximum Duty Cycle Proportional to Line Voltage Programmable Soft Start Precision 5.0 V Reference NCP1560 = Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week ORDERING INFORMATION Device NCP1560HDR2 Package Shipping SO-16 2500/Tape & Reel Typical Applications • • • • • Telecommunication Power Converters Industrial Power Converters High Voltage Power Modules +42 V Automotive Systems Control Driven Synchronous Rectifier Power Converters Semiconductor Components Industries, LLC, 2003 January, 2003 - Rev. 5 1 Publication Order Number NCP1560/D NCP1560 Vin VAUX High Voltage Start-up Regulator 5.0 V Reference UV/OV CS UV Fault Detection Modulator Delay Logic VREF Output Drivers OUT1 OUT2 tD CSKIP RT Oscillator VEA FF SS GND DCMAX Figure 1. Simplified Block Diagram http://onsemi.com 2 NCP1560 1 Vin VAUX Disable 13.8 mA 16 One Shot Pulse (250 ns) VAUX CAUX 5.0 V Reference 11 DIS + 14 - Disable_VREF 11 V/7 V GND S Q Monotonic Start Latch (Reset Dominant) R Disable_VREF Vin + - + 1.49 V 2 UV/OV RD Disable_ss STOP + - + 3.6 V - 12 tD VREF Disable CSKIP 11 A DIS 15 + S Clock 6 One Shot Pulse (600 ns) Delay Logic VAUX DIS CS + OUT2 VAUX + - Soft Start - + Comparator 0.5 V PWM Comparator + - - 10 VREF Oscillator Ramp Disable_ss 9 I1 2 I1 SS CSS + - 10 pF * Trimmed during manufacturing to obtain 1.3 V with RT = 101 k - 2V 2V Clock V I 125 k 5.3 k 4 IFF 6.7 k + + V - Max DC Comparator + - + 2V - + + 1.3 V* - Vin FF 20 k 2V STOP 7 One Shot Pulse FF Ramp (Adjustable) 40 k 32 k 8 CFF Figure 2. NCP1560 Functional Block Diagram http://onsemi.com 3 VREF RMDP + DCMAX VDC(inv) 10 pF VEA 2 k CURRENT MIRROR RFF 13 + + 0.6 V - 5 RT OUT1 Q Output Latch (Reset Dominant) R + + 2V - CCSKIP RT VREF 27 k RP NCP1560 PIN DESCRIPTION Pin Name Application Information 1 Vin This pin is connected to the bulk DC input voltage supply. A constant current source supplies current from this pin to the capacitor connected on the VAUX pin. The charge current is typically 13.8 mA. Input voltage range is 21.5 V to 150 V. 2 UV/OV Input supply voltage is scaled down and sampled by means of a resistor divider. The supply voltage must be scaled down between 1.52 V and 3.61 V within the specified input voltage range. 3 NC Not Connected. 4 FF An external resistor between Vin and this pin adjusts the amplitude of the FF Ramp in proportion to Vin. By varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth are eliminated. 5 CS Over current sense input. If the CS voltage exceeds 0.48 V or 0.57 V, the converter enters the Cycle by Cycle or Cycle Skip current limit mode, respectively. 6 CSKIP The capacitor connected between this pin and ground sets the Cycle Skip period. A soft start sequence follows at the conclusion of the fault period. 7 RT 8 DCMAX An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting input. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the Feedforward Ramp. 9 SS An internal 6.2 A current source charges the external capacitor connected to this pin. The duty cycle is limited during start-up by comparing the voltage on this pin to the Oscillator Ramp. 10 VEA The error signal from an external error amplifier is fed into this input and compared to the Feedforward Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Comparator inverting input. 11 VREF Precision 5.0 V reference output. Maximum output current is 6 mA. 12 tD An external resistor between VREF and this pin sets the overlap delay between OUT1 and OUT2 transitions. 13 OUT2 Output of the PWM controller with leading and trailing edge overlap delay. OUT2 can be used to drive a synchronous rectifier topology, an active clamp/reset switch, or both. 14 GND Control circuit ground. 15 OUT1 Main output of the PWM controller. 16 VAUX Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An internal current supplies current from Vin to this pin. Once the voltage on VAUX reaches 11 V, the current source turns OFF. It turns ON again once VAUX falls to 7 V. During normal operation, power is supplied to the IC via this pin, by means of an auxiliary winding. A single external resistor between this pin and GND sets the oscillator fixed frequency. http://onsemi.com 4 NCP1560 MAXIMUM RATINGS (Note 1) Symbol Value Unit Vin -0.3 to 150 V Auxiliary Supply Voltage VAUX -0.3 to 16 V Auxiliary Supply Input Current IAUX 35 mA OUT1 and OUT2 Voltage VOUT -0.3 to (VAUX + 0.3 V) V OUT1 and OUT2 Output Current IOUT 10 mA 5.0 V Reference Voltage VREF -0.3 to 6.0 V 5.0 V Reference Output Current IREF 6.0 mA All Other Inputs/Outputs Voltage VIO -0.3 to VREF V All Other Inputs/Outputs Current IIO 10 mA Operating Junction Temperature TJ -40 to 125 °C Storage Temperature Range Tstg -55 to 150 °C Power Dissipation at TA = 25°C PD 0.77 W RJA 130 °C/W Rating Input Line Voltage Thermal Resistance, Junction to Ambient 1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. A. This device series contains ESD protection and exceeds the following tests: Pin 1 is the HV start-up of the device and is rated to the max rating of the part, or 150 V. Machine Model Method 150 V. Pins 2-16: Human Body Model 4000 V per MIL-STD-883, Method 3015. Machine Model Method 200 V. http://onsemi.com 5 NCP1560 ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF, RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = -40°C to 125°C, unless otherwise noted) Characteristic Symbol Min Typ Max VAUX(on) VAUX(off) VH 10.5 6.6 - 11.0 7.0 4.0 11.5 7.4 - - 19.3 21.5 Unit START-UP CONTROL AND VAUX REGULATOR VAUX Regulation Start-up Threshold/VAUX Regulation Peak (VAUX increasing) Minimum Operating VAUX Valley Voltage After Turn-On Hysteresis V Minimum Start-up Voltage (Pin 1) ISTART = 1.0 mA, VAUX = VAUX(on) - 0.2 V VSTART(min) Start-up Circuit Output Current VAUX = 0 V TJ = 25°C TJ = -40°C to 125°C VAUX = VAUX(on) - 0.2 V TJ = 25°C TJ = -40°C to 125°C V ISTART Start-up Circuit Off-State Leakage Current (Vin = 150 V) TJ = 25°C TJ = -40°C to 125°C mA 13 10 17.5 - 21 25 10 8 13.8 - 17 19 - 23 - 50 100 150 - - A ISTART(off) Start-up Circuit Breakdown Voltage (Note 2) ISTART(off) = 50A, TJ = 25°C V(BR)DS Auxiliary Supply Current After VAUX Turn-On Outputs Disabled VEA = 0 V VUV/OV = 0.7 V Outputs Enabled V mA IAUX1 IAUX2 IAUX3 - 2.7 1.3 4.6 5.0 2.5 6.5 VUV 1.40 1.52 1.64 V VUV(H) 0.080 0.098 0.120 V VOV 3.47 3.61 3.75 V VOV(H) - 0.145 - V Undervoltage Propagation Delay to Output tUV - 250 - ns Overvoltage Propagation Delay to Output tOV - 160 - ns Cycle by Cycle Threshold Voltage ILIM1 0.44 0.48 0.52 V Propagation Delay to Output (VEA = 2.0 V) VCS = ILIM1 to 2.0 V, measured when VOUT reaches 0.5 VOH tILIM - 90 150 ns Cycle Skip Threshold Voltage ILIM2 0.54 0.57 0.62 V ICSKIP 8.0 12.3 15 A LINE UNDER/OVERVOLTAGE DETECTOR Undervoltage Threshold (Vin Increasing) Undervoltage Hysteresis Overvoltage Threshold (Vin Increasing) Overvoltage Hysteresis CURRENT LIMIT Cycle Skip Charge Current (VCSKIP = 0 V) 2. Guaranteed by design only. http://onsemi.com 6 NCP1560 ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF, RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = -40°C to 125°C, unless otherwise noted) Symbol Characteristic Min Typ Max 285 280 300 - 315 320 456 444 480 - 504 516 57 75 62 80 66 85 Unit OSCILLATOR Frequency (RT = 101 k, Vin = 36 V) TJ = 25°C TJ = -40°C to 125°C fOSC1 Frequency (RT = 59 k, Vin = 36 V, VEA = 1 V) TJ = 25°C TJ = -40°C to 125°C fOSC2 kHz kHz MAXIMUM DUTY CYCLE COMPARATOR Maximum Duty Cycle (Vin = 36 V, VEA = 3 V, TJ = 25°C) RP = 0 , RMDP = open RP = open, RMDP = open DCMAX Open Circuit Voltage VDCMAX 0.40 0.47 0.60 V Charge Current (VSS = 1.0 V) ISS(C) 5.0 6.2 7.4 A Discharge Current (VSS = 5.0 V, VUV/OV = 3.7 V) ISS(D) 20 52.5 - mA RIN(VEA) 8.0 22 60 k Lower Input Threshold VEA(L) 0.3 0.7 0.9 V Delay to Output (from VOH to 0.5 VOH) tPWM - 200 - ns VREF 4.9 5.0 5.1 V Load Regulation (IREF = 0 to 6 mA) VREF(Load) - 10 50 mV Line Regulation (VAUX = 7.5 to 16 V) VREF(Line) - 50 100 mV VOL VOH - 0.25 11.8 - % SOFT START PWM COMPARATOR Input Resistance (V1 = 1.25 V, V2 = 1.50 V) RIN(VEA) = (V2 - V1)/(I2 - I1) 5.0 V REFERENCE Output Voltage (IREF = 0 mA) CONTROL OUTPUTS Output Voltage (IOUT = 0 mA) Low State High State V Overlap Delay (Vin = 36 V) RD = 1 M Leading Trailing RD = 60 k Leading Trailing tD ns - 200 170 - 50 32 90 72 130 130 RSNK RSRC 20 50 40 90 80 170 Rise Time (CL = 100 pF, 10% to 90% of VOH) ton - 30 - ns Fall Time (CL = 100 pF, 90% to 10% of VOH) toff - 12 - ns Drive Resistance (Vin = 15 V) Sink (VEA = 0 V, VOUT = 2 V) Source (VEA = 3 V, VOUT = 10 V) http://onsemi.com 7 NCP1560 20 ISTART, START-UP CIRCUIT OUTPUT CURRENT (mA) 12 11 START-UP THRESHOLD 10 9 8 7 MINIMUM OPERATING THRESHOLD 6 5 -50 -25 25 50 75 100 125 150 19 Vin = 48 V 18 17 VAUX = 0 V 16 15 14 13 VAUX = VAUX(on) - 0.2 V 12 11 10 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Auxiliary Supply Voltage Thresholds versus Junction Temperature Figure 4. Start-up Circuit Output Current versus Junction Temperature 17.0 ISTART, START-UP CIRCUIT OUTPUT CURRENT (mA) 17.5 Vin = 48 V 16.5 16.0 15.5 15.0 14.5 14.0 13.5 0 ISTART(off), START-UP CIRCUIT OFFSTATE LEAKAGE CURRENT (A) 0 2 4 6 8 10 TJ = 25°C 12 TJ = 125°C 8 4 VAUX = VAUX(on) - 0.2 V 0 0 25 50 75 100 125 Vin, LINE VOLTAGE (V) Figure 5. Start-up Circuit Output Current versus Auxiliary Supply Voltage Figure 6. Start-up Circuit Output Current versus Line Voltage VAUX = 12 V TJ = -40°C 35 30 25 TJ = 25°C 20 TJ = 125°C 15 10 5 0 0 TJ = -40°C 16 VAUX, AUXILIARY SUPPLY VOLTAGE (V) 40 25 50 75 100 125 150 150 4.0 3.5 VAUX = 12 V 3.0 VEA = 0 V 2.5 2.0 1.5 VUV/OV = 0 V 1.0 0.5 0 -50 -25 0 25 50 75 100 125 150 Vin, LINE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Start-up Circuit Off-State Leakage Current versus Line Voltage Figure 8. Auxiliary Supply Current versus Junction Temperature http://onsemi.com 8 150 20 12 IAUX, AUXILIARY SUPPLY CURRENT (mA) ISTART, START-UP CIRCUIT OUTPUT CURRENT (mA) VAUX, AUXILIARY SUPPLY VOLTAGE (V) Typical Characteristics NCP1560 Typical Characteristics 4.0 fOSC = 440 kHz 6 VUV/OV, UV/OV VOLTAGE (V) VAUX = 12 V DC 50% fOSC = 300 kHz 5 4 3 fOSC = 87 kHz 2 1 0 -50 -25 0 25 50 75 100 125 VUV/OV(H), UV/OV THRESHOLD VOLTAGE HYSTERESIS (mV) OV THRESHOLD 3.0 2.5 2.0 1.5 UV THRESHOLD 1.0 0.5 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 9. Operating Auxiliary Supply Current versus Junction Temperature Figure 10. Line Under/Overvoltage Thresholds versus Junction Temperature 160 150 OV HYSTERESIS 140 130 120 110 UV HYSTERESIS 100 90 -50 -25 0 25 50 75 100 125 150 600 575 CYCLE SKIP 550 525 500 CYCLE BY CYCLE 475 450 425 400 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 11. Line Under/Over Voltage Thresholds Hysteresis versus Junction Temperature Figure 12. Current Limit Thresholds versus Junction Temperature 115 VAUX = 12 V 110 Measured from VOH to 0.5 VOH fosc, OSCILLATOR FREQUENCY (kHz) 120 tILIM, CURRENT LIMIT PROPAGATION DELAY (ns) 3.5 0 -50 150 ILIM, CURRENT LIMIT THRESHOLDS (mV) IAUX3, OPERATING AUXILIARY SUPPLY CURRENT (mA) 7 105 100 95 90 85 80 75 70 -50 -25 0 25 50 75 100 125 150 450 400 RT = 68 k 350 300 RT = 101 k 250 200 150 100 RT = 390 k 50 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 13. Current Limit Propagation Delay versus Junction Temperature Figure 14. Oscillator Frequency versus Junction Temperature http://onsemi.com 9 150 NCP1560 600 fosc, OSCILLATOR FREQUENCY (kHz) 315 RT = 101 k 400 305 300 300 200 295 100 290 -25 0 25 50 75 100 125 100 150 200 250 300 350 RT, TIMING RESISTOR (k) Figure 15. Oscillator Frequency versus Junction Temperature Figure 16. Oscillator Frequency versus Timing Resistor 17 16 15 14 13 12 11 10 -25 0 25 50 75 100 125 Vin = 36 V VEA = 3.0 V VDCMAX = 0 V 80 70 60 50 TJ = -40°C 40 30 20 TJ = 125°C 10 0 0 150 75 150 225 300 375 450 TJ, JUNCTION TEMPERATURE (°C) IFF, FEEDFORWARD CURRENT (A) Figure 17. Feedforward Internal Resistance versus Junction Temperature Figure 18. Maximum Duty Cycle versus Feedforward Current 100 Vin = 36 V RFF = 432 k 90 RP = OPEN, RMDP = OPEN 80 70 RP = 0 , RMDP = OPEN 60 -25 0 25 50 75 100 125 150 400 90 DCMAX, MAXIMUM DUTY CYCLE (%) 18 50 -50 50 TJ, JUNCTION TEMPERATURE (°C) 19 9 -50 0 150 ISS(C), SOFT START CHARGE CURRENT (A) 285 -50 TJ = 25°C DC 50% 500 310 525 70 7.0 6.5 65 CHARGE 6.0 60 5.5 55 DISCHARGE 5.0 50 4.5 45 4.0 40 3.5 35 3.0 -50 -25 0 25 50 75 100 30 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 19. Maximum Duty Cycle versus Junction Temperature Figure 20. Soft Start Charge/Discharge Currents versus Junction Temperature http://onsemi.com 10 ISS(D), SOFT START DISCHARGE CURRENT (mA) DCMAX, MAXIMUM DUTY CYCLE (%) FEEDFORWARD INTERNAL RESISTANCE (k) fosc, OSCILLATOR FREQUENCY (kHz) Typical Characteristics NCP1560 50 VEA(L), PWM COMPARATOR LOWER INPUT THRESHOLD (V) RIN(VEA), VEA INPUT RESISTANCE (k) Typical Characteristics 40 30 20 10 0 -50 0 -25 25 50 75 100 125 150 0.85 0.75 0.65 0.55 0.45 0.35 -50 -25 Figure 21. VEA Input Resistance versus Junction Temperature 50 75 100 125 150 350 tD, OUTPUTS OVERLAP DELAY (ns) VREF, REFERENCE VOLTAGE (V) 25 Figure 22. PWM Comparator Lower Input Threshold versus Junction Temperature 5.03 5.01 IREF = 0 mA 4.99 IREF = 6 mA 4.97 4.95 4.93 -50 -25 0 25 50 75 100 125 300 200 150 RD = 60 k, LEADING 100 50 0 -50 150 RD = 1 M, LEADING 250 -25 200 TRAILING 150 125 100 75 50 0 200 400 600 800 1000 RSNK/SRC OUTPUTS DRIVE RESISTANCE () LEADING 175 25 50 75 100 125 150 Figure 24. Outputs Overlap Delay versus Junction Temperature 225 TJ = 25°C 0 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 23. Reference Voltage versus Junction Temperature tD, OUTPUTS OVERLAP DELAY (ns) 0 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) 200 160 Vin = 36 V VAUX = 12 V RMDP = 100 k 120 RSRC (VEA = 0 V, VOUT = 10 V) 80 40 RSNK (VEA = 3 V, VOUT = 2 V) 0 -50 RD, DELAY RESISTOR (k) -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 25. Outputs Overlap Delay versus Delay Resistor Figure 26. Outputs Drive Resistance Voltage versus Junction Temperature http://onsemi.com 11 NCP1560 Typical Characteristics 35 Measured from 10% to 90% of VOH VAUX = 12 V 70 toff, OUTPUTS FALL TIME (ns) ton, OUTPUTS RISE TIME (ns) 80 TJ = 125°C TJ = 25°C 60 50 40 30 TJ = -40°C 20 10 0 Measured from 90% to 10% of VOH 30 VAUX = 12 V TJ = 125°C 25 20 TJ = 25°C 15 10 TJ = -40°C 5 0 0 25 50 75 100 125 150 175 200 0 25 75 50 100 125 150 175 CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF) Figure 27. Outputs Rise Time versus Load Capacitance Figure 28. Outputs Fall Time versus Load Capacitance 200 DETAILED OPERATING DESCRIPTION The NCP1560 PWM controller contains all the features and flexibility needed for implementation of Voltage-Mode Control in high performance DC/DC converters. This device cost effectively reduces system part count with the inclusion of a high voltage start-up regulator. The NCP1560 provides two control outputs. Output 1 controls the main switch of a forward or flyback topology. Output 2 has an adjustable overlap delay, which can be used to control an active clamp/reset switch, a synchronous rectifier switch, or both. Other distinctive features include: two mode overcurrent protection, line under/over voltage lockout, fast line feedforward, soft start and a maximum duty cycle limit. The Functional Block Diagram is shown in Figure 2. The features included in the NCP1560 provide all the advantages of Current-Mode Control, fast line feedforward, and cycle by cycle current limit. It eliminates the disadvantages of low power jitter, slope compensation and noise susceptibility. the start-up regulator from turning ON. It is recommended to bias the VAUX pin using an auxiliary supply generated out of an auxiliary winding from the power transformer. An independent voltage supply can also be used. However, if VAUX is biased before the outputs are enabled or while a fault is present, the One Shot Pulse Generator (Figure 2) will not be enabled and the outputs will remain OFF. As the DSS sources current to the VAUX pin, a diode should be placed between CAUX and the auxiliary supply as shown in Figure 29. This will allow the NCP1560 to charge CAUX while preventing the start- up regulator from sourcing current into the auxiliary supply. ISTART 13.8 mA Vin To auxiliary supply VAUX IAUX CAUX Isupply Disable High Voltage Start-up Regulator The NCP1560 contains an internal high voltage start-up regulator that eliminates the need for external start-up components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The start- up regulator consists of a constant current source that supplies current from the input line voltage (Vin) to the capacitor on the VAUX pin (CAUX). The start- up current is typically 13.8 mA. Once VAUX reaches 11 V, the start- up regulator turns OFF and the outputs are enabled. When VAUX reaches 7 V, the outputs are disabled and the start- up regulator turns ON. This “7- 11” mode of operation is known as Dynamic Self Supply (DSS). The VAUX pin can be biased externally above 7 V once the outputs are enabled to prevent Figure 29. Recommended VAUX Configuration Power to the controller while operating in the self-bias or DSS mode is provided by CAUX. Therefore, CAUX must be sized such that a VAUX voltage greater than 7 V is maintained while the outputs are switching and the converter reaches regulation. Also, the VAUX discharge time (from 11 V to 7 V) must be greater that the soft start charge period to assure the converter turns ON. The start-up circuit is rated at a maximum voltage of 150 V. If the device operates in the DSS mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. http://onsemi.com 12 NCP1560 Line Under/Over Voltage Shutdown The NCP1560 incorporates a line under/over voltage shutdown (UV/OV) circuit. The under voltage (UV) threshold is 1.52 V and the over voltage threshold (OV) is 3.61 V, for a ratio of 1:2.4. The UV/OV circuit can be biased using an external resistor divider from the input line. The resistor divider must be sized to enable the controller once Vin is within the required operating range. If the UV or OV threshold is reached, the soft start capacitor is discharged, and the outputs are immediately disabled with no overlap delay as shown in Figure 30. Also, if an UV condition is detected, the 5.0 V Reference Supply is disabled. VAUX(on) VAUX VAUX(off) 0V VOV UV/OV Voltage VUV 0V UV or OV Fault Propagation delay to outputs (tUV or tOV) OUT2 0V OUT1 0V Figure 30. UV/OV Fault Timing Diagram http://onsemi.com 13 NCP1560 The UV/OV pin can also be used to implement a remote enable/disable function. Biasing the UV/OV pin below its UV threshold disables the converter. Once the UV or OV condition is removed and VAUX reaches 11 V, the controller initiates a soft start cycle. Figure 31 shows the relationship between the UV/OV voltage, the outputs and the soft start voltage. SOFT START VAUX(on) VAUX VAUX(off) 0V 2V UV/OV Voltage 0V Soft Start Voltage 0V OUT2 0V OUT1 0V Figure 31. Soft Start Timing Diagram (Using Auxiliary Winding) Feedforward Ramp Generator The NCP1560 incorporates line feedforward (FF) to compensate for changes in line voltage. A FF Ramp proportional to Vin is generated and compared to VEA. If the line voltage changes, the FF Ramp slope changes accordingly. The duty cycle will be adjusted immediately instead of waiting for the line voltage change to propagate around the system and be reflected back on VEA. A resistor between Vin and the FF pin (RFF) sets the feedforward current (IFF). The FF Ramp is generated by charging an internal 10 pF capacitor (CFF) with a constant current proportional to IFF. The FF Ramp is finished (capacitor is discharged) once the Oscillator Ramp reaches 2.0 V. Please refer to Figure 2 for a functional drawing of the Feedforward Ramp generator. IFF is usually a few hundred microamps, depending on the operating frequency and the required duty cycle. If the operating frequency and maximum duty cycle are known, IFF is calculated using the equation below: IFF Figure 18 shows the relationship between IFF and DCMAX. For example, if a system is designed to operate at 300 kHz, with a 60% maximum duty cycle at 36 V, the DCMAX pin can be grounded and IFF is calculated as follows: 1 T1 3.33 s 300 kHz f ton(max) DCMAX T 0.6 3.33 s 2.0 s IFF CFF VDC(inv) 125 k 6.7 k ton(max) 10 pF 0.888 V 125 k 82.8 A 6.7 k 2.0 s As the minimum line voltage is 36 V, the required feedforward resistor is calculated using the equation below: V RFF in 12.0 k 36 V 12.0 k 434 k IFF 82.8 A From the above calculations it can be observed that IFF is controlled predominantly by the value of RFF, as the resistance seen into the FF pin is only 12 k. If a tight maximum duty cycle control over temperature is required, RFF should have a low thermal coefficient. CFF VDC(inv) 125 k 6.7 k ton(max) where VDC(inv) is the voltage on the inverting input of the Max DC Comparator and ton(max) is the maximum ON time. http://onsemi.com 14 NCP1560 Current Limit The NCP1560 has two over current protection modes, cycle by cycle and cycle skip. It allows the NCP1560 to handle momentary and hard shorts differently for the best tradeoff in performance and safety. The outputs are disabled typically 90 ns after a current limit fault is detected. The cycle by cycle mode terminates the conduction cycle (reducing the duty cycle) if the voltage on the CS pin exceeds 0.48 V. The cycle skip mode is enabled if the voltage on the CS pin reaches 0.57 V. Once a cycle skip fault is detected, the outputs are disabled, the soft start and cycle skip capacitors are discharged, and the cycle skip period (TCSKIP) commences. NORMAL OPERATION ILIM1 ILIM2 The cycle skip period is set by an external capacitor (CCSKIP). Once a cycle skip fault is detected, the cycle skip capacitor is discharged followed by a charge cycle. The charge current is 12.3 A. The cycle skip period ends when the voltage on the cycle skip capacitor reaches 2.0 V. The cycle skip capacitor is calculated using the equation below: CCSKIP TCSKIP 12.3 A 2V Using the above equation, a cycle skip period of 11.0 s requires a cycle skip capacitor of 68 pF. The differences between the cycle by cycle and cycle skip modes are observed in Figure 32. SOFT START RESET NORMAL OPERATION VAUX(on) VAUX VAUX(off) 0V OUT2 0V OUT1 0V ILIM2 ILIM1 CS Voltage 0V TCSKIP 0V Cycle Skip Voltage Figure 32. Over Current Faults Timing Diagram Once the cycle skip period is complete and VAUX reaches 11 V, a soft start sequence commences. The possible minimum OFF time is set by CCSKIP. However, the actual OFF time is generally greater than the cycle skip period because it is the cycle skip period added to the time it takes VAUX to reach 11 V. The voltage on the RT pin is laser trim adjusted during manufacturing to 1.3 V for an RT of 101 k. A current set by RT generates an Oscillator Ramp by charging an internal 10 pF capacitor as shown in Figure 2. The period ends (capacitor is discharged) once the Oscillator Ramp reaches 2.0 V. If RT increases, the current and the Oscillator Ramp slope decrease, thus reducing the frequency. If RT decreases, the opposite effect is obtained. Figure 16 shows the relationship between RT and the oscillator frequency. Oscillator The NCP1560 oscillator frequency is set by a single external resistor connected between the RT pin and GND. The oscillator is designed to operate up to 500 kHz. http://onsemi.com 15 NCP1560 Maximum Duty Cycle A dedicated internal comparator limits the maximum ON time of OUT1 by comparing the FF Ramp to VDC(inv). If the FF Ramp voltage exceeds VDC(inv), the output of the Max DC Comparator goes high. This will reset the Output Latch, thus turning OFF the outputs and limiting the duty cycle. Duty cycle is defined as: 5.0 V Reference The NCP1560 includes a precision 5.0 V reference output. The reference output is biased directly from VAUX and it can supply up to 6 mA. Load regulation is 50 mV and line regulation is 100 mV within the specified operating range. It is recommended to bypass the reference output with a 0.1 F ceramic capacitor. The reference output is disabled when an UV fault is present. t DC on ton f T PWM Comparator The output of an external error amplifier is compared to the FF Ramp by means of the PWM Comparator. The external error amplifier drives the VEA input. There is a 0.7 V offset between the VEA input and the PWM Comparator inverting input. The offset is provided by a series diode and resistor. If the voltage on the VEA input is below 0.7 V, the outputs are disabled. The PWM Comparator controls the duty cycle by turning OFF the outputs once the FF Ramp voltage exceeds the offset VEA voltage. The VEA range required to control the DC from 0% to DCMAX is given by the equation below: Therefore, the maximum ON time can be set to yield the desired DC if the operating frequency is known. The maximum ON time is set by adjusting the FF Ramp to reach VDC(inv) in a time equal to ton(max) as shown in Figure 33. The maximum ON time should be set for the minimum line voltage. As line voltage increases, the slope of the FF Ramp increases. This reduces the duty cycle below DCMAX, which is a desirable feature as the duty cycle is inversely proportional to line voltage. Oscillator Ramp VEA(L) VEA 2V 0V where, VEA(L) is the PWM comparator lower input threshold. T FF Ramp Soft Start Soft start (SS) allows the converter to gradually reach steady state operation, thus reducing start-up stress and surges on the system. The duty cycle is limited during a soft start sequence by comparing the Oscillator Ramp to the SS voltage (VSS) by means of the Soft Start Comparator. A 6.2 A current source starts to charge the capacitor on the SS pin once faults are removed and VAUX reaches 11 V. The Soft Start Comparator controls the duty cycle while the SS voltage is below 2.0 V. Once VSS reaches 2.0 V, it exceeds the Oscillator Ramp voltage and the Soft Start Comparator does not limit the duty cycle. Figure 34 shows the relationship between the outputs duty cycle and the soft start voltage. VDC(inv) 0V ton(max) Figure 33. Maximum ON Time Limit Waveforms An internal resistor divider from a 2.0 V reference is used to set VDC(inv). If the DCMAX pin is grounded, VDC(inv) is 0.88 V. If the pin is floating, VDC(inv) is 1.19 V. This is equivalent to 60% or 80% of a 1.5 V FF Ramp. VDC(inv) can be adjusted to other values by using an external resistor network on the DCMAX pin. For example, if the minimum line voltage is 36 V, RFF is 434 k, operating frequency is 300 kHz and a maximum duty cycle of 70% is required, VDC(inv) is calculated as follows: VDC(inv) VDC(inv) IFF DC 186.56 VEA(L) pf f IFF 6.7 k ton(max) CFF 125 k Oscillator Ramp 88.2 A 6.7 k 2.33 s 1.10 V 10 pF 125 k This can be achieved by connecting a 45.3 k resistor from the DCMAX pin to GND. The maximum duty cycle limit can be disabled connecting a 100 k resistor between the DCMAX and VREF pins. OUT2 OUT1 Figure 34. Soft Start Timing Diagram http://onsemi.com 16 VSS NCP1560 If the soft start period is too long, VAUX may discharge to 7 V before the converter output is completely in regulation causing the outputs to be disabled. If the converter output is not completely discharged when the outputs are re-enabled, the converter will eventually reach regulation exhibiting a non-monotonic start-up behavior. But, if the converter output is completely discharged when the outputs are re-enabled, the cycle may repeat and the converter will not start. In the event of an UV, OV, or cycle skip fault, the soft start capacitor is discharged. Once the fault is removed, a soft start cycle commences. The soft start steady state voltage is approximately 4.1 V. The control outputs are biased from VAUX. The outputs can supply up to 10 mA each and their high state voltage is usually 0.2 V below VAUX. Therefore, the auxiliary supply voltage should not exceed the maximum input voltage of the driver stage. If the control outputs need to drive a large capacitive load, a driver should be used between the NCP1560 and the load. ON Semiconductor’s MC33152 is a good selection for an integrated driver. Figures 27 and 28 shows the relationship between the output’s rise and fall times vs capacitive load. Time Delay The overlap delay between the outputs is set connecting a resistor (RD) between the tD and VREF pins. A minimum overlap delay of 80 ns is obtained when RD is 60 k. If RD is not present, the delay is 200 ns. The output duty cycle can be adjusted from 0% to 85% selecting appropriate values of RFF and VDC(inv). It should be noted that the overlap delay may cause OUT2 to reach 100% duty cycle. Therefore, if OUT2 is used, the maximum duty cycle of OUT2 needs to be kept below 100%. The maximum overlap delay, tD(max), depends on the maximum duty cycle and frequency of operation. The maximum overlap delay is calculated using the equation below. Control Outputs The NCP1560 has two in-phase control outputs, OUT1 and OUT2, with adjustable overlap delay (tD). OUT2 precedes OUT1 during a low to high transition and OUT1 precedes OUT2 at any high to low transition. Figure 35 shows the relationship between OUT1 and OUT2. tD (Leading) tD (Trailing) OUT1 tD(max) OUT2 (1 DC) 2ƒ For example, if the converter operates at a frequency of 300 kHz with a maximum duty cycle of 80%, the maximum allowed overlap delay is 333 ns. However, this is a theoretical limit and variations over the complete operating range should be considered when selecting the overlap delay. Figure 35. Control Outputs Timing Diagram Generally, OUT1 controls the main switching element. Output 2, once inverted, can control a synchronous rectifier. The overlap delay prevents simultaneous conduction. Output 2 can also be used to control an active clamp reset. Once VAUX reaches 11 V, the internal start-up circuit is disabled and the One Shot Pulse Generator is enabled. If no faults are present, the outputs turn ON. Otherwise, the outputs remain OFF until the fault is removed and VAUX reaches 11 V again. Additional Information A 100 W DC-DC converter for telecom systems was designed and implemented using the NCP1560. The converter design is discussed in Application Note AND8105/D. http://onsemi.com 17 NCP1560 PACKAGE DIMENSIONS SO-16 D SUFFIX CASE 751B-05 ISSUE J -A16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 The product described herein (NCP1560) may be covered by one or more U.S. patents. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 18 NCP1560/D