NTLUD3C20CZ Product Preview Small Signal MOSFET 12 V, Complementary, 2.0 x 2.0 mm UDFN Package www.onsemi.com Features • • • • Advanced Trench Complementary MOSFET Low RDS(on) Low Profile UDFN 2.0x2.0x0.55mm for Board Space Saving These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant V(BR)DSS RDS(on) Max 23 mW @ 4.5 V 26 mW @ 3.3 V N−Channel 12 V 59 mW @ 1.8 V 44 mW @ −4.5 V • Power Load Switch • Load Switch with Level Shift • Optimized for Power Management in Ultra Portable Devices PMOS VDSS NMOS Gate−to−Source Voltage N−Channel Continuous Drain Current (Note 1) P−Channel Continuous Drain Current (Note 1) Power Dissipation (Note 1) PMOS 175 mW @ −1.8 V Value VGS ±8.0 8.1 Steady State TA = 25°C −4.6 tv5s TA = 25°C Steady State TA = 25°C tv5s TA = 25°C PMOS Source Current (Body Diode) Operating Junction and Storage Temperature Lead Temperature for Soldering Purposes (1/8” from case for 10 s) ID ID 4.6 PMOS mA −3.3 mA −5.9 1.40 mW PD 2.29 mW MARKING DIAGRAM 21 IDM IS mA 14 A −1.6 TJ, TSTG TL UDFN6 CASE 527AD 1.6 −55 to 150 °C 260 °C This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. November, 2015 − Rev. P1 D2 S1 NMOS Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq), 1 oz. Cu. © Semiconductor Components Industries, LLC, 2015 G2 6.4 TA = 25°C tp = 10 ms G1 V ±8.0 tv5s TA = 85°C S2 D1 Unit V 12 TA = 25°C NMOS Pulsed Drain Current SYMBOLS AND PIN CONNECTIONS Steady State TA = 85°C −4.6 mA 75 mW @ −2.5 V 12 NMOS Drain−to−Source Voltage 55 mW @ −3.3 V P−Channel −12 V MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Symbol 6.4 mA 31 mW @ 2.5 V Applications Parameter ID Max 1 1 AAMG G AA = Specific Device Code M = Date Code (Note: Microdot may be in either location) ORDERING INFORMATION Device NTLUD3C20CZTAG Package UDFN6 NTLUD3C20CZTBG (Pb−Free) Shipping† 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTLUD3C20CZ/D NTLUD3C20CZ THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient – Steady State, Minimum Pad (Note 1) Symbol Value Unit RqJA 89.3 °C/W Junction−to−Ambient – t v 5 s (Note 1) 54.6 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol FET Test Condition Min Typ Max Unit OFF CHARACTERISTICS N Drain−to−Source Breakdown Voltage V(BR)DSS Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS / TJ Zero Gate Voltage Drain Current P VGS = 0 V ID = −250 mA −12 V TBD P TBD N VGS = 0 V, VDS = 9.6 V P VGS = 0 V, VDS = −9.6 V IDSS IGSS 12 N N Gate−to−Source Leakage Current ID = 250 mA TJ = 25°C 1 TJ = 125°C 10 TJ = 25°C −1 TJ = 125°C −10 mA mA ±100 VDS = 0 V, VGS = ±8.0 V P mV/°C ±100 nA ON CHARACTERISTICS (Note 2) N Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH) VGS(TH) / TJ P 1.0 ID = −250 mA −0.4 −1.0 P TBD V mV/°C VGS = 4.5 V ID = 5 A 18 23 VGS = 3.3 V ID = 5 A 21 26 VGS = 2.5 V ID = 4.6 A 25 31 VGS = 1.8 V ID = 4 A 47 59 VGS = −4.5 V, ID = −4 A 35 44 VGS = −3.3 V ID = −4 A 44 55 VGS = −2.5 V, ID = −3 A 60 75 VGS = −1.8 V ID = −1 A 140 175 N VDS = 5 V ID = 5 A TBD P VDS = −5 V ID = −4 A TBD RDS(on) gFS 0.4 TBD P Forward Transconductance ID = 250 mA N N Drain−to−Source On Resistance VGS = VDS mW S CAPACITANCES Input Capacitance CISS 1074 f = 1 MHz, VGS = 0 V VDS = 9.6 V Output Capacitance COSS Reverse Capacitance CRSS 139 Input Capacitance CISS 1201 Output Capacitance COSS Reverse Capacitance CRSS N f = 1 MHz, VGS = 0 V VDS = −9.6 V P 147 pF 150 145 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Switching characteristics are independent of operating junction temperatures www.onsemi.com 2 NTLUD3C20CZ ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol FET Test Condition Min Typ Max Unit CHARGES Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) 10.8 0.8 N VGS = 4.5 V, VDS = 9.6 V, ID = 5 A Gate−to−Source Charge QGS 1.9 Gate−to−Drain Charge QGD 2.4 Total Gate Charge QG(TOT) 12.6 Threshold Gate Charge QG(TH) nC 0.9 P VGS = −4.5 V, VDS = −9.6 V, ID = −4 A Gate−to−Source Charge QGS 1.7 Gate−to−Drain Charge QGD 2.8 td(ON) 7.6 SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) N VGS = 4.5 V, VDS = 9.6 V, RG = 1.0 W 22 22 tf 4.0 td(ON) 6.8 tr td(OFF) P VGS = −4.5 V, VDD = −9.6 V, RG = 1.0 W tf ns 18 33 9.9 DRAIN−SOURCE DIODE CHARACTERISTICS N Forward Diode Voltage VGS = 0 V, IS = 1.0 mA VSD P VGS = 0 V, IS = −1.0 mA TJ = 25°C 0.8 TJ = 125°C TBD TJ = 25°C −0.8 TJ = 125°C TBD 1.1 −1.1 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Switching characteristics are independent of operating junction temperatures www.onsemi.com 3 NTLUD3C20CZ PACKAGE DIMENSIONS UDFN6 2x2, 0.65P CASE 517BF ISSUE B D PIN ONE REFERENCE 0.10 C ÍÍÍ ÍÍÍ ÍÍÍ 0.10 C ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ A B EXPOSED Cu PLATING L TOP VIEW A A3 0.08 C L L1 0.10 C DETAIL A OPTIONAL CONSTRUCTIONS A1 C SIDE VIEW 0.10 C A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e F K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.25 0.35 2.00 BSC 0.57 0.77 2.00 BSC 0.90 1.10 0.65 BSC 0.15 BSC 0.25 REF 0.20 0.30 --0.10 SEATING PLANE B D2 F D2 DETAIL A DETAIL B OPTIONAL CONSTRUCTIONS E DETAIL B NOTE 4 MOLD CMPD 1 3 L E2 0.10 C A 6 K 4 6X b 0.10 C A e BOTTOM VIEW B 0.05 C B NOTE 3 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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