MC10ELT24 D

MC10ELT24, MC100ELT24
5V TTL to Differential
ECL Translator
Description
The MC10ELT/100ELT24 is a TTL to differential ECL translator.
Because ECL levels are used a +5 V, −5.2 V (or −4.5 V) and ground
are required. The small outline 8−lead package and the single gate of
the ELT24 makes it ideal for those applications where space,
performance and low power are at a premium.
The 100 Series contains temperature compensation.
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MARKING DIAGRAMS*
8
8
Features
•
•
•
•
•
1
0.8 ns tPHL, 0.95 ns tPLH Typical Propagation Delay
PNP TTL Inputs for Minimal Loading
Flow Through Pinouts
Operating Range: VCC = 4.5 V to 5.5 V; VEE = −4.2 V to −5.5 V with
GND = 0 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
8
HLT24
ALYW
G
SOIC−8
D SUFFIX
CASE 751
1
1
8
8
1
1
8
HT24
ALYWG
G
1
KT24
ALYWG
G
2T MG
G
5E MG
G
TSSOP−8
DT SUFFIX
CASE 948R
KLT24
ALYW
G
1
4
1
4
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
DFN8
MN SUFFIX
CASE 506AA
H
K
5E
2T
M
= MC10
= MC100
= MC10
= MC100
= Date Code
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 11
1
Publication Order Number:
MC10ELT24/D
MC10ELT24, MC100ELT24
Table 1. PIN DESCRIPTION
VEE
1
8
VCC
Pin
Function
Q, Q
ECL Differential Outputs*
D
TTL Input
VCC
Positive Supply
VEE
Negative Supply
GND
Ground
NC
No Connect
EP
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically
connect to the most negative supply (GND) or
leave unconnected, floating open.
TTL
D
2
7
Q
ECL
NC
NC
3
6
4
5
Q
GND
*Output state undetermined when inputs are open.
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
Pb−Free Pkg
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
51 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10ELT24, MC100ELT24
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
Positive Power Supply
Parameter
GND = 0 V
Condition 1
VEE = −5.0 V
7
V
VEE
Negative Power Supply
GND = 0 V
VCC = +5.0 V
−8
V
VIN
Input Voltage
GND = 0 V
VI v VCC
0 to VCC
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SO−8
SO−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SO−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44 $5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 260°C
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
Pb−Free
Condition 2
(Note 2)
DFN8
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. 10ELT SERIES NECL OUTPUT DC CHARACTERISTICS VCC = 5.0 V; VEE = −5.0 V; GND = 0 V (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
ICC
VCC Power Supply Current
7.0
4.5
7.0
7.0
mA
IEE
Power Supply Current
18
12.5
18
18
mA
VOH
Output HIGH Voltage (Note 4)
−1080
−990
−890
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 4)
−1950
−1800
−1650
−1950
−1790
−1630
−1950
−1773
−1595
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Output parameters vary 1:1 with GND. VCC can vary 4.5 V / 5.5 V. VEE can vary −4.2 V / −5.5 V.
4. Outputs are terminated through a 50 W resistor to GND − 2 V.
Table 5. 100ELT SERIES NECL OUTPUT DC CHARACTERISTICS VCC = 5.0 V; VEE = −5.0 V; GND = 0 V (Note 5)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
ICC
VCC Power Supply Current
7.0
4.5
7.0
7.0
mA
IEE
Power Supply Current
18
12.5
18
18
mA
VOH
Output HIGH Voltage (Note 6)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 6)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. Output parameters vary 1:1 with GND. VCC can vary 4.5 V / 5.5 V. VEE can vary −4.2 V / −5.5 V.
6. Outputs are terminated through a 50 W resistor to GND − 2 V.
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3
MC10ELT24, MC100ELT24
Table 6. TTL INPUT DC CHARACTERISTICS VCC = 4.5 V to 5.5 V; VEE = −4.2 V to −5.5 V; GND = 0.0 V; TA = −40°C to +85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
20
mA
IIH
Input HIGH Current
VIN = 2.7 V
IIHH
Input HIGH Current
VIN = 7.0 V
100
mA
IIL
Input LOW Current
VIN = 0.5 V
−0.6
mA
VIK
Input Clamp Diode Voltage
IIN = −18 mA
−1.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 7. AC CHARACTERISTICS VCC = 4.5 V to 5.5 V; VEE = −4.2 V to −5.5 V; GND = 0.0 V
−40°C
Symbol
Min
Characteristic
Typ
25°C
Max
Min
85°C
Typ
Max
Min
Typ
Max
400
Unit
fmax
Maximum Toggle Frequency
MHz
tPLH
Propagation Delay (Note 7)
1.5 V to 50%
0.5
2.0
0.5
0.95
2.0
0.5
2.0
ns
tPHL
Propagation Delay (Note 7)
1.5 V to 50%
0.5
2.0
0.5
0.8
2.0
0.5
2.0
ns
tJITTER
Random Clock Jitter (RMS)
tr/tf
Output Rise/Fall Time
(20−80%)
2.5
0.25
1.25
ps
0.25
1.25
0.25
1.25
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
7. Specifications for standard TTL input signal.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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4
MC10ELT24, MC100ELT24
ORDERING INFORMATION
Package
Shipping†
MC10ELT24DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC10ELT24DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC10ELT24DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC10ELT24DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC10ELT24MNR4G
DFN8
(Pb−Free)
1000 / Tape & Reel
MC100ELT24DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100ELT24DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100ELT24DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100ELT24DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100ELT24MNR4G
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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5
MC10ELT24, MC100ELT24
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC10ELT24, MC100ELT24
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
5
0.25 (0.010)
B
−U−
L
0.15 (0.006) T U
M
M
4
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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7
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC10ELT24, MC100ELT24
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
D
PIN ONE
REFERENCE
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.10 C
2X
A
B
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
A1
C
SIDE VIEW
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
8X
DETAIL A
1.30
D2
1
8X
L
8
5
8X
e/2
e
0.50
PACKAGE
OUTLINE
4
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
0.90
2.30
1
b
0.10 C A B
0.05 C
8X
0.30
NOTE 3
0.50
PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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8
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For additional information, please contact your local
Sales Representative
MC10ELT24/D