MC100EPT622 D

MC100EPT622
3.3V LVTTL/LVCMOS to
LVPECL Translator
Description
The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The device has an OR−ed enable input which
can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
(ENTTL). If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel−to−channel skew.
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MARKING
DIAGRAMS*
Features
•
•
•
•
•
•
•
•
450 ps Typical Propagation Delay
Maximum Frequency > 1.5 GHz Typical
MC100
EPT622
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
PECL Mode
32
Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
1
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Inputs Open
1
MC100
EPT622
AWLYYWWG
G
The 100 Series Contains Temperature Compensation
Pb−Free Packages are Available*
32
1
QFN32
MN SUFFIX
CASE 488AM
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Table 1. TRUTH TABLE
ENPECL
ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
MC100EPT622/D
MC100EPT622
VCCO D4
D3
D2 VEE
D1
ENPECL
D0 VCCO
ENTTL
D0
25
26
27
28
29
30
31
32
Q4
17
8
VEE
Q3
18
7
ENPECL
VCCO
19
6
ENTTL
Q2
20
5
D9
MC100EPT622
Q1
21
4
D8
Q0
22
3
D7
VCCO
23
2
D6
24
1
D5
VCCO
16
15
14
13
12
11
10
9
32
31
D2 VEE
D1
D0 VCCO
30
29
27
26
28
25
24
VCCO
D6
2
23
Q0
D7
3
22
Q1
D8
4
21
Q2
D9
5
20
VCCO
ENTTL
6
19
Q3
ENPECL
7
18
Q4
VEE
8
17
VCCO
10
11
12
13
Q8
Q7
VCC Q6
14
15
LVCMOS/TTL
D4
D7
D8
1
9
D3
(EP)
D5
VCCO Q9
D2
D6
Figure 1. 32−Lead LQFP Pinout (Top View) Exposed Pad
D3
D1
D5
VCCO Q9 Q8 Q7 VCC Q6 Q5 VCCO
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
VCCO D4
Q0
D9
Q1
Q2
Q3
Q4 LVPECL
Q5
Q6
Q7
Q8
Q9
Figure 2. Logic Symbol
16
Q5 VCCO
Figure 3. 32−Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Function
D0:9
Data Input (TTL)
Q0:9
Data Outputs (PECL)
ENTTL
Enable Control (TTL)
ENPECL
Enable Control (PECL)
VCC, VCCO
Positive Supply
VEE
Ground
EP
The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out
of the package. THe exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to VEE.
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2
MC100EPT622
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack
LQFP−32
QFN−32
Flammability Rating
Oxygen Index: 28 to 34
> 2 kV
> 150 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 2
N/A
Level 2
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
596 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
Power Supply
VEE = 0 V
VI
Input Voltage
VEE = 0 V
Iout
Output Current
Continuous
Surge
TA
Condition 2
Rating
Unit
5
V
5 to 0
V
50
100
mA
mA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
32 LQFP
12 to 17
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
Tsol
Wave Solder
265
265
°C
VI VCC
Pb
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN= 2.7 V
25
mA
IIHH
Input HIGH Current MAX
VIN= VCC
100
mA
IIL
Input LOW Current
VIN= 0.5 V
−0.6
mA
VIK
Input Clamp Voltage
IIN= −18 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
−1.2
−0.9
V
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC100EPT622
Table 5. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN= 2420 mV
150
mA
IIL
Input LOW Current
VIN= 1490 mV
200
mA
VIH
Input HIGH Voltage
2075
2420
mV
VIL
Input LOW Voltage
1490
1675
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
85
115
145
90
120
155
95
130
155
mA
IEE
Power Supply Current
VOH
Output High Voltage
(Note 2)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output Low Voltage
(Note 2)
1355
1520
1700
1355
1520
1700
1355
1520
1700
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC.
2. All loading with 50 W to VCC−2.0 V.
Table 7. AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 3)
−40°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 4)
tPLH,
tPHL
Propagation Delay to Output (Figure 5, Note 4)
D to Q
ENPECL to Q
ENTTL to Q
tJITTER
Random Clock Jitter (RMS)
(See Figure 4)
tr / tf
Output Rise/Fall Times
(20% − 80%)
TSKEW
Duty Cycle Skew (Note 5)
D to Q
ENPECL to Q
ENTTL to Q
25°C
Min
Typ
1.0
1.5
100
150
300
450
500
450
800
875
800
0.7
3.0
200
450
120
200
120
100
375
775
400
275
100
Channel 0−7
Channel 8−9
Max
85°C
Min
Typ
1.0
1.5
100
150
300
500
500
500
875
875
800
0.7
3.0
200
250
120
200
120
100
375
775
400
275
100
Max
Min
Typ
1.0
1.5
100
200
300
500
550
500
800
925
800
0.7
3.0
ps
200
300
ps
120
200
120
100
375
775
400
275
100
Max
Unit
GHz
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V.
4. 1.5 V to 50% point of the output.
5. Duty cycle skew |tPLH − tPHL| on the specific path.
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4
MC100EPT622
2400
10.0
9.0
8.0
VCC = 3.3 V
TA = 25°C
2000
VOH (mV)
7.0
6.0
VOL (mV)
1800
5.0
1600
4.0
1400
3.0
RMS Jitter (ps)
1200
RMS JITTER (ps)
OUTPUT AMPLITUDE (mV)
2200
2.0
1.0
1000
0.5
1.0
1.5
2.0
0.0
FREQUENCY (GHz)
Figure 4. Average Output Amplitude/Jitter (3.3 V, 255C)
800
700
tPLH, tPHL (ps)
600
500
400
300
200
100
0
tPLH
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
tPHL
CHANNEL
Figure 5. Average Propagation Delay (3.3 V, 255C)
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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5
MC100EPT622
ORDERING INFORMATION
Package
Shipping†
MC100EPT622FA
LQFP−32
250 Units / Tray
MC100EPT622FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100EPT622FAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
MC100EPT622MNG
QFN32
(Pb−Free)
74 Units / Rail
MC100EPT622MNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC100EPT622
PACKAGE DIMENSIONS
A1
A
32
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
25
0.20 (0.008) AB T-U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
AC T-U Z
AE
DETAIL Y
ÉÉ
ÉÉ
ÉÉ
ÉÉ
−Z−
9
S1
4X
0.20 (0.008) AC T-U Z
F
S
8X
G
J
R
D
DETAIL AD
−AB−
SECTION AE−AE
C E
−AC−
H
W
K
X
DETAIL AD
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7
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M_
M
N
9
0.20 (0.008)
B1
MC100EPT622
PACKAGE DIMENSIONS
QFN32 5x5, 0.5 P
CASE 488AM−01
ISSUE O
A
B
ÉÉ
ÉÉ
D
PIN ONE
LOCATION
2X
0.15 C
2X
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
EXPOSED PAD
16
K
32 X
17
SOLDERING FOOTPRINT*
8
5.30
E2
3.20
1
24
32
32 X
0.63
25
32 X b
0.10 C A B
e
3.20
0.05 C
5.30
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100EPT622/D