ONSEMI MC100EPT622

MC100EPT622
3.3VLVTTL/LVCMOS to
LVPECL Translator
The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The device has an OR- ed enable input which
can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
(ENTTL). If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel- to- channel skew
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MARKING
DIAGRAM*
450 ps Typical Propagation Delay
Maximum Frequency > 1.5 GHz Typical
MC100
EPT622
PECL Mode
Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
AWLYYWW
LQFP-32
FA SUFFIX
CASE 873A
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Inputs Open
32
1
The 100 Series Contains Temperature Compensation.
ENPECL
A
WL
YY
WW
ENTTL
D0
D1
D2
Q0
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
Q1
ORDERING INFORMATION
Q2
Device
D3
LVCMOS/TTL
D4
D5
D6
D7
D8
D9
Package
Shipping
LQFP32
250 Unit Trays
MC100EPT622FA
Q3
MC100EPT622FAR2 LQFP32
2000 Tape & Reel
Q4 LVPECL
TRUTH TABLE
Q5
ENPECL
ENTTL
D
Q
H
X
H
H
Q6
Q7
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
Q8
Q9
Figure 1. Logic Symbol
 Semiconductor Components Industries, LLC, 2002
December, 2002 - Rev. 2
1
Publication Order Number:
MC100EPT622/D
VCCO
Q4
Q3
VCCO
Q2
Q1
Q0
VCCO
MC100EPT622
PIN DESCRIPTION
24
23
22
21
20
19
18
17
PIN
FUNCTION
D0:9
Data Input (TTL)
Q0:9
Data Output (PECL)
ENTTL
Enable Control (TTL)
VCCO
25
16
VCCO
D0
26
15
Q5
D1
27
14
Q6
VEE
28
13
VCC
ENPECL
Enable Control (PECL)
D2
29
12
Q7
VCC
Positive Supply
D3
30
11
Q8
VEE
Ground
D4
31
10
Q9
VCCO
32
9
5
D8
D9
6
7
8
VEE
4
ENPECL
3
ENTTL
2
D7
D5
1
D6
MC100EPT622
VCCO
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack
Flammability Rating
Level 2
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
596 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Condition 1
Rating
Units
5
V
5 to 0
V
50
100
mA
mA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VCC
Power Supply
VEE = 0 V
VI
Input Voltage
VEE = 0 V
Iout
Output Current
Continuous
Surge
TA
1. Maximum Ratings are those values beyond which device damage may occur.
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2
Condition 2
VI VCC
MC100EPT622
TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN= 2.7 V
25
A
IIHH
Input HIGH Current MAX
VIN= VCC
100
A
IIL
Input LOW Current
VIN= 0.5 V
-0.6
mA
VIK
Input Clamp Voltage
IIN= -18 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
-1.2
-0.9
V
2.0
V
0.8
V
Max
Unit
PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
IIH
Input HIGH Current
VIN= 2420 mV
150
A
IIL
Input LOW Current
VIN= 1490 mV
200
A
VIH
Input HIGH Voltage
2075
2420
mV
VIL
Input LOW Voltage
1490
1675
mV
PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 2)
-40 °C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
85
115
145
90
120
155
95
130
155
mA
VOH
Input High Voltage
(Note 3)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Input Low Current
(Note 3)
1355
1520
1700
1355
1520
1700
1355
1520
1700
mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
2. Input and output parameters vary 1:1 with VCC.
3. All loading with 50 to VCC- 2.0 V.
AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 4)
-40 °C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2)
tPLH,
tPHL
Propagation Delay to Output (Figure 3, Note 5)
D to Q
ENPECL to Q
ENTTL to Q
tJITTER
Random Clock Jitter (RMS)
(See Figure 2)
tr / tf
Output Rise/Fall Times
(20% - 80%)
TSKEW
Duty Cycle Skew (Note 6)
D to Q
25°C
Min
Typ
Max
1.0
1.5
100
150
300
450
500
450
800
875
800
0.7
3.0
200
450
120
200
120
100
375
775
400
275
85°C
Min
Typ
Max
1.0
1.5
100
150
300
500
500
500
875
875
800
0.7
3.0
200
250
120
200
120
100
375
775
400
275
Min
Typ
Max
1.0
1.5
100
200
300
500
550
500
800
925
800
0.7
3.0
ps
200
300
ps
120
200
120
100
375
775
400
275
Unit
GHz
ps
100
100
100
ps
Channel 0-7
Channel 8-9
ENPECL to Q
ENTTL to Q
4. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V.
5. 1.5 V to 50% point of the output.
6. Duty cycle skew |tPLH - tPHL| on the specific path.
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3
MC100EPT622
2400
10.0
9.0
8.0
VCC = 3.3 V
TA = 25°C
2000
VOH (mV)
7.0
6.0
VOL (mV)
1800
5.0
1600
4.0
1400
3.0
RMS Jitter (ps)
RMS JITTER (ps)
OUTPUT AMPLITUDE (mV)
2200
2.0
1200
1.0
1000
0.5
1.0
1.5
2.0
0.0
FREQUENCY (GHz)
Figure 2. Average Output Amplitude/Jitter (3.3 V, 25C)
800
700
ÉÉ
ÉÉ
É
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
tPLH
tPHL
tPLH, tPHL (ps)
600
500
400
300
200
100
0
CHANNEL
Figure 3. Average Propagation Delay (3.3 V, 25C)
Q
D
Driver
Device
Receiver
Device
50 VTT
VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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4
MC100EPT622
Resource Reference of Application Notes
AN1404
-
ECLinPS Circuit Performance at Non-Standard VIH Levels
AN1405
-
ECL Clock Distribution Techniques
AN1406
-
Designing with PECL (ECL at +5.0 V)
AN1504
-
Metastability and the ECLinPS Family
AN1568
-
Interfacing Between LVDS and ECL
AN1650
-
Using Wire-OR Ties in ECLinPS Designs
AN1672
-
The ECL Translator Guide
AND8001
-
Odd Number Counters Design
AND8002
-
Marking and Date Codes
AND8009
-
ECLinPS Plus Spice I/O Model Kit
AND8020
-
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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5
MC100EPT622
PACKAGE DIMENSIONS
A
32
-T-, -U-, -Z-
LQFP
FA SUFFIX
32-LEAD PLASTIC PACKAGE
CASE 873A-02
ISSUE A
4X
A1
0.20 (0.008) AB T−U Z
25
1
-U-
-TB
V
AE
P
B1
DETAIL Y
17
8
AE
DETAIL Y
9
4X
-Z9
V1
0.20 (0.008) AC T−U Z
S1
S
DETAIL AD
G
-AB0.10 (0.004) AC
AC T−U Z
-ACBASE
METAL
ÉÉ
ÉÉ
ÉÉ
F
8X
M
R
M
N
D
J
0.20 (0.008)
SEATING
PLANE
SECTION AE-AE
W
K
X
DETAIL AD
Q
GAUGE PLANE
H
0.250 (0.010)
C E
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6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MC100EPT622
Notes
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7
MC100EPT622
ECLinPS Plus is a trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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8
MC100EPT622/D