NLSX4302E D

NLSX4302E
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX4302E is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The VCC I/O and VL I/O ports are designed to track two different
power supply rails, VCC and VL respectively. Both the VCC and VL
supply rails are configurable from 1.5 V to 5.5 V. This allows voltage
logic signals on the VL side to be translated into lower, higher or
equal value voltage logic signals on the VCC side, and vice−versa.
The NLSX4302E translator uses external pull−up resistors on the
I/O lines. The external pull−up resistors are used to pull up the I/O
lines to either VL or VCC. The NLSX4302E is an excellent match for
open−drain applications such as the I2C communication bus.
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MARKING
DIAGRAMS
UQFN8
MU SUFFIX
CASE 523AS
E
M
Features
• VL can be Less than, Greater than or Equal to VCC
• Wide VCC Operating Range: 1.5 V to 5.5 V
•
•
•
•
•
•
•
Wide VL Operating Range: 1.5 V to 5.5 V
High−Speed with 20 Mb/s Guaranteed Date Rate
Low Bit−to−Bit Skew
Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V
Non−preferential Powerup Sequencing
Power−Off Protection
Small Space Saving Package: 1.4 mm x 1.2 mm UQFN8 Package
These Devices are Pb−Free and are RoHS Compliant
EM
1
= Specific Device Code
= Date Code
LOGIC DIAGRAM
VL
EN
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
Typical Applications
• I2C, SMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
ORDERING INFORMATION
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 6000 V
− Machine Model (MM) > 400 V
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 0
Device
Package
Shipping†
NLSX4302EBMUTCG
UQFN8
(Pb−Free)
3000/Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
Publication Order Number:
NLSX4302E/D
NLSX4302E
Figure 1. Block Diagram (1 I/O Line)
VL
I/O VL1
2
I/O VL2
3
GND
4
1
5
8
VCC
7
I/O VCC1
6
I/O VCC2
EN
UQFN8
(Top Through View)
Figure 2. Pin−out Diagram
PIN ASSIGNMENT
Pins
FUNCTION TABLE
EN
Operating Mode
VCC
VCC Supply Voltage
Description
L
Hi−Z
VL
VL Supply Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable, Referenced to VL
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
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NLSX4302E
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
High−side DC Supply Voltage
−0.3 to +7.0
V
VL
High−side DC Supply Voltage
−0.3 to +7.0
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.3 to (VCC + 0.3)
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.3 to (VL + 0.3)
V
VEN
Enable Control Pin DC Input Voltage
−0.3 to +7.0
V
II/O_SC
Short−Circuit Duration (I/O VL and I/O VCC to GND)
TSTG
Storage Temperature
40
Continuous
mA
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
High−side Positive DC Supply Voltage
1.5
5.5
V
VL
High−side Positive DC Supply Voltage
1.5
5.5
V
Enable Control Pin Voltage
GND
5.5
V
I/O Pin Voltage (Side referred to VCC)
GND
VCC
V
VIO_VL
I/O Pin Voltage (Side referred to VL)
GND
VL
V
Dt/DV
Input Transition Rise and Fall Rate
10
10
ns/V
+85
°C
VEN
VIO_VCC
TA
I/O VL− or I/O VL− Ports, Push−Pull Driving
Control Input
Operating Temperature Range
−40
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NLSX4302E
DC ELECTRICAL CHARACTERISTICS (VL = 1.5 V to 5.5 V and VCC = 1.5 V to 5.5 V, unless otherwise specified) (Note 1)
−405C to +855C
Symbol
VIH_VL
VIH_VCC I/O High Level I/O_VCC
VIL_VL
I/O Low Level I/O_VL
VIL_VCC I/O Low Level I/O_VCC
VOL
IL
IOFF
Test Conditions (Note 2)
Parameter
I/O High Level I/O_VL
VL (V)
1.65–5.50 1.65–5.50
VL x 0.7
Data Inputs I/O_VCCn
1.65–5.50 1.65–5.50 VCC – 0.4
Data Inputs I/O_VLn
1.65–5.50 1.65–5.50
0.4
Control Input EN
1.65–5.50 1.65–5.50
VL x 0.3
Unit
V
V
V
Data Inputs I/O_VCCn
1.65–5.50 1.65–5.50
0.4
V
Low Level Output
Voltage
VIL = 0.15 V, IOL = 6 mA
1.65–5.50 1.65–5.50
0.4
V
Input Leakage Current
Control Input EN, VIN = VL or GND 1.65–5.50 1.65–5.50
±1
mA
Power−Off Leakage
Current
I/O_VLn,
I/O_VCCn
±2
mA
±2
mA
Tristate Output Mode
Leakage Current
(Note 3)
VIN or VO = 0 to 5.5 V
0
0
0
5.50
5.50
0
I/O_VLn,
I/O_VCCn
VO = 0 to 5.5 V,
EN = VIL
5.50
5.50
I/O_VLn
VO = 0 to 5.5 V,
EN = Don’t Care
5.50
0
0
5.50
Quiescent Supply
Current, Active Mode
(Notes 4, 5)
VL
Quiescent Supply
Current, Standby Mode
(Notes 4, 5)
VL
ICC_OFF Quiescent Supply
Current, Power−Off
(Notes 3, 5)
VCC
VCC
VL
VCC
1.
2.
3.
4.
5.
Max
Control Input EN
I/O_VCCn
ICCZ
Typ
VL – 0.4
I/O_VCCn
ICC
Min
1.65–5.50 1.65–5.50
I/O_VLn
IOZ
VCC (V)
Data Inputs I/O_VLn
VIN = VCCI or GND,
IO = 0, EN = VIH_VL
1.65–5.50 1.65–5.50
5.0
mA
VIN = VCCI or GND,
IO = 0, EN = VIL_VL
1.65–5.50 1.65–5.50
5.0
mA
2.0
mA
VIN = 5.5 V or GND,
IO = 0, EN = Don’t
Care, I/O_VCC to
I/O_VL
VIN = 5.5 V or GND,
IO = 0, EN = Don’t
Care, I/O_VL to
I/O_VCC
0
1.65–5.50
1.65–5.50
0
1.65–5.50
0
0
1.65–5.50
Typical values are for VL = +1.8 V, VCC = +3.3 V and TA = +25°C.
All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
“Don’t care” indicates any valid logic level.
VCCI is the power supply associated with the input side.
Reflects current per supply, VL or VCC.
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NLSX4302E
DYNAMIC OUTPUT ELECTRICAL CHARACTERISTICS
OUTPUT RISE / FALL TIMES (Output Load: CL = 50 pF, RPU = 2.2 kW, push/pull driver, TA = −40°C to +85°C) (Note 6)
VCCO (Note 7)
Parameter
Symbol
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Typ
Typ
Typ
Typ
Unit
tRISE
Output Rise Time, I/O_VLn, I/O_VCCn
6.4
5
6.5
10.7
ns
tFALL
Output Fall Time, I/O_VLn, I/O_VCCn
10
9.5
8.6
9.5
ns
6. Output rise and fall times guaranteed by design and are not production tested.
7. VCCO is the VL or VCC power supply associated with the output side.
MAXIMUM DATA RATE (Output Load: CL = 50 pF, RPU = 2.2 kW, push/pull driver, TA = −40°C to +85°C) (Note 8)
VCC
VL
Parameter
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
I/O_VLn,to I/O_VCCn or I/O_VCCn to
I/O_VLn
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Min
Min
Min
Min
Unit
50
41
31
17
MHz
34
35
36
23
MHz
25
27
30
24
MHz
14
16
22
21
MHz
8. Maximum frequency guaranteed by design and is not production tested.
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NLSX4302E
AC ELECTRICAL CHARACTERISTICS (Output Load: CL = 50 pF, RPU = 2.2 kW, push/pull driver, TA = −40°C to +85°C) (Note 9)
VCC
4.5 to 5.5 V
Symbol
Parameter
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Unit
VL = 4.5 to 5.5 V
tPLH
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
2.5
4.3
3
5
3
6.4
4
8.6
ns
tPHL
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
5
8.1
8
13
8
17.3
15
28.5
ns
tPZL
OE to I/O_Vln, OE to I/O_VCCn
14
19.6
16
20
22
26.5
33
44
ns
tPLZ
OE to I/O_Vln, OE to I/O_VCCn
24
31.4
25
32
24
31.8
28
36.2
ns
tskew
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn (Note 10)
0.3
0.3
0.5
0.6
0.8
0.8
1.2
1.9
ns
VL = 3.0 to 3.6 V
tPLH
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
2.5
4.7
3
5.4
3
6.5
5
9.3
ns
tPHL
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
7
14.2
6
10.1
8
14.6
15
27
ns
tPZL
OE to I/O_Vln, OE to I/O_VCCn
15
18.8
18
22.3
19
23.5
29
38.3
ns
tPLZ
OE to I/O_Vln, OE to I/O_VCCn
25
34.9
22
27.6
22
27.9
23
28.8
ns
tskew
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn (Note 10)
0.4
0.5
0.5
0.6
0.6
0.7
2.5
3.0
ns
VL = 2.3 to 2.7 V
tPLH
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
3
5.6
4
6
4
7.3
6
10.3
ns
tPHL
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
12
18.1
11
14.1
8
11.9
15
22.1
ns
tPZL
OE to I/O_Vln, OE to I/O_VCCn
16
23.7
17
21.5
25
30
31
36.6
ns
tPLZ
OE to I/O_Vln, OE to I/O_VCCn
28
33.8
26
31
25
30.8
25
30
ns
tskew
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn (Note 10)
0.5
0.7
0.8
1
0.6
0.6
2.3
2.7
ns
VL = 1.65 to 1.95 V
tPLH
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
5
9
5
9.2
6
9.2
7
12.7
ns
tPHL
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn
19
28.3
15
25.5
12
17.3
14
19
ns
tPZL
OE to I/O_Vln, OE to I/O_VCCn
23
32.2
22
26.5
25
32
40
72
ns
tPLZ
OE to I/O_Vln, OE to I/O_VCCn
35
44
32
38.7
33
36.7
30
36.5
ns
tskew
I/O_VLn to I/O_VCCn,
I/O_VCCn to I/O_VLn (Note 10)
0.5
1.1
1.4
1.5
0.8
1.1
2.0
2.5
ns
9. AC characteristics are guaranteed by design and are not production tested.
10. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (I/O_VLn or I/O_VCCn)
and switching with the same polarity (LOW−to−HIGH or HIGH−to−LOW). Skew is defined by applying a single input to the two input channels
and measuring the difference in propagation delays between the output channels.
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NLSX4302E
CAPACITANCE (TA = 25°C)
Symbol
Parameter
Test Condition
Typical
Unit
CIN
Input Capacitance, Control Pin (EN)
VL = VCC = GND
2
pF
CIO
Input / Output Capacitance
(I/O_VLn, I/O_VCCn)
VL = VCC = 5 V,EN = GND, I/O_VLn = I/O_VCCn = 5 V
3
pF
CPD
Power Dissipation Capacitance (Note 11)
VL = VCC = 5 V,EN = 5 V, VIN = 5 V or GND, f = 400 KHz
17
pF
11. CPD is defined as the value of the internal equivalent capacitance per channel.
TEST SETUP AND TIMING DEFINITIONS
Figure 3. AC Test Circuit
Figure 4. Propagation Delays and Tri-State Measurements
Figure 5. Definition of Rise and Fall Times
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NLSX4302E
Figure 6. Definition of Output Skew
Figure 7. Definition of Output Tri-State Times
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NLSX4302E
APPLICATIONS INFORMATION
Level Translator Architecture
when the transmitter is not transmitting data. Normal
translation operation occurs when the EN pin is equal to a
logic high signal. The EN pin is referenced to the VL supply
and has Overvoltage Tolerant (OVT) protection.
The NLSX4302E auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX4302E consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Each input/output channel requires external pullup
resistors.
Power Supply Guidelines
The sequencing of the power supplies will not damage
the device during the power up operation. In addition, the
I/O VCC and I/O VL pins are in the high impedance state if
either supply voltage is equal to 0 V. For optimal
performance, 0.01 mF to 0.1 mF decoupling capacitors
should be used on the VL and VCC power supply pins.
Ceramic capacitors are a good design choice to filter and
bypass any noise signals on the voltage lines to the ground
plane of the PCB. The noise immunity will be maximized
by placing the capacitors as close as possible to the supply
and ground pins, along with minimizing the PCB
connection traces.
Enable Input (EN)
The NLSX4302E has an Enable pin (EN) that can be
used to minimize the power consumption of the device
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NLSX4302E
PACKAGE DIMENSIONS
UQFN8 1.4x1.2, 0.4P
CASE 523AS
ISSUE A
2X
2X
0.10 C
0.10 C
ALTERNATE
CONSTRUCTIONS
EXPOSED Cu
(A3)
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ÏÏÏ
ÎÎÎ
ÎÎÎ
TOP VIEW
0.05 C
A
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
0.05 C
A1
SIDE VIEW
L2
DETAIL A
DETAIL A
E
DETAIL B
8X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.25 mm FROM THE TERMINAL TIP.
L
L1
ÏÏ
ÏÏ
PIN ONE
REFERENCE
L
A
B
D
2
C
SOLDERING FOOTPRINT*
SEATING
PLANE
1.61
0.55
L
4
1
e
8
1.40
6
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
1.40 BSC
1.20 BSC
0.40 BSC
0.20
0.40
−−−
0.15
0.30
0.50
6X
1
7X
0.45
b
0.10
M
C A B
0.05
M
C
NOTE 3
8X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf . SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product
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fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws
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NLSX4302E/D