NLSX5002 D

NLSX5002
2-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX5002 is a 2-bit configurable dual-supply autosensing
bidirectional level translator that does not require a direction control
pin. The I/O VCC- and I/O VL-ports are designed to track two
different power supply rails, VCC and VL respectively. Both the VCC
and the VL supply rails are configurable from 0.9 V to 4.5 V. This
allows a logic signal on the VL side to be translated to either a higher
or a lower logic signal voltage on the VCC side, and vice-versa.
The NLSX5002 offers the feature that the values of the VCC and
VL supplies are independent. Design flexibility is maximized
because VL can be set to a value either greater than or less than the
VCC supply. In contrast, the majority of competitive auto sense
translators have a restriction that the value of the VL supply must be
equal to less than (VCC - 0.4) V.
The NLSX5002 has high output current capability, which allows
the translator to drive high capacitive loads such as most high
frequency EMI filters. Another feature of the NLSX5002 is that each
I/O_VLn and I/O_VCCn channel can function as either an input or an
output.
An Output Enable (EN) input is available to reduce the power
consumption. The EN pin can be used to disable both I/O ports by
putting them in 3-state which significantly reduces the supply current
from both VCC and VL. The EN signal is referenced to the VL supply.
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MARKING
DIAGRAM
UQFN8
MU SUFFIX
CASE 523AS
A
M
AM
1
= Specific Device Code
= Date Code
ORDERING INFORMATION
Device
NLSX5002BMUTCG
Package
Shipping†
UQFN8 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Features
• Wide VCC, VL Operating Range: 0.9 V to 4.5 V
• VL and VCC are independent
− VL may be greater than, equal to, or less than VCC
• High−Speed with 140 Mb/s Guaranteed Date Rate
•
•
•
•
•
•
for VCC, VL > 1.8 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−Preferential Power−Up Sequencing
Power−Off Protection
Small Packaging: UQFN8, 1.4 mm x 1.2 mm, 0.4 mm Pitch
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
Important Information
• ESD Protection for All Pins:
♦
♦
HBM (Human Body Model) > 8000 V
MM (Machine Model) > 400 V
© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 0
1
Publication Order Number:
NLSX5002/D
NLSX5002
P
One−Shot
VL
+1.8V
R1
+3.6V
VL
+1.8 V System
I/O1
I/On
GND OE
NLSX5002
I/O VL1
VCC
N
One−Shot
VCC
+3.6 V System
I/O VCC1
I/O1
I/O VLn I/O VCCn
EN
GND
I/On
I/O VL
I/O VCC
P
One−Shot
R2
GND
N
One−Shot
Figure 1. Typical Application Circuit
2.5 V
VL
mC
NLSX5002
VCC
Figure 2. Simplified Functional Diagram (1 I/O Line)
3.0 V
2.5 V
Peripheral
mC
1.8 V
VL
NLSX5002
VCC
Peripheral
TX
I/O VL1
I/O VCC1
RX
TX
I/O VL1
I/O VCC1
RX
RX
I/O VL2
I/O VCC2
TX
RX
I/O VL2
I/O VCC2
TX
ANO
EN
GND
ANO
Figure 3. Application Example for VL < VCC
EN
GND
Figure 4. Application Example for VL > VCC
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2
NLSX5002
VL
EN
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
Figure 5. Logic Diagram
VL
1
I/O VL1
2
8
VCC
I/O VL2
3
7
I/O VCC1
GND
4
6
I/O VCC2
5
EN
UQFN8
(Top View)
Figure 6. Pin Assignments
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
EN
Operating Mode
VCC
VCC Input Voltage
L
Hi−Z
VL
VL Input Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
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3
NLSX5002
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
I/O VCC−side DC Supply Voltage
−0.5 to +5.5
V
VL
I/O VL−side DC Supply Voltage
−0.5 to +5.5
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.5 to +5.5
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.5 to +5.5
V
VI
Enable Control Pin DC Input Voltage
−0.5 to +5.5
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
ICC
DC Supply Current Through VCC
$100
mA
IL
DC Supply Current Through VL
$100
mA
IGND
DC Ground Current Through Ground Pin
$100
mA
TSTG
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
I/O VCC−side Positive DC Supply Voltage
0.9
4.5
V
VL
I/O VL−side Positive DC Supply Voltage
0.9
4.5
V
GND
4.5
V
GND
GND
4.5
4.5
V
−55
+125
°C
0
10
ns
VCC
Parameter
VI
Enable Control Pin Voltage (Referenced to VL)
VIO
Bus Input/Output Voltage
TA
Operating Temperature Range
Dt/DV
I/O VCC
I/O VL
Input Transition Rise or Rate
VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V
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4
NLSX5002
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Min
Max
Unit
VL (V)
(Note 3)
I/O VCC Input HIGH Voltage
0.9 – 4.5
0.9 – 4.5
2/3 *
VCC
−
−
2/3 *
VCC
−
V
VILC
I/O VCC Input LOW Voltage
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VCC
−
1/3 *
VCC
V
VIHL
I/O VL Input HIGH Voltage
0.9 – 4.5
0.9 – 4.5
2/3 *
VL
−
−
2/3 * VL
−
V
VILL
I/O VL Input LOW Voltage
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VL
−
1/3 * VL
V
VIH
Control Pin Input HIGH
Voltage
TA = +25°C
0.9 – 4.5
0.9 – 4.5
2/3 *
VL
−
−
2/3 * VL
−
V
VIL
Control Pin Input LOW
Voltage
TA = +25°C
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VL
−
1/3 * VL
V
VOHC
I/O VCC Output HIGH
Voltage
I/O VCC source
current = 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 *
VCC
−
−
0.9 *
VCC
−
V
VOLC
I/O VCC Output LOW Voltage
I/O VCC sink
current = 20 mA
0.9 – 4.5
0.9 – 4.5
−
−
0.2
−
0.2
V
VOHL
I/O VL Output HIGH Voltage
I/O VL source
current = 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 *
VL
−
−
0.9 * VL
−
V
VOLL
I/O VL Output LOW Voltage
I/O VL sink current
= 20 mA
0.9 – 4.5
0.9 – 4.5
−
−
0.2
−
0.2
V
IQVCC
VCC Supply Current
EN = VL, IO = 0 A,
(I/O VCC = 0 V,
I/O VL = 0 V) or
(I/O VCC = VCC,
I/O VL = VL)
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.5
mA
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.5
mA
VCC Tristate Output Mode
Supply Current
TA = +25°C,
EN = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.1
mA
ITS−VL
VL Tristate Output Mode
Supply Current
TA = +25°C,
EN = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.1
mA
IOZ
I/O Tristate Output Mode
Leakage Current
TA = +25°C,
EN = 0V
0.9 – 4.5
0.9 – 4.5
−
−
±1
−
±1.5
mA
II
Control Pin Input Current
TA = +25°C
0.9 – 4.5
0.9 – 4.5
−
−
±1
−
±1
mA
I/O VCC = 0 to 4.5V,
0
0
−
−
1
−
1.5
mA
I/O VL = 0 to 4.5 V
0.9 – 4.5
0
−
−
1
−
1.5
0
0.9 – 4.5
−
−
1
−
1.5
Parameter
VIHC
IQVL
ITS−VCC
IOFF
1.
2.
3.
4.
Max
VCC (V)
(Note 2)
Symbol
VL Supply Current
Power Off Leakage Current
Test Conditions
(Note 1)
−555C to +1255C
Typ
(Note 4)
Min
Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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5
NLSX5002
TIMING CHARACTERISTICS
−555C to +1255C
Symbol
Parameter
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
Min
Typ
(Note 8)
Max
Unit
0.9 – 4.5
0.9 – 4.5
−
−
8.5
ns
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9
1.8
4.5
0.9 – 4.5
−
−
−
37
20
6.0
−
−
−
W
0.9 – 4.5
0.9
1.8
4.5
−
−
−
37
20
6.0
−
−
−
W
0.9 – 4.5
0.9 – 4.5
−
−
40
ns
1.8 – 4.5
1.8 – 4.5
−
−
13
0.9 – 4.5
0.9 – 4.5
−
−
40
1.8 – 4.5
1.8 – 4.5
−
−
13
tR−VCC
I/O VCC Rise Time
CIOVCC = 15 pF
tF−VCC
I/O VCC Fall Time
CIOVCC = 15 pF
tR−VL
tF−VL
ZOVCC
ZOVL
I/O VL Rise Time
I/O VL Fall Time
CIOVL = 15 pF
CIOVL = 15 pF
I/O VCC One−Shot
Output Impedance
I/O VL One−Shot Output Impedance
tPD_VL−VCC Propagation Delay
(Driving I/O VCC)
CIOVCC = 25 pF
tPD_VCC−VL Propagation Delay
(Driving I/O VL)
CIOVL = 25 pF
ns
ns
ns
ns
tSK
Channel−to−Channel
Skew
CIOVCC = 15 pF, CIOVL = 15 pF
(Note 9)
0.9 – 4.5
0.9 – 4.5
−
−
0.15
ns
IIN_PEAK
Input Driver Maximum
Peak Current
EN = VL;
I/O_VCC = 1 MHz Square Wave,
Amplitude = VCC, or
I/O_VL = 1 MHz Square Wave,
Amplitude = VL
0.9 – 4.5
0.9 – 4.5
−
−
5.0
mA
5.
6.
7.
8.
Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
9. Guaranteed by design.
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6
NLSX5002
TIMING CHARACTERISTICS (continued)
−555C to +1255C
Symbol
tEN−VCC
tEN−VL
I/O_VCC Output Enable Time
I/O_VL Output Enable Time
tDIS−VCC I/O_VCC Output Disable Time
tDIS−VL
MDR
Test Conditions
(Note 10)
VCC (V)
(Note 11)
VL (V)
(Note 12)
Min
Typ
(Note 13)
Max
Unit
tPZH
CIOVCC = 15 pF,
I/O_VL = VL
0.9 – 4.5
0.9 – 4.5
−
−
160
ns
tPZL
CIOVCC = 15 pF,
I/O_VL = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
130
tPZH
CIOVL = 15 pF,
I/O_VCC = VCC
0.9 – 4.5
0.9 – 4.5
−
−
160
tPZL
CIOVL = 15 pF,
I/O_VCC = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
130
tPHZ
CIOVCC = 15 pF,
I/O_VL = VL
0.9 – 4.5
0.9 – 4.5
−
−
210
tPLZ
CIOVCC = 15 pF,
I/O_VL = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
175
tPHZ
CIOVL = 15 pF,
I/O_VCC = VCC
0.9 – 4.5
0.9 – 4.5
−
−
210
tPLZ
CIOVL = 15 pF,
I/O_VCC = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
175
CIO = 15 pF
0.9 – 4.5
0.9 – 4.5
50
−
−
1.8 – 4.5
1.8 – 4.5
140
−
−
Parameter
I/O_VL Output Disable Time
Maximum Data Rate
ns
ns
ns
mbps
10. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
12. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
13. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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7
NLSX5002
DYNAMIC POWER CONSUMPTION (TA = +25°C)
Symbol
Parameter
CPD_VL
Power Dissipation
Capacitance
(Referred to VL)
Test Conditions
VL = Input port, VCC = Output Port
CLoad = 0, f = 1 MHz,
EN = VL (Output enabled)
VCC = Input port, VL = Output Port
CLoad = 0, f = 1 MHz,
EN = VL (Output enabled)
CPD_VCC
Power Dissipation
Capacitance
(Referred to VCC)
VL = Input port, VCC = Output Port
CLoad = 0, f = 1 MHz,
EN = VL (Output enabled)
VCC = Input port, VL = Output Port
CLoad = 0, f = 1 MHz,
EN = VL (Output enabled)
VCC (V)
(Note 14)
VL (V)
(Note 15)
Typ
(Note 16)
Unit
0.9
4.5
13
pF
1.5
1.8
7.0
1.8
1.5
6.0
1.8
1.8
6.0
1.8
2.8
7.0
2.5
2.5
6.0
2.8
1.8
6.0
4.5
0.9
10
0.9
4.5
19
1.5
1.8
16
1.8
1.5
16
1.8
1.8
16
1.8
2.8
16
2.5
2.5
16
2.8
1.8
16
4.5
0.9
16
0.9
4.5
16
1.5
1.8
17
1.8
1.5
17
1.8
1.8
17
1.8
2.8
17
2.5
2.5
18
2.8
1.8
18
4.5
0.9
21
0.9
4.5
13
1.5
1.8
6.0
1.8
1.5
7.0
1.8
1.8
7.0
1.8
2.8
6.0
2.5
2.5
7.0
2.8
1.8
7.0
4.5
0.9
15
pF
pF
pF
14. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
15. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
16. Typical values are at TA = +25°C.
17. CPD VL and CPD VCC are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the
VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ≈ ICC(operating) ≈ CPD x VCC x fIN x NSW where ICC = ICC_VCC
+ ICC VL and NSW = total number of outputs switching.
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8
NLSX5002
STATIC POWER CONSUMPTION (TA = +25°C)
Symbol
Parameter
CPD_VL
Power Dissipation
Capacitance
(Referred to VL)
Test Conditions
VL = Input port, VCC = Output Port
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
VCC = Input port, VL = Output Port
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CPD_VCC
Power Dissipation
Capacitance
(Referred to VCC)
VL = Input port, VCC = Output Port
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
VCC = Input port, VL = Output Port
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
VCC (V)
(Note 18)
VL (V)
(Note 19)
Typ
(Note 20)
Unit
0.9
4.5
0.01
pF
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
18. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
19. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
20. Typical values are at TA = +25°C
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pF
pF
pF
NLSX5002
NLSX5002
VL
VCC
NLSX5002
VL
EN
I/O VL
Source
VCC
EN
I/O VL
I/O VCC
I/O VCC
CIOVL
CIOVCC
Source
tRISE/FALL v
3 ns
I/O VL
90%
50%
10%
I/O VCC
tRISE/FALL v 3 ns
90%
50%
10%
tPD_VL−VCC
I/O VCC
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 7. Driving I/O VCC Test Circuit and Timing
tR−VL
Figure 8. Driving I/O VL Test Circuit and Timing
VCC
PULSE
GENERATOR
2xVCC
OPEN
R1
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 9. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
90%
50%
10%
tR
EN
VCC
90%
50%
10%
tPHL
GND
VL
50%
tPZL
Output
50%
tPZH
tF
Output
50%
GND
tPLZ
tPHZ
HIGH
IMPEDANCE
10%
VOL
90%
VOH
Figure 10. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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10
HIGH
IMPEDANCE
NLSX5002
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
VL pins to a high impedance state. Normal translation
operation occurs when the EN pin is equal to a logic high
signal. The EN pin is referenced to the VL supply and has
Over−Voltage Tolerant (OVT) protection.
The NLSX5002 auto−sense translator provides
bi−directional logic voltage level shifting to transfer data
in multiple supply voltage systems. These level translators
have two supply voltages, VL and VCC, which set the logic
levels on the input and output sides of the translator. When
used to transfer data from the I/O VL to the I/O VCC ports,
input signals referenced to the VL supply are translated to
output signals with a logic level matched to VCC. In a
similar manner, the I/O VCC to I/O VL translation shifts
input signals with a logic level compatible to VCC to an
output signal matched to VL.
The NLSX5002 translator consists of bi−directional
channels that independently determine the direction of the
data flow without requiring a directional pin. One−shot
circuits are used to detect the rising or falling input signals.
In addition, the one−shots decrease the rise and fall times
of the output signal for high−to−low and low−to−high
transitions.
Uni−Directional versus Bi−Directional Translation
The NLSX5002 translator can function as a
non−inverting uni−directional translator. One advantage of
using the translator as a uni−directional device is that each
I/O pin can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
The values of the VL and VCC supplies can be set to
anywhere between 0.9 and 4.5 V. Design flexibility is
maximized because VL may be either greater than or less
than the VCC supply. In contrast, the majority of the
competitive auto sense translators has a restriction that the
value of the VL supply must be equal to less than (VCC −
0.4) V.
The sequencing of the power supplies will not damage
the device during power−up operation. In addition, the I/O
VCC and I/O VL pins are in the high impedance state if
either supply voltage is equal to 0 V. For optimal
performance, 0.01 to 0.1 mF decoupling capacitors should
be used on the VL and VCC power supply pins. Ceramic
capacitors are a good design choice to filter and bypass any
noise signals on the voltage lines to the ground plane of the
PCB. The noise immunity will be maximized by placing
the capacitors as close as possible to the supply and ground
pins, along with minimizing the PCB connection traces.
The NLSX5002 translators have a power down feature
that provides design flexibility. The output ports are
disabled when either power supply is off (VL or VCC = 0 V).
This feature causes all of the I/O pins to be in the power
saving high impedance state.
Input Driver Requirements
Auto−sense translators such as the NLSX5002 have a
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi−directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent in the opposite direction. For
proper operation, the input driver to the auto−sense
translator should be capable of driving 5 mA of peak output
current. The bi−directional configuration of the translator
results in both input stages being active for a very short time
period. Although the peak current from the input signal
circuit is relatively large, the average current is small and
consistent with a standard CMOS input stage.
Enable Input (EN)
The NLSX5002 translator has an Enable pin (EN) that
provides tri−state operation at the I/O pins. Driving the
Enable pin to a low logic level minimizes the power
consumption of the device and drives the I/O VCC and I/O
http://onsemi.com
11
NLSX5002
PACKAGE DIMENSIONS
UQFN8 1.4x1.2, 0.4P
CASE 523AS
ISSUE A
ÏÏ
ÏÏ
PIN ONE
REFERENCE
2X
2X
0.10 C
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.25 mm FROM THE TERMINAL TIP.
L
L1
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
0.05 C
EXPOSED Cu
(A3)
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ÏÏÏ
ÎÎÎ
ÏÏÏ
TOP VIEW
DETAIL B
8X
L
A
B
D
A
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
0.05 C
A1
SIDE VIEW
C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
1.40 BSC
1.20 BSC
0.40 BSC
0.20
0.40
−−−
0.15
0.30
0.50
SOLDERING FOOTPRINT*
SEATING
PLANE
1.61
L2
DETAIL A
2
L
4
0.55
1
e
8
1.40
6
BOTTOM VIEW
6X
b
0.10
M
C A B
0.05
M
C
1
NOTE 3
8X
0.25
7X
0.45
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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NLSX5002/D