NLSX3014 D

NLSX3014
4-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3014 is a 4−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O VCC− and I/O
VL−ports are designed to track two different power supply rails, VCC
and VL respectively. The VCC supply rail is configurable from 1.3 V
to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC
− 0.4) V. This allows lower voltage logic signals on the VL side to be
translated into higher voltage logic signals on the VCC side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both VCC and VL. The EN signal is designed to track
VL.
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MARKING
DIAGRAM
1
UQFN12
MU SUFFIX
CASE 523AE
UT = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
LOGIC DIAGRAM
Features
• Wide High−Side VCC Operating Range: 1.3 V to 4.5 V
•
•
•
•
•
•
UTMG
G
Wide Low−Side VL Operating Range: 0.9 V to (VCC − 0.4) V
High−Speed with 100 Mb/s Guaranteed Date Rate for VL > 1.6 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−preferential Powerup Sequencing
Small packaging: 1.7 mm x 2.0 mm UQFN12
This is a Pb−Free Device
VL
EN
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
PIN ASSIGNMENT
EN
VL
1
I/O VL1
11
VCC
2
10
I/O VCC1
I/O VL2
3
9
I/O VCC2
I/O VL3
4
8
I/O VCC3
I/O VL4
5
7
I/O VCC4
12
6
GND
(TOP VIEW)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 4
1
Publication Order Number:
NLSX3014/D
NLSX3014
P
One−Shot
VL
+1.8V
+3.6V
VL
+1.8 V System
NLSX3014
4 kW
VCC
N
One−Shot
+3.6 V System
I/O VL
I/O1
I/On
GND EN
I/O VL1
VCC
I/O VCC1
I/O1
I/O VLn I/O VCCn
EN
GND
I/On
I/O VCC
P
One−Shot
GND
4 kW
N
One−Shot
Figure 1. Typical Application Circuit
Figure 2. Simplified Functional Diagram (1 I/O Line)
(EN = 1)
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
EN
Operating Mode
VCC
VCC Input Voltage
L
Hi−Z
VL
VL Input Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
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2
NLSX3014
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
VCC Supply Voltage
−0.5 to +5.5
V
VL
VL Supply Voltage
−0.5 to +5.5
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.5 to (VCC + 0.3)
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.5 to (VL + 0.3)
V
VEN
Enable Control Pin DC Input Voltage
−0.5 to +5.5
V
IIK
Input Diode Clamp Current
−50
VI < GND
mA
IOK
Output Diode Clamp Current
−50
VO < GND
mA
ICC
DC Supply Current Through VCC
$100
mA
IL
DC Supply Current Through VL
$100
mA
IGND
DC Ground Current Through Ground Pin
$100
mA
TSTG
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VL
Parameter
Min
Max
Unit
VCC Supply Voltage
1.3
4.5
V
VL Supply Voltage
0.9
VCC − 0.4
V
GND
4.5
V
GND
GND
4.5
4.5
V
−40
+85
°C
0
10
ns
VEN
Enable Control Pin Voltage
VIO
Bus Input/Output Voltage
TA
Operating Temperature Range
DI/DV
I/O VCC
I/O VL
Input Transition Rise or Rate
VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V
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3
NLSX3014
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
Test Conditions
(Note 1)
Parameter
VCC (V)
(Note 2)
VL (V)
(Note 3)
Min
Typ
(Note 4)
Max
Unit
VIHC
I/O VCC Input HIGH
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 *
VCC
−
−
V
VILC
I/O VCC Input LOW
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 *
VCC
V
VIHL
I/O VL Input HIGH
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 * VL
−
−
V
VILL
I/O VL Input LOW
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 * VL
V
VIH
Control Pin Input HIGH
Voltage
TA = +25°C
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 * VL
−
−
V
VIL
Control Pin Input LOW
Voltage
TA = +25°C
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 * VL
V
VOHC
I/O VCC Output HIGH
Voltage
I/O VCC Source Current =
20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 *
VCC
−
−
V
VOLC
I/O VCC Output LOW
Voltage
I/O VCC Sink Current = 20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 *
VCC
V
VOHL
I/O VL Output HIGH
Voltage
I/O VL Source Current = 20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 * VL
−
−
V
VOLL
I/O VL Output LOW
Voltage
I/O VL Sink Current = 20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 * VL
V
1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
POWER CONSUMPTION
Symbol
Parameter
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
−405C to +855C
Min
Typ
Max
Unit
IQ−VCC
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4)
VCC
I/O VCCn = VCC or I/O VLn = VL and Io = 0
−
−
1.0
mA
IQ−VL
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4)
VL
I/O VCCn = VCC or I/O VLn = VL and Io = 0
−
−
1.0
mA
−
−
2.0
EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V,
I/O VCCn = VCC or I/O VLn = (VCC −
0.2 V) and Io = 0
ITS−VCC
ITS−VL
IOZ
IEN
< (VCC – 0.2)
VCC Tristate Output
Mode Supply
Current
EN = 0 V
1.3 to 3.6 0.9 to (VCC – 0.4)
−
−
1.0
mA
VL Tristate Output
Mode Supply
Current
EN = 0 V
1.3 to 3.6 0.9 to (VCC – 0.4)
−
−
0.2
mA
−
−
2.0
I/O Tristate Output
Mode Leakage
Current
EN = 0 V
−
−
0.15
−
−
2.0
Output Enable Pin
Input Current
−
−
−
1.0
EN = 0 V
VCC − 0.2
1.3 to 3.6 0.9 to (VCC – 0.4)
EN = 0 V
VCC – 0.2
1.3 to 3.6 0.9 to (VCC – 0.4)
mA
mA
5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 3.6 V.
7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
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NLSX3014
TIMING CHARACTERISTICS
−405C to +855C
Symbol
Parameter
Typ
(Note 11)
Max
Unit
0.9 to (VCC – 0.4)
1.3
1.7
ns
Test Conditions
(Note 8)
VCC (V)
(Note 9)
VL (V)
(Note 10)
Min
tR−VCC
I/O VCC Rise Time
(Output = I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
> 2.0
> 1.6
0.9
1.1
tF−VCC
I/O VCC Falltime
(Output = I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8
1.2
> 2.0
> 1.6
0.6
1.0
1.3 to 4.5
0.9 to (VCC – 0.4)
2.7
3.0
> 2.0
> 1.6
0.8
1.0
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8
1.0
> 2.0
> 1.6
0.7
0.8
tR−VL
tF−VL
I/O VL Risetime
(Output = I/O_VL)
CIOVL = 15 pF
I/O VL Falltime
(Output = I/O_VL)
CIOVL = 15 pF
ns
ns
ns
ZO−VCC
I/O VCC One−Shot
Output Impedance
1.3 to 4.5
0.9 to (VCC – 0.4)
30
W
ZO−VL
I/O VL One−Shot
Output Impedance
1.3 to 4.5
0.9 to (VCC – 0.4)
30
W
1.3 to 4.5
0.9 to (VCC – 0.4)
15
17
> 2.0
> 1.6
4
5
1.3 to 4.5
0.9 to (VCC – 0.4)
10
11
> 2.0
> 1.6
3
4
1.3 to 4.5
0.9 to (VCC – 0.4)
0.6
1
> 2.0
> 1.6
0.2
0.8
1.3 to 4.5
0.9 to (VCC – 0.4)
0.4
0.6
> 2.0
> 1.6
0.2
0.3
1.3 to 4.5
0.9 to (VCC – 0.4)
60
> 2.0
> 1.6
100
tPD_VL−VCC Propagation Delay
(Output = I/O_VCC,
tPHL, tPLH)
CIOVCC = 15 pF
tPD_VCC−VL Propagation Delay
(Output = I/O_VL,
tPHL, tPLH)
CIOVL = 15 pF
tSK VL−VCC
Channel−to−Channel
Skew (Output =
I/O_VCC)
CIOVCC = 15 pF
tSK_VCC−VL Channel−to−Channel
Skew
(Output = I/O_VL)
CIOVCC = 15 pF
Maximum Data Rate
(Output = I/O_VCC,
CIOVCC = 15 pF)
(Output = I/O_VL,
CIOVL = 15 pF)
ns
ns
nS
nS
Mb/s
8. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
9. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
10. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
11. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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NLSX3014
ENABLE / DISABLE TIME MEASUREMENTS
−405C to +855C
tEN−VL
Unit
0.9 to (VCC – 0.4)
80
140
ns
1.3 to 4.5
0.9 to (VCC – 0.4)
175
300
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
250
475
ns
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
175
250
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
90
140
ns
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
150
200
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
200
300
ns
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
150
250
ns
VL (V)
(Note 14)
Turn−On Enable Time (Output =
I/O_VCC, tpZH)
CIOVCC = 15 pF
1.3 to 4.5
Turn−On Enable Time (Output =
I/O_VCC, tpZL)
CIOVL = 15 pF
Turn−On Enable Time (Output =
I/O_VL, tpZH)
Turn−On Enable Time (Output =
I/O_VL, tpZL)
tDIS−VCC Turn−Off Disable Time (Output =
I/O_VCC, tpHZ)
Propagation Delay (Output =
I/O_VCC, tPLZ)
tDIS−VL
Max
VCC (V)
(Note 13)
Parameter
tEN−VCC
Typ
(Note 15)
Test Conditions
(Note 12)
Symbol
Turn−Off Disable Time (Output =
I/O_VL, tpHZ)
Propagation Delay (Output = I/O_VL,
tPLZ)
Min
12. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
13. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
14. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
15. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 °C. All units are production tested at TA = +25 °C. Limits over the operating
temperature range are guaranteed by design.
NLSX3014
VL
VCC
NLSX3014
VL
EN
Source
I/O VL
VCC
EN
I/O VL
I/O VCC
I/O VCC
CIOVL
CIOVCC
Source
tRISE/FALL v
3 ns
I/O VL
90%
50%
10%
tPD_VL−VCC
I/O VCC
I/O VCC
tRISE/FALL v 3 ns
90%
50%
10%
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 3. Driving I/O VL Test Circuit and Timing
tR−VL
Figure 4. Driving I/O VCC Test Circuit and Timing
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NLSX3014
VCC
PULSE
GENERATOR
2xVCC
OPEN
R1
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 5. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
90%
50%
10%
tR
EN
VCC
90%
50%
10%
tPHL
GND
VL
50%
tPZL
Output
50%
tPZH
tF
Output
50%
GND
tPLZ
tPHZ
HIGH
IMPEDANCE
10%
VOL
90%
VOH
Figure 6. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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7
HIGH
IMPEDANCE
NLSX3014
TEST CONDITIONS
1. TA = +25°C,
2. Input Applied to 1 channel, the other 3 inputs are grounded,
3. CLoad = 15 pF
2.5
7
6
2
VCC = 3.3 V, VL = 2.5 V
VCC = 3.3 V, VL = 2.5 V
4
ICC (mA)
ICC (mA)
5
VCC = 2.8 V, VL = 1.8 V
3
2
1.5
VCC = 2.8 V, VL = 1.8 V
1
1
0
0
0
1
5
10
25
50
0
1
FREQUENCY (MHz)
Figure 7. ICC vs. Frequency
(Input = I/O VCC, Output = I/O VL)
25
50
700
600
4
500
VCC = 3.3 V, VL = 2.5 V
3
2
IL (mA)
ICC (mA)
10
Figure 8. IL vs. Frequency
(Input = I/O VCC, Output = I/O VL)
5
VCC = 2.8 V, VL = 1.8 V
VCC = 3.3 V, VL = 2.5 V
400
300
VCC = 2.8 V, VL = 1.8 V
200
1
0
5
FREQUENCY (MHz)
100
0
1
5
10
25
0
50
0
FREQUENCY (MHz)
1
5
10
25
FREQUENCY (MHz)
Figure 9. ICC vs. Frequency
(Input = I/O VL, Output =I/O VCC)
Figure 10. IL vs. Frequency
(Input = I/O VL, Output = I/O VCC)
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50
NLSX3014
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
is referenced to the VL supply and has Over−Voltage
Tolerant (OVT) protection.
The NLSX3014 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX3014 consists of four bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
Uni−Directional versus Bi−Directional Translation
The NLSX3014 can function as a non−inverting
uni−directional translator. One advantage of using the
translator as a uni−directional device is that each I/O pin
can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
It is recommended that the VL supply should be less than
or equal to the value of the VCC minus 0.4 V. The
sequencing of the power supplies will not damage the
device during the power up operation; however, the current
consumption of the device will increase if VL exceeds VCC
minus 0.4 V. The Enable (EN) pin can be used to provide
power savings. Both I/O ports are tri−stated and in low
power consumption state if the EN input equals 0 V.
The enable pin should be used to enter the low current
tri−state mode, rather than setting either the VL or VCC
supplies to 0 V. The NLSX3014 will not be damaged if
either VL or VCC is equal to 0 V while the other supply
voltage is at a nominal operating value; however, the
operation of the translator cannot be guaranteed during
single supply operation.
For optimal performance, 0.01 to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the power supply voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
Input Driver Requirements
For proper operation, the input driver to the auto sense
translator should be capable of driving 2.0 mA of peak
output current.
Output Load Requirements
The NLSX3014 is designed to drive CMOS inputs.
Resistive pullup or pulldown loads of less than 50 kW
should not be used with this device. The NLSX3373 or
NLSX3378 open−drain auto sense translators are alternate
translator options for an application such as the I2C bus that
requires pullup resistors.
Enable Input (EN)
The NLSX3014 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
ORDERING INFORMATION
Device
NLSX3014MUTAG
Package
Shipping†
UQFN12
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NLSX3014
PACKAGE DIMENSIONS
UQFN12 1.7x2.0, 0.4P
CASE 523AE−01
ISSUE A
D
PIN 1 REFERENCE
2X
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH 0.03
MAX ON BOTTOM SURFACE OF
TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
A B
ÏÏ
ÏÏ
L1
DETAIL A
E
NOTE 5
TOP VIEW
DIM
A
A1
A3
b
D
E
e
K
L
L1
L2
DETAIL B
A
0.05 C
12X
0.05 C
A1
A3
8X
C
SIDE VIEW
SEATING
PLANE
K
5
7
DETAIL A
MOUNTING FOOTPRINT
SOLDERMASK DEFINED
e
1
12X
DETAIL B
OPTIONAL
CONSTRUCTION
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.70 BSC
2.00 BSC
0.40 BSC
0.20
---0.45
0.55
0.00
0.03
0.15 REF
11
L
2.00
12X
L2
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
1
NOTE 3
0.32
2.30
0.40
PITCH
11X
0.22
12X
0.69
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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