MC14046B D

MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1out, and maintains 90° phase shift at
the center frequency between PCAin and PCBin signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2out and LD, and maintains a 0°
phase shift between PCA in and PCB in signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout
whose frequency is determined by the voltage of input VCOin and the
capacitor and resistors connected to pins C1A, C1B, R1, and R2.
The source−follower output SFout with an external resistor is used
where the VCOin signal is needed but no loading can be tolerated.
The inhibit input Inh, when high, disables the VCO and source
follower to minimize standby power consumption. The zener diode
can be used to assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
•
•
•
•
•
•
•
•
Buffered Outputs Compatible with Low−Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin−for−Pin Replacement for CD4046B
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle
Limited
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
VDD
DC Supply Voltage Range
Vin
Input Voltage Range (All Inputs)
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SOIC−16 WB
DW SUFFIX
CASE 751G
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
16
14046BG
AWLYYWW
MC14046B
ALYWG
1
1
SOEIAJ−16
SOIC−16 WB
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range
VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Iin
DC Input Current, per Pin
± 10
mA
PD
Power Dissipation, per Package (Note 1)
500
mW
TA
Operating Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 14
1
Publication Order Number:
MC14046B/D
MC14046B
PIN ASSIGNMENT
BLOCK DIAGRAM
SELF BIAS
CIRCUIT
PCAin 14
PCBin 3
VCOin 9
VDD = PIN 16
VSS = PIN 8
PHASE
COMPARATOR 1
2PC1out
PHASE
COMPARATOR 2
13PC2out
1LD
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
4VCOout
11R1
12R2
6C1A
7C1B
1
16
VDD
PC1out
2
15
ZENER
PCBin
3
14
PCAin
VCOout
4
13
PC2out
INH
5
12
R2
C1A
6
11
R1
C1B
7
10
SFout
VSS
8
9
VCOin
10SFout
SOURCE FOLLOWER
INH 5
LD
VSS
15ZENER
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
− 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage (Note 2)
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
“1” Level
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–1.2
–0.25
–0.62
–1.8
−
−
−
−
–1.0
–0.2
–0.5
–1.5
–1.7
–0.36
–0.9
–3.5
−
−
−
−
–0.7
–0.14
–0.35
–1.1
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
Vdc
VIH
IOH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
mAdc
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Input Current
Vdc
Input Capacitance
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V, PCBin = VDD
or 0 V, Iout = 0 mA
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3)
(Inh = “0”, fo = 10 kHz, CL = 50 pF,
R1 = 1.0 MW, R2 = R RSF = ∞,
and 50% Duty Cycle)
IT
5.0
10
15
IT = (1.46 mA/kHz) f + IDD
IT = (2.91 mA/kHz) f + IDD
IT = (4.37 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Noise immunity specified for worst−case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
3. To Calculate Total Current in General:
VCOin – 1.65 3/4
VCOin – 1.65
VDD − 1.35 3/4
IT [ 2.2 x VDD
+
+ 1.6 x
+ 1 x 10−3 (CL + 9) VDD f +
R1
R2
RSF
ǒ
1 x 10−1 VDD2
Ǔ
ǒ100% Duty Cycle of PCAin Ǔ + IQ
100
ǒ
Ǔ
where: IT in mA, CL in pF, VCOin, VDD in Vdc, f in kHz, and
R1, R2, RSF in MW, CL on VCOout.
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2
MC14046B
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25°C)
Characteristic
Symbol
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
VDD
Vdc
Minimum
Maximum
Device
Typical
Device
5.0
10
15
−
−
−
180
90
65
350
150
110
5.0
10
15
−
−
−
100
50
37
175
75
55
Units
ns
ns
PHASE COMPARATORS 1 and 2
Input Resistance − PCAin
Rin
5.0
10
15
1.0
0.2
0.1
2.0
0.4
0.2
−
−
−
MW
− PCBin
Rin
15
150
1500
−
MW
Vin
5.0
10
15
−
−
−
200
400
700
300
600
1050
mV p–p
−
5 to 15
fmax
5.0
10
15
0.5
1.0
1.4
0.7
1.4
1.9
−
−
−
MHz
Temperature − Frequency Stability
(R2 = ∞ )
−
5.0
10
15
−
−
−
0.12
0.04
0.015
−
−
−
%/_C
Linearity (R2 = ∞ )
(VCOin = 2.5 V ± 0.3 V, R1 > 10 kW)
(VCOin = 5.0 V ± 2.5 V, R1 > 400 kW)
(VCOin = 7.5 V ± 5.0 V, R1 ≥ 1000 kW)
−
5.0
10
15
−
−
−
1.0
1.0
1.0
−
−
−
Output Duty Cycle
−
5 to 15
−
50
−
%
Rin
15
150
1500
−
MW
Offset Voltage
(VCOin minus SFout, RSF > 500 kW)
−
5.0
10
15
−
−
−
1.65
1.65
1.65
2.2
2.2
2.2
V
Linearity
(VCOin = 2.5 V ± 0.3 V, RSF > 50 kW)
(VCOin = 5.0 V ± 2.5 V, RSF > 50 kW)
(VCOin = 7.5 V ± 5.0 V, RSF > 50 kW)
−
5.0
10
15
−
−
−
0.1
0.6
0.8
−
−
−
Minimum Input Se−sitivity
AC Coupled — PCAin
C series = 1000 pF, f = 50 kHz
DC Coupled − PCAin, PCBin
See Noise Immunity
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Maximum Frequency
(VCOin = VDD, C1 = 50 pF
R1 = 5.0 kW, and R2 = ∞)
Input Resistance − VCOin
%
SOURCE−FOLLOWER
%
ZENER DIODE
Zener Voltage (Iz = 50 mA)
VZ
−
6.7
7.0
7.3
V
Dynamic Resistance (Iz = 1.0 mA)
RZ
−
−
100
−
W
4. The formula given is for the typical characteristics only.
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3
MC14046B
PHASE COMPARATOR 1
Input Stage
00
01
11
10
XX
PCAin
PCBin
PC1out
0
1
PHASE COMPARATOR 2
Input Stage
XX
PCAin
00
01
PCBin
00
10
10
00
01
01
10
11
11
11
PC2out
0
3−State
Output Disconnected
1
LD (Lock Detect)
0
1
0
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
No signal on input PCAin.
VCO in PLL system adjusts to center
frequency (f0).
VCO in PLL system adjusts to minimum
frequency (fmin).
Phase angle between PCAin and PCBin.
90° at center frequency (f0), approaching
0_ and 180° at ends of lock range (2fL)
Always 0_ in lock (positive rising edges).
Locks on harmonics of center frequency.
Yes
No
Signal input noise rejection.
High
Low
Lock frequency range (2fL).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax – fmin.
Capture frequency range (2fC).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Depends on low−pass filter characteristics
(see Figure 3). fC v fL
Center frequency (f0).
VCO output frequency (f).
Note: These equations are intended to be
a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than ± 20%.
The frequency of VCOout, when VCOin = 1/2 VDD
fmin =
fmax =
1
(VCO input = VSS)
R2(C1 + 32 pF)
1
R1(C1 + 32 pF)
+ fmin
Where: 10K v R1 v 1 M
10K v R2 v 1 M
100pF v C1 v .01 mF
Figure 2. Design Information
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4
(VCO input = VDD)
fC = fL
MC14046B
9
SOURCE
FOLLOWER
VCOin
PCAin
@ FREQUENCY f′
PCBin
14
3
PHASE
2 OR 13
COMPARATOR PC1out
OR
PC2out
EXTERNAL
LOW-PASS
FILTER
SFout
10
RSF
9
11
12
7
CIA
R1
VCOout
@ FREQUENCY Nf′ = f
4
VCO
6
CIB
R2
CI
EXTERNAL
÷N
COUNTER
Typical Low−Pass Filters
(a)
INPUT
R3
OUTPUT
C2
2fC [ 1
p
(a)
INPUT
Ǹ
2 p fL
R3 C2
Typically:
R3
N
R4 C2 + 6N –
fmax 2 p D f
(R3 ) 3, 000W) C2 + 100NDf – R4 C2
fmax2
OUTPUT
R4
C2
D f = fmax − fmin
NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint to ground. The value for
CC should be such that the corner frequency of this network does not significantly affect Wn. In Figure B, the ratio of R3 to R4 sets
the damping, R4 ^ (0.1)(R3) for optimum results.
LOW−PASS FILTER
Filter A
Definitions: N = Total division ratio in feedback loop
Kφ = VDD/π for Phase Comparator 1
Kφ = VDD/4 π for Phase Comparator 2
2 p D fVCO
KVCO +
VDD – 2 V
2 p fr
(at phase detector input)
for a typical design Wn ^
10
ζ ^ 0.707
wn +
z+
Ǹ
KfKVCO
NR3C2
Nwn
2KfKVCO
F(s) +
1
R3C2S ) 1
Filter B
wn +
Ǹ
KfKVCO
NC2(R3 ) R4)
z + 0.5 wn (R3C2 )
F(s) +
N
)
KfKVCO
R3C2S ) 1
S(R3C2 ) R4C2) ) 1
Waveforms
Phase Comparator 1
PCAin
Phase Comparator 2
VDD
PCAin
VSS
VOH
PCBin
PC1out
VCOin
VDD
VSS
VOH
PCBin
VOL
VOH
LD
VOL
VOH
PC2out
VOL
VCOin
VOL
VOH
VOL
VOH
VOL
VOH
VOL
Note: for further information, see:
(1) F. Gardner, “Phase−Lock Techniques”, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, “Miniature RC Filters Using Phase−Locked Loop”, BSTJ, May, 1965.
(3) Garth Nash, “Phase−Lock Loop Design Fundamentals”, AN−535, Motorola Inc.
(4) A. B. Przedpelski, “Phase−Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.
Figure 3. General Phase−Locked Loop Connections and Waveforms
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5
MC14046B
ORDERING INFORMATION
Package
Shipping†
MC14046BDWG
SOIC−16 WB
(Pb−Free)
47 Units / Tube
NLV14046BDWG*
SOIC−16 WB
(Pb−Free)
47 Units / Tube
MC14046BDWR2G
SOIC−16 WB
(Pb−Free)
1000 Units / Tape & Reel
MC14046BFELG
SOEIAJ−16
(Pb−Free)
2000 Units / Tape & Reel
MC14046BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
MC14046B
PACKAGE DIMENSIONS
SOIC−16 WB
DW SUFFIX
CASE 751G−03
ISSUE D
A
D
9
1
8
h X 45 _
E
0.25
16X
M
T A
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
S
B
S
L
A
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
B
B
14X
e
A1
H
8X
M
B
M
16
q
C
T
SEATING
PLANE
SOLDERING FOOTPRINT*
16X
0.58
11.00
1
16X
1.27
PITCH
1.62
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MC14046B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
CASE 966
ISSUE A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
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