Revised March 2002 CD4046BC Micropower Phase-Locked Loop General Description Features The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal. ■ Wide supply voltage range: Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and maintains 90° phase shifts at the VCO center frequency. Between signal input and comparator input (both at 50% duty cycle), it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency. 3.0V to 18V ■ Low dynamic power consumption: 70 µW (typ.) at fo = 10 kHz, VDD = 5V ■ VCO frequency: 1.3 MHz (typ.) at VDD = 10V ■ Low frequency drift: 0.06%/°C at VDD = 10V with temperature ■ High VCO linearity: 1% (typ.) Applications • FM demodulator and modulator • Frequency synthesis and multiplication • Frequency discrimination Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal (phase comp. II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0° phase shift between signal input and comparator input. • Data synchronization and conditioning The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1A, C1B, R1 and R2. • Motor speed control • Voltage-to-frequency conversion • Tone decoding • FSK modulation The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 kΩ or more. The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary. Ordering Code: Order Number Package Number Package Description CD4046BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4046BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 Fairchild Semiconductor Corporation DS005968 www.fairchildsemi.com CD4046BC Micropower Phase-Locked Loop October 1987 CD4046BC Connection Diagram Top View Block Diagram FIGURE 1. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) (Note 2) −0.5 to +18 VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5 to VDD +0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) Note 2: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3 to 15 VDC Input Voltage (VIN) DC Electrical Characteristics (Note 2) Symbol IDD Parameter Quiescent Device Current −55°C Conditions Min +25°C Max Min Typ +125°C Max Min Max Units Pin 5 = VDD, Pin 14 = VDD, Pin 3, 9 = VSS VDD = 5V 5 0.005 5 150 VDD = 10V 10 0.01 10 300 VDD = 15V 20 0.015 20 600 µA Pin 5 = VDD, Pin 14 = Open, Pin 3, 9 = VSS VOL VOH VIL VIH IOL IOH IIN LOW Level Output Voltage HIGH Level Output Voltage VDD = 5V 45 5 35 185 VDD = 10V 450 20 350 650 VDD = 15V 1200 50 900 1500 VDD = 5V 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 VDD = 5V 4.95 4.95 5 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 V 4.95 V LOW Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 Comparator and Signal In VDD = 10V, VO = 1V or 9V 3.0 4.5 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 6.25 4.0 4.0 HIGH Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 Comparator and Signal In VDD = 10V, VO = 1V or 9V 7.0 7.0 5.5 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 LOW Level Output Current VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output Current VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current µA V V mA mA All Inputs Except Signal Input VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 VDD = 15V, VIN = 15V 0.1 10−5 0.1 CIN Input Capacitance Any Input (Note 3) PT Total Power Dissipation fo = 10 kHz, R1 = 1 MΩ, −1.0 1.0 7.5 µA pF R2 = ∞, VCOIN = VCC/2 VDD = 5V 0.07 VDD = 10V 0.6 VDD = 15V 2.4 mW Note 3: Capacitance is guaranteed by periodic testing. Note 4: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4046BC Absolute Maximum Ratings(Note 1) CD4046BC AC Electrical Characteristics (Note 5) TA = 25°C, CL = 50 pF Symbol Parameter Conditions Min Typ Max Units VCO SECTION IDD Operating Current fo = 10 kHz, R1 = 1 MΩ, R2 = ∞, fMAX Maximum Operating Frequency 20 VDD = 10V 90 VDD = 15V 200 µA C1 = 50 pF, R1 = 10 kΩ, R2 = ∞, Linearity VCOIN = VCC/2 VDD = 5V VCOIN = VDD VDD = 5V 0.4 0.8 VDD = 10V 0.6 1.2 VDD = 15V 1.0 1.6 MHz VCOIN = 2.5V ± 0.3V, R1 ≥ 10 kΩ, VDD = 5V 1 VCOIN = 5V ± 2.5V, R1 ≥ 400 kΩ, V DD = 10V % 1 VCOIN = 7.5V ± 5V, R1 ≥ 1 MΩ, VDD = 15V Temperature-Frequency Stability No Frequency Offset, fMIN = 0 Frequency Offset, fMIN ≠ 0 VCOIN VCO tTHL Input Resistance Output Duty Cycle VCO Output Transition Time tTHL 1 %/°C < 5c1/f. VDD R2 = ∞ VDD = 5V 0.12–0.24 VDD = 10V 0.04–0.08 VDD = 15V 0.015–0.03 VDD = 5V 0.06–0.12 VDD = 10V 0.05–0.1 VDD = 15V 0.03–0.06 VDD = 5V 106 VDD = 10V 106 VDD = 15V 106 VDD = 5V 50 VDD = 10V 50 VDD = 15V 50 %/°C %/°C MΩ % VDD = 5V 90 200 VDD = 10V 50 100 VDD = 15V 45 80 ns ns PHASE COMPARATORS SECTION RIN Input Resistance Signal Input Comparator Input AC-Coupled Signal Input Voltage Sensitivity VDD = 5V 1 3 VDD = 10V 0.2 0.7 VDD = 15V 0.1 VDD = 5V VDD = 10V 10 VDD = 15V MΩ 106 6 CSERIES = 1000 pF f = 50 kHz VDD = 5V 200 400 VDD = 10V 400 800 VDD = 15V 700 1400 DEMODULATOR OUTPUT www.fairchildsemi.com 0.3 106 4 mV Symbol VCOIN− VDEM (Continued) Parameter Offset Voltage Linearity Typ Max RS ≥ 10 kΩ, VDD = 5V Conditions Min 1.50 2.2 RS ≥ 10 kΩ, VDD = 10V 1.50 2.2 RS ≥ 50 kΩ, VDD = 15V 1.50 2.2 Units V RS ≥ 50 kΩ VCOIN = 2.5V ± 0.3V, V DD = 5V 0.1 VCOIN = 5V ± 2.5V, VDD = 10V 0.6 VCOIN = 7.5V ± 5V, VDD = 15V 0.8 % ZENER DIODE VZ Zener Diode Voltage IZ = 50 µA RZ Zener Dynamic Resistance IZ = 1 mA 6.3 7.0 100 7.7 V Ω Note 5: AC Parameters are guaranteed by DC correlated testing. Phase Comparator State Diagrams FIGURE 2. 5 www.fairchildsemi.com CD4046BC AC Electrical Characteristics CD4046BC Typical Waveforms FIGURE 3. Typical Waveform Employing Phase Comparator I in Locked Condition FIGURE 4. Typical Waveform Employing Phase Comparator II in Locked Condition www.fairchildsemi.com 6 CD4046BC Typical Performance Characteristics Typical Center Frequency vs C1 for R1 = 10 kΩ, 100 kΩ and 1 MΩ FIGURE 5. Typical Frequency vs C1 for R2 = 10 kΩ, 100 kΩ and 1 MΩ FIGURE 6. Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (R S); Phase Comparator II, PD (Total) = PD (fMIN). 7 www.fairchildsemi.com CD4046BC Typical Performance Characteristics (Continued) Typical fMAX/fMIN vs R2/R1 FIGURE 7. Typical VCO Power Dissipation at Center Frequency vs R1 FIGURE 8. Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (RS); Phase Comparator II, PD (Total) = PD (fMIN). www.fairchildsemi.com 8 CD4046BC Typical Performance Characteristics (Continued) Typical VCO Power Dissipation at fMIN vs R2 FIGURE 9. Typical Source Follower Power Dissipation vs RS FIGURE 10. Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (R S); Phase Comparator II, PD (Total) = PD (fMIN). 9 www.fairchildsemi.com CD4046BC Typical Performance Characteristics (Continued) FIGURE 11. Typical VCO Linearity vs R1 and C1 Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (RS); Phase Comparator II, PD (Total) = PD (fMIN). www.fairchildsemi.com 10 This information is a guide for approximating the value of external components for the CD4046B in a phase-lockedloop system. The selected external components must be within the following ranges: R1, R2 ≥ 10 kΩ, RS ≥ 10 kΩ, C1 ≥ 50 pF. In addition to the given design information, refer to Figure 5, Figure 6, Figure 7 for R1, R2 and C1 component selections. Using Phase Comparator I Characteristics VCO Without Offset Using Phase Comparator II VCO With Offset VCO Without Offset R2 = ∞ VCO With Offset R2 = ∞ VCO Frequency For No Signal Input VCO in PLL system will adjust VCO in PLL system will adjust to to center frequency, fo lowest operating frequency, fmin 2 fL = full VCO frequency range Frequency Lock 2 fL = fmax − fmin Range, 2 fL Frequency Capture Range, 2 fC Loop Filter Component Selection For 2 fC, see Ref. Phase Angle Between 90° at center frequency (fo), approximating Single and Comparator 0° and 180° at ends of lock range (2 fL) Locks on Harmonics fC = fL Always 0° in lock Yes No High Low of Center Frequency Signal Input Noise Rejection 11 www.fairchildsemi.com CD4046BC Design Information CD4046BC Design Information (Continued) Using Phase Comparator I Characteristics VCO Without Offset VCO With Offset R2 = ∞ VCO Component Selection Using Phase Comparator II VCO Without Offset VCO With Offset R2 = ∞ Given: fo. Given: fo and fL. Given: fmax. Use fo with Calculate fmin Calculate fo from Given: fmin and fmax. Use fmin with Figure 5 to from the equation the equation Figure 6 to determine R1 and C1. fmin = fo − fL. to determine R2 and C1. Use fmin with Figure 6 to determine R2 and C1. Calculate Use fo with Figure 5 to Calculate determine R1 and C1. Use with Figure 7 from the equation to determine ratio R2/R1 to obtain R1. Use with Figure 7 to determine ratio R2/ R1 to obtain R1. References G.S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965. Floyd Gardner, “Phaselock Techniques”, John Wiley & Sons, 1966. www.fairchildsemi.com 12 CD4046BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 13 www.fairchildsemi.com CD4046BC Micropower Phase-Locked Loop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 14