EL9200, EL9201, EL9202 ® Data Sheet April 7, 2005 Programmable VCOM Features The EL9200, EL9201, and EL9202 represent programmable VCOM amplifiers for use in TFT-LCD displays. Featuring 1, 2, and 4 channels of VCOM amplification, respectively, each device features just a single programmable current source for adding offset to one VCOM output. This current source is programmable using a single wire interface to one of 128 levels. The value is stored on an internal EEPROM memory. • 128 step adjustable sink current • EEPROM memory • 2-pin adjustment and disable • Single, dual or quad amplifiers - 44MHz bandwidth - 80V/µs slew rate - 60mA continuous output - 180mA peak output The EL9200 is available in the 12-pin DFN package and the EL9201 and EL9202 are available in 24-pin QFN packages. All are specified for operation over the -40°C to +85°C temperature range. • Up to 18V operation • 2.6V to 3.6V logic control Typical Block Diagram • Pb-free available (RoHS compliant) RF AVDD VS+ + CE CTL VOUT INP GND EEPROM CONTROL Applications RG INN VSD UP/DOWN COUNTER ANALOG POT GND FN7438.0 AVDD R1 • TFT-LCD VCOM supplies for - LCD-TVs - LCD monitors R2 IOUT SET RSET 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL9200, EL9201, EL9202 Pinouts 20 VINB- 21 VINB+ 22 VS+ 23 VINA+ 24 VINA- 20 VINA- 21 VINA+ 19 NC VOUTA 1 19 VOUTB 11 VOUTA NC 2 18 VOUTA VOUTD 2 18 VOUTC 17 VS+ THERMAL PAD IOUT 4 AVDD 5 8 CTL NC 5 GND 6 7 VSD 16 VOUTB VIND- 3 17 VINCTHERMAL PAD NC 4 16 NC VIND+ 5 15 VINC+ AVDD 6 14 SET AVDD 6 14 GND GND 7 13 CE NC 12 IOUT 11 SET 10 13 AVDD NC 9 CTL 7 CE 8 NC 8 15 VINB- CTL 12 9 CE VINB+ 3 VSD 11 10 SET THERMAL PAD 22 NC NC 1 NC 10 IOUT 4 12 VS+ NC 9 GND 2 23 GND 24 NC VINA- 1 VINA+ 3 EL9202 (24-PIN QFN) TOP VIEW EL9201 (24-PIN QFN) TOP VIEW EL9200 (12-PIN DFN) TOP VIEW Ordering Information PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # TAPE & REEL PKG. DWG. # EL9200IL 12-Pin DFN - 24-Pin QFN (Pb-Free) - MDP0046 EL9200IL-T7 12-Pin DFN EL9201ILZ-T7 (See Note) 24-Pin QFN (Pb-Free) 7” MDP0046 EL9200IL-T13 MDP0047 EL9201ILZ-T13 (See Note) 24-Pin QFN (Pb-Free) 13” MDP0046 - MDP0047 EL9202IL 24-Pin QFN - MDP0046 12-Pin DFN (Pb-Free) 7” MDP0047 EL9202IL-T7 24-Pin QFN 7” MDP0046 EL9200ILZ-T13 (See Note) 12-Pin DFN (Pb-Free) 13” MDP0047 EL9202IL-T13 24-Pin QFN 13” MDP0046 EL9201IL 24-Pin QFN - MDP0046 EL9202ILZ (See Note) 24-Pin QFN (Pb-Free) - MDP0046 EL9201IL-T7 24-Pin QFN 7” MDP0046 EL9202ILZ-T7 (See Note) 24-Pin QFN (Pb-Free) 7” MDP0046 EL9201IL-T13 24-Pin QFN 13” MDP0046 EL9202ILZ-T13 (See Note) 24-Pin QFN (Pb-Free) 13” MDP0046 PART NUMBER PACKAGE MDP0047 EL9201ILZ (See Note) 7” MDP0047 12-Pin DFN 13” EL9200ILZ (See Note) 12-Pin DFN (Pb-Free) EL9200ILZ-T7 (See Note) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Absolute Maximum Ratings (TA = 25°C) AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V ESD Rating - HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C VS+ Supply Voltage between VS+ and GND . . . . . . . . . . . . . .18V Supply Voltage between VSD and GND . . . . . . . . . . . . . . . . . . . .4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA Input Voltages to GND SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V Output Voltages to GND OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VSD = 3V, VS+ = 15V, AVDD = 15V, RSET = 24.9kΩ, and TA = 25°C unless otherwise specified DESCRIPTION VS+ Supply Voltage IS+ Quiescent Current VSD Logic Supply Voltage CONDITION Quiescent Logic Current TYP 4.5 MAX UNIT 16.5 V EL9200 3.8 4.8 mA EL9201 7.6 9.6 mA EL9202 10.5 16 mA 3 3.6 V 2.6 3.6 V CE = 3.6V 50 µA CE = GND 25 µA Program (charge pump current) (Note 1) 23 mA Read (Note 1) 3 mA 25 µA For programming For operation ISD MIN IADD Supply Current Note 2 CTLIH CTL High Voltage 2.6V < VSD < 3.6V 0.7*VSD 0.8*VSD V CTLIL CTL Low Voltage 2.6V < VSD < 3.6V 0.2*VSD 0.3*VSD V CTLIHRPW CTL High Rejected Pulse Width 20 µs CTLILRPW CTL Low Rejected Pulse Width 20 µs CTLIHMPW CTL High Minimum Pulse Width 200 µs CTLILMPW CTL Low Minimum Pulse Width CTLMTC CTL Minimum Time Between Counts ICTL CTL Input Current 200 10 µs CTL = GND 10 µA CTL = VSD 10 µA CTLCAP CTL Input Capacitance CEIL CE Input Low Voltage 2.6V < VSD < 3.6V CEIH CE Input High Voltage 2.6V < VSD < 3.6V CEST CE Minimum Start Up Time (Note 1) CTLPROM CTL EEPROM Program Voltage 2.6V < VSD < 3.6V (Note 2) 4.9 CTLPT CTL EEPROM Programming Signal Time > 4.9V 200 PT Programming Time EEWC EE Write Cycles Guaranteed by design SETDN SET Differential Nonlinearity Monotonic over-temperature 3 µs 10 pF 0.4 V 1.6 V 1 ms 15.75 V µs 100 1000 ms cycles ±1 LSB FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Electrical Specifications PARAMETER VSD = 3V, VS+ = 15V, AVDD = 15V, RSET = 24.9kΩ, and TA = 25°C unless otherwise specified DESCRIPTION CONDITION MIN TYP MAX UNIT SETZSE SET Zero-Scale Error Note 3 ±2 LSB SETFSE SET Full-Scale Error Note 3 ±8 LSB ISET SET Current Through RSET (Note 1) 120 µA SETER SET External Resistance To GND, AVDD = 20V (Note 1) 10 200 kΩ To GND, AVDD = 4.5V (Note 1) 2.25 45 kΩ AVDD to SET AVDD to SET Voltage Attenuation OUTST OUT Settling Time To ±0.5 LSB error band (Note 1) VOUT OUT Voltage Range (Note 1) OUTVD OUT Voltage Drift (Note 1) 1:20 V/V 20 µs VSET + 0.5V 13 V 10 mV 15 mV AMPLIFIER CHARACTERISTICS INPUT CHARACTERISTICS VOS Input Offset Voltage TCVOS Average Offset Voltage Drift (Note 1) IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMRR Common-Mode Rejection Ratio For VIN from -5.5V to +5.5V 50 70 dB AVOL Open-Loop Gain -4.5V ≤ VOUT ≤ +4.5V 60 70 dB VCM = 0V 3 7 VCM = 0V 2 µV/°C 60 nA OUTPUT CHARACTERISTICS VOL Output Swing Low VOH Output Swing High 14.85 14.9 V ISC Short-Circuit Current ±150 ±180 mA IOUT Output Current ±65 mA RL = 1.5kΩ to 0 0.09 0.15 V POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS+ is moved from 4.5V to 15.5V 55 80 dB 60 80 V/µs 80 ns DYNAMIC PERFORMANCE SR Slew Rate (Note 4) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% tS Settling to +0.1% (AV = +1) (AV = +1), VOUT = 2V step BW -3dB Bandwidth 44 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz (EL9201 & EL9202 only) 110 dB dG Differential Gain (Note 5) RF = RG = 1kΩ and VOUT = 1.4V 0.17 % dP Differential Phase (Note 5) RF = RG = 1kΩ and VOUT = 1.4V 0.24 ° NOTES: 1. Simulated and determined via design and not directly tested 2. Tested at AVDD = 20V 3. Wafer sort only 4. NTSC signal generator used 4 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Pin Descriptions PIN IN/OUT VINX- Input DESCRIPTION EQUIVALENT CIRCUIT Amplifier X inverting input, where: X = A for EL9200 X = A, B for EL9201 X = A, B, C, D for EL9202 VS+ GND CIRCUIT 1 VINX+ Input Amplifier X non-inverting input, where: X = A for EL9200 X = A, B for EL9201 X = A, B, C, D for EL9202 VS+ Supply Op amp supply; bypass to GND with 0.1µF capacitor VOUTX Output Amplifier X output, where: X = A for EL9200 X = A, B for EL9201 X = A, B, C, D for EL9202 Reference Circuit 1 VS+ GND GND CIRCUIT 2 NC - No connect; not internally connected GND Supply Ground connection IOUT Output Adjustable sink current output pin; the current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128; see SET pin function description for the maxim adjustable sink current setting SET Output Maximum sink current adjustment point; connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin; the maximum adjustable sink current is equal to (AVDD/20) divided by RSET CE Input Counter enable pin; connect CE to VDD to enable counting of the internal counter; connect CE to GND to inhibit counting CTL Input Internal counter up/down control and internal EEPROM programming control input; if CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT; a mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT; applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter; see EEPROM Programming section for details AVDD Supply analog voltage supply; bypass to GND with 0.1µF capacitor VSD Supply System power supply input; bypass to GND with 0.1µF capacitor 5 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Amplifier Typical Performance Curves VS=5V TA=25°C TYPICAL PRODUCTION DISTRIBUTION 400 300 200 100 0.008 INPUT BIAS CURRENT (µA) QUANTITY (AMPLIFIERS) 500 0.004 0 -0.004 -0.008 -0.012 -50 12 8 10 6 4 2 0 -2 -4 -6 -8 -10 -12 0 VS=5V -10 QUANTITY (AMPLIFIERS) TYPICAL PRODUCTION DISTRIBUTION 20 15 10 5 4.96 4.94 4.92 4.9 4.88 -10 FIGURE 3. INPUT OFFSET VOLTAGE DRIFT OUTPUT LOW VOLTAGE (V) INPUT OFFSET VOLTAGE (mV) -4.85 1.5 1 0.5 0 70 110 150 TEMPERATURE (°C) FIGURE 5. INPUT OFFSET VOLTAGE vs TEMPERATURE 6 70 110 150 FIGURE 4. OUTPUT HIGH VOLTAGE vs TEMPERATURE 2 30 30 TEMPERATURE (°C) INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C) -10 150 VS=5V IOUT=5mA 4.86 -50 21 19 17 15 13 11 9 7 5 3 1 0 -0.5 -50 110 FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE OUTPUT HIGH VOLTAGE (V) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION VS=5V 70 TEMPERATURE (°C) INPUT OFFSET VOLTAGE (mV) 25 30 VS=5V IOUT=5mA -4.87 -4.89 -4.91 -4.93 -4.95 -50 -10 30 70 110 150 TEMPERATURE (°C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Amplifier Typical Performance Curves 78 VS=±5V RL=1kΩ VS=±V 77 SLEW RATE (V/µs) 70 65 76 75 74 73 60 -50 -10 30 70 110 72 -50 150 -10 FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE 0 -0.06 -0.08 -0.1 -0.12 -0.14 -0.16 100 0.25 0.2 0.15 0.1 0.05 0 200 0 100 IRE FIGURE 10. DIFFERENTIAL PHASE VS=5V AV=2 -40 R =1kΩ L FREQ=1MHz 80 250 60 190 GAIN 2nd HD GAIN (dB) DISTORTION (dB) -30 -60 3rd HD 40 130 20 70 PHASE 0 -80 -90 200 IRE FIGURE 9. DIFFERENTIAL GAIN -70 0 2 4 6 8 VOP-P (V) FIGURE 11. HARMONIC DISTORTION vs VOP-P 7 150 0.3 DIFFERENTIAL PHASE (°) DIFFERENTIAL GAIN (%) -0.04 -50 110 FIGURE 8. SLEW RATE vs TEMPERATURE VS=5V AV=2 RL=1kΩ -0.02 0 70 TEMPERATURE (°C) TEMPERATURE (°C) -0.18 30 10 -20 1K PHASE (°) OPEN-LOOP GAIN (dB) 75 10 10K 100K 1M 10M -50 100M FREQUENCY (Hz) FIGURE 12. OPEN LOOP GAIN AND PHASE FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Amplifier Typical Performance Curves 25 VS=5V AV=1 3 CLOAD=0pF MAGNITUDE (NORMALIZED) (dB) MAGNITUDE (NORMALIZED) (dB) 5 1kΩ 1 -1 150Ω 560Ω -3 -5 100K 1M 10M 100M 100pF 15 1000pF 47pF 10pF 5 -5 -15 VS=5V AV=1 RL=1kΩ -25 100K 1M FREQUENCY (Hz) FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS CL 12 MAXIMUM OUTPUT SWING (VP-P) 400 OUTPUT IMPEDANCE (Ω) 350 300 250 200 150 100 50 1M 100K 10M 100M 10 8 6 4 VS=5V 2 AV=1 RL=1kΩ DISTORTION <1% 0 10K 100K FREQUENCY (Hz) 10M 100M FIGURE 16. MAXIMUM OUTPUT SWING vs FREQUENCY -15 -80 -25 -60 PSRR (dB) CMRR (dB) 1M FREQUENCY (Hz) FIGURE 15. CLOSED LOOP OUTPUT IMPEDANCE -35 -45 PSRR+ VS=5V TA=25°C PSRR- -40 -20 -55 -65 1K 100M FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS RL 0 10K 10M 10K 100K 1M FREQUENCY (Hz) FIGURE 17. CMRR 8 10M 100M 0 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 18. PSRR FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Amplifier Typical Performance Curves -60 DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C -80 OTHER COMBINATIONS YIELD IMPROVED REJECTION 100 XTALK (dB) VOLTAGE NOISE (nV/√Hz) 1K 10 1 100 1K 10K 100K 1M 10M -100 -120 VS=5V -140 RL=1kΩ AV=1 VIN=110mVRMS -160 1K 10K 100M FREQUENCY (Hz) 1M 10M 30M FREQUENCY (Hz) FIGURE 19. INPUT VOLTAGE NOISE SPECTRAL DENSITY FIGURE 20. CHANNEL SEPARATION 100 5 VS=5V AV=1 80 RL=1kΩ VIN=50mV TA=25°C VS=5V AV=1 3 RL=1kΩ STEP SIZE (V) OVERSHOOT (%) 100K 60 40 20 0.1% 1 -1 0.1% -3 0 10 100 1K -5 55 65 LOAD CAPACITANCE (pF) 75 85 95 105 SETTLING TIME (ns) FIGURE 21. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE FIGURE 22. SETTLING TIME vs STEP SIZE VS=±5V TA=25°C AV=1 RL=1kΩ VS=±5V TA=25°C AV=1 RL=1kΩ 100mV STEP 1V STEP 50ns/DIV FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE 9 50ns/DIV FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Amplifier Typical Performance Curves 4.5 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 4 3.5 3.378W 3 θJ 2.5 2 A= QF N2 37 4 °C /W 1.5 1 0.5 0 0 25 75 85 100 50 125 AMBIENT TEMPERATURE (°C) FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 1 893mW 0.8 θ JA = 0.6 QF N2 14 0° 4 C/ W 0.4 0.2 0 150 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Application Information Adjustable Sink Current Output This device provides the ability to reduce the flicker of an LCD panel by adjustment of the VCOM voltage during production test and alignment. A 128-step resolution is provided under digital control which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. The device provides an output sink current which lowers the voltage on the external voltage divider. The equations that control the output are given below: The adjustment of the output and the programming of the non-volatile memory are provided on one pin while the counter enable (CE) is provided on a separate pin. The output is adjusted via the CTL pin either by counting up with a mid to low transition or by counting down with a mid to high transition. Once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximum value. An increment of the counter will increase the output sink current which will lower the voltage on the external voltage divider. A decrement of the counter will decrease the output sink current, which will raise the voltage on the external voltage divider. Once the desired output level is obtained, the part can store it's setting using the non-volatile memory in the device. See the non-volatile programming section for detailed information. NOTE: Once the desired output level is stored in the EEPROM, the CE pin must go low to preserve the stored value. A VDD Setting I OUT = --------------------- × --------------------------20 ( R SET ) 128 R1 R2 Setting V OUT = --------------------- V AVDD 1 – --------------------- × --------------------------- 20 ( R SET ) 128 R 1 + R 2 NOTE: Where setting is an integer between 1 and 128. 7-Bit Up/Down Counter The counter sets the level to the digital potentiometer and is connected to the non-volatile memory. When the part is programmed, the counter setting is loaded into the nonvolatile memory. This value will be loaded from the nonvolatile memory into the counter during power-on. The counter will not exceed its maximum level and will hold that value during subsequent increment requests on the CTL pin. The counter will not exceed its minimum level and will hold that value during subsequent decrement requests on the CTL pin. CTL Pin CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series 1kΩ resistor and a shunt 0.01µF capacitor connected on the CTL pin. In order to increment the setting, pulse CTL low for more than 200µs. The output sink current increases and lowers the VCOM lever by one least-significant bit (LSB). On the other hand, to decrement the setting, pulse CTL high for 10 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Since the internal comparators come up in an unknown state, the very first CTL pulse is ignored to avoid the possibility of a false pulse. more than 200µs. The output sink current will decrease and the VCOM level will increase by one LSB. To avoid unintentional adjustment, the EL9200, EL9201, and EL9202 guarantees to reject CTL pulses shorter than 20µs. See Figure 27 for the timing information. TABLE 1. TRUTH TABLE INPUT OUTPUT CTL CE VDD SET ICC MEMORY Mid to Hi Hi VDD Decrement Normal X Mid to Lo Hi VDD Increment Normal X X Lo VDD No Change Lower X > 4.9V X VDD No Change Increased Program X X 0 to VDD Read Increased Read NOTE: CE should be disabled (pulled low) before powering down the device to assure that the glitches and transients will not cause unwanted EEPROM overwriting. CTLMTC CTLIHRPW CTL HIGH CTL VDD/2 CTL LOW CTLILMPW CTLIHMPW CTLILRPW CE COUNTER OUTPUT UNDEF 78 79 7A 7B 7A VCOM FIGURE 27. VCOM ADJUSTMENT 11 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Non-Volatile Memory (EEPROM) Programming Short-Circuit Current Limit When the CTL pin exceeds 4.9V, the non-volatile programming cycle will be activated. The CTL signal needs to remain above 4.9V for more than 200µs. The level and timing needed to program the non-volatile memory is given below. It then takes a maximum of 100ms for the programming to be completed inside the device (see PT specification in Electrical Specification Table). CTL VOLTAGE 4.9V TIME The amplifiers will limit the short circuit current to ±180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±65mA. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The amplifiers are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur. CTLPT 1V 10µs FIGURE 28. EEPROM PROGRAMMING Amplifiers’ Operating Voltage, Input, and Output The amplifiers are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most amplifier specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the amplifiers extends 500mV beyond the supply rails. The output swings of the those typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 27 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from 5V supply with a 1kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.8VP-P. 5V AV=1 VS=5V TA=25°C VIN=10VP-P 5V FIGURE 30. OPERATION WITH BEYOND-THE-RAILS INPUT Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Power Supply Bypassing and Printed Circuit Board Layout The amplifiers can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal operation a 0.1µF ceramic capacitor should be placed from VS to pin to GND. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. OUTPUT INPUT 10µs 1V VS=2.5V AV=1 TA=25°C VIN=6VP-P FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT 12 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 Replacing Existing Mechanical Potentiometer Circuits Figures 29 and 30 show the common adjustment mechanical circuits and equivalent replacement with the EL920X. AVDD RF AVDD RA RB AVDD IN+ VOUT VCOM EL9200 RC RG IN+ R1 R2 VCOM OUT SET RSET R1 = RA R2 = RB + RC RA ( RB + RC ) R SET = ----------------------------------20R B FIGURE 31. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING EL9200 AVDD AVDD RF RX RY AVDD IN+ VOUT VCOM EL9200 RZ RG IN+ R1 R2 VCOM OUT SET RSET R1 = RX R2 = RZ RX ( RX + RY + RZ ) R SET = ------------------------------------------------20R Y FIGURE 32. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE EL9200 13 FN7438.0 April 7, 2005 EL9200, EL9201, EL9202 QFN Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN7438.0 April 7, 2005