1N59xxBRNG Series 3 W DO-41 Surmetict 30 Zener Voltage Regulators This is a 1N59xxBRNG series with limits and excellent operating characteristics that reflect the superior capabilities of silicon−oxide passivated junctions. All this in an axial−lead, transfer−molded plastic package that offers protection in all common environmental conditions. Features • • • • • • http://onsemi.com Cathode Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16 KV) per Human Body Model Surge Rating of 98 W @ 1 ms Maximum Limits Guaranteed on up to Six Electrical Parameters Package No Larger than the Conventional 1 W Package This is a Pb−Free Device Anode AXIAL LEAD CASE 59AB STYLE 1 Mechanical Characteristics CASE: Void free, transfer−molded, thermosetting plastic FINISH: All external surfaces are corrosion resistant and leads are readily solderable MAXIMUM LEAD TEMPERATURE FOR SOLDERING PURPOSES: 260°C, 1/16″ from the case for 10 seconds POLARITY: Cathode indicated by polarity band MOUNTING POSITION: Any MARKING DIAGRAM A 1N 59xxR YYWWG G MAXIMUM RATINGS Rating Symbol Value Unit Max. Steady State Power Dissipation @ TL = 75°C, Lead Length = 3/8″ Derate above 75°C PD 3.0 W 24 mW/°C Steady State Power Dissipation @ TA = 50°C Derate above 50°C PD 1.0 W 6.67 mW/°C −65 to +200 °C Operating and Storage Temperature Range TJ, Tstg A = Assembly Location 1N59xxR = Device Number YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Device 1N59xxBRNG Package Shipping† Axial Lead (Pb−Free) 3000 Units / Box †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 0 1 Publication Order Number: 1N5929BRN/D 1N59xxBRNG Series ELECTRICAL CHARACTERISTICS I (TL = 30°C unless otherwise noted, VF = 1.5 V Max @ IF = 200 mAdc for all types) IF Parameter Symbol VZ Reverse Zener Voltage @ IZT IZT Reverse Current ZZT Maximum Zener Impedance @ IZT IZK Reverse Current ZZK Maximum Zener Impedance @ IZK IR Reverse Leakage Current @ VR VR Breakdown Voltage IF Forward Current VF Forward Voltage @ IF IZM Maximum DC Zener Current VZ VR V IR VF IZT Zener Voltage Regulator http://onsemi.com 2 1N59xxBRNG Series ELECTRICAL CHARACTERISTICS (TL = 30°C unless otherwise noted, VF = 1.5 V Max @ IF = 200 mAdc for all types) Zener Voltage (Note 2) VZ (Volts) Zener Impedance (Note 3) Leakage Current @ IZT ZZT @ IZT Max mA W W mA mA Max 15 15.75 25.0 9 600 0.25 20 21.00 18.7 14 650 0.25 24 25.20 15.6 19 700 0.25 Device† (Note 1) Device Marking Min Nom 1N5929BRNG 1N5929R 14.25 1N5932BRNG 1N5932R 19.00 1N5934BRNG 1N5934R 22.80 ZZK @ IZK IR @ VR IZM Volts mA 1 11.4 100 1 15.2 75 1 18.2 62 PD, STEADY STATE DISSIPATION (WATTS) †The “G’’ suffix indicates Pb−Free package available. 1. TOLERANCE AND TYPE NUMBER DESIGNATION Tolerance designation − device tolerance of ±5% are indicated by a “B” suffix. 2. ZENER VOLTAGE (VZ) MEASUREMENT ON Semiconductor guarantees the zener voltage when measured at 90 seconds while maintaining the lead temperature (TL) at 30°C ±1°C, 3/8″ from the diode body. 3. ZENER IMPEDANCE (ZZ) DERIVATION The zener impedance is derived from 60 seconds AC voltage, which results when an AC current having an rms value equal to 10% of the DC zener current (IZT or IZK) is superimposed on IZT or IZK. 5 L = LEAD LENGTH TO HEAT SINK 4 L = 3/8″ 3 2 1 0 0 20 40 60 80 100 120 140 160 TL, LEAD TEMPERATURE (°C) 180 Figure 1. Power Temperature Derating Curve http://onsemi.com 3 200 1N59xxBRNG Series θ JL (t, D), TRANSIENT THERMAL RESISTANCE JUNCTION‐TO‐LEAD ( °C/W) 100 0.5 10 1 0.2 0.1 0.05 0.02 0.01 0.1 D = 0 0.01 PPK DUTY CYCLE, D = t1/t2 SINGLE PULSE D TJL = qJL(t)PPK REPETITIVE PULSES D TJL = qJL(t,D)PPK qJL(t,D) = D * qJL (∞)+(1−D) * qJL(t) [where qJL(t) is D = 0 curve] t1 t2 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 t, TIME (SECONDS) Figure 2. Typical Thermal Response L, Lead Length = 3/8 Inch IR , REVERSE LEAKAGE (μ Adc) @ VR AS SPECIFIED IN ELEC. CHAR. TABLE PPK , PEAK SURGE POWER (WATTS) 1K RECTANGULAR NONREPETITIVE WAVEFORM TJ=25°C PRIOR TO INITIAL PULSE 500 300 200 100 50 30 20 10 0.1 0.2 0.3 0.5 1 2 3 5 10 PW, PULSE WIDTH (ms) 20 30 50 100 3 2 1 0.5 TA = 125°C 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0005 0.0003 TA = 125°C 1 Figure 3. Maximum Surge Power 2 5 10 20 50 100 NOMINAL VZ (VOLTS) 200 400 Figure 4. Typical Reverse Leakage http://onsemi.com 4 1000 1N59xxBRNG Series APPLICATION NOTE DTJL is the increase in junction temperature above the lead temperature and may be found from Figure 2 for a train of power pulses (L = 3/8 inch) or from Figure 10 for dc power. Since the actual voltage available from a given zener diode is temperature dependent, it is necessary to determine junction temperature under any set of operating conditions in order to calculate its value. The following procedure is recommended: Lead Temperature, TL, should be determined from: DTJL = qJL PD For worst-case design, using expected limits of IZ, limits of PD and the extremes of TJ (DTJ) may be estimated. Changes in voltage, VZ, can then be found from: TL = qLA PD + TA qLA is the lead-to-ambient thermal resistance (°C/W) and PD is the power dissipation. The value for qLA will vary and depends on the device mounting method. qLA is generally 30−40°C/W for the various clips and tie points in common use and for printed circuit board wiring. The temperature of the lead can also be measured using a thermocouple placed on the lead as close as possible to the tie point. The thermal mass connected to the tie point is normally large enough so that it will not significantly respond to heat surges generated in the diode as a result of pulsed operation once steady-state conditions are achieved. Using the measured value of TL, the junction temperature may be determined by: DV = qVZ DTJ qVZ, the zener voltage temperature coefficient, is found from Figures 5 and 6. Under high power-pulse operation, the zener voltage will vary with time and may also be affected significantly by the zener resistance. For best regulation, keep current excursions as low as possible. Data of Figure 2 should not be used to compute surge capability. Surge limitations are given in Figure 3. They are lower than would be expected by considering only junction temperature, as current crowding effects cause temperatures to be extremely high in small spots resulting in device degradation should the limits of Figure 3 be exceeded. TJ = TL + DTJL http://onsemi.com 5 1N59xxBRNG Series TEMPERATURE COEFFICIENT RANGES 10 8 6 4 RANGE 2 0 -2 -4 3 4 5 6 7 8 9 10 VZ, ZENER VOLTAGE @ IZT (VOLTS) 11 12 θ VZ, TEMPERATURE COEFFICIENT (mV/ °C) @ I ZT θ VZ, TEMPERATURE COEFFICIENT (mV/ °C) @ I ZT (90% of the Units are in the Ranges Indicated) 1000 500 200 100 50 20 10 10 20 50 100 200 400 VZ, ZENER VOLTAGE @ IZT (VOLTS) Figure 5. Units To 12 Volts 1000 Figure 6. Units 10 To 400 Volts ZENER VOLTAGE versus ZENER CURRENT 100 100 50 30 20 50 30 20 IZ , ZENER CURRENT (mA) IZ, ZENER CURRENT (mA) (Figures 7, 8 and 9) 10 5 3 2 1 0.5 0.3 0.2 0.1 0 1 2 3 4 5 6 7 VZ, ZENER VOLTAGE (VOLTS) 8 9 10 5 3 2 1 0.5 0.3 0.2 0.1 10 0 10 20 10 IZ , ZENER CURRENT (mA) 5 2 1 0.5 0.2 0.1 100 150 200 250 300 350 VZ, ZENER VOLTAGE (VOLTS) 80 90 100 Figure 8. VZ = 12 thru 82 Volts 400 θJL, JUNCTION‐TO‐LEAD THERMAL RESISTANCE (° C/W) Figure 7. VZ = 3.3 thru 10 Volts 30 40 50 60 70 VZ, ZENER VOLTAGE (VOLTS) 80 70 60 50 L 40 L 30 TL 20 EQUAL CONDUCTION THROUGH EACH LEAD 10 0 0 Figure 9. VZ = 100 thru 400 Volts 1/8 1/4 3/8 1/2 5/8 3/4 L, LEAD LENGTH TO HEAT SINK (INCH) 7/8 Figure 10. Typical Thermal Resistance http://onsemi.com 6 1 1N59xxBRNG Series PACKAGE DIMENSIONS AXIAL LEAD CASE 59AB ISSUE O NOTES: 1. CONTROLLING DIMENSION: INCHES. 2. PACKAGE CONTOUR IS OPTIONAL WITHIN DIMENSIONS A AND B. HEAT SLUGS, IF ANY, SHALL BE WITHIN DIMENSION B BUT NOT SUBJECT TO ITS MINIMUM VALUE. 3. DIMENSION A DEFINES THE ENTIRE BODY INCLUDING HEAT SLUGS. 4. DIMENSION B IS MEASURED AT THE MAXIMUM DIAMETER OF THE BODY. 5. POLARITY SHALL BE DENOTED BY A CATHODE BAND. 6. LEAD DIAMETER, D, IS NOT CONTROLLED IN ZONE F. 7. ALL RULES AND NOTES ASSOCIATED WITH JEDEC DO−41 OUTLINE SHALL APPLY B K D F A POLARITY INDICATOR OPTIONAL AS NEEDED (SEE STYLES) DIM A B D F K F K INCHES MIN MAX 0.161 0.205 0.079 0.106 0.028 0.034 −−− 0.050 0.540 −−− MILLIMETERS MIN MAX 4.10 5.20 2.00 2.70 0.71 0.86 −−− 1.27 13.70 −−− STYLE 1: PIN 1. CATHODE (POLARITY BAND) 2. ANODE SURMETIC is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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