TI TPIC1310KTR

TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
D
D
D
D
D
D
KTR or KTS PACKAGE
(TOP VIEW)
Configured for 3-Phase Brushless Motor
Drive
Low rDS(on) . . . 0.25 Ω Typ
High Voltage Output . . . 30 V
Pulsed Current . . . 12 A Per Channel
Input Transient and ESD Protection
Compatible With High-Side and Low-Side
Current Sense Resistors
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDD
OUTA
UGA
LGA
UGB
SUB/GND
SOURCE
OUTB
SOURCE
SUB/GND
LGB
LGC
UGC
OUTC
VDD
description
The TPIC1310 is a monolithic gate-protected
power DMOS array that consists of six electrically
isolated N-channel enhancement-mode DMOS
transistors configured as a three-half H-bridge.
When suitably heat sunk, the TPIC1310 can drive
motors requiring 2.5 A of phase current. The
DMOS transistors are immune to second breakdown effects and current crowding, problems
often associated with bipolar transistors.
Tab is SUB/GND
The TPIC1310 is offered in 15-pin through-hole
(KTS) and surface-mount (KTR) PowerFLEX
packages and is characterized for operation over
the case temperature range of – 40°C to 125°C.
schematic
KTR PACKAGE
KTS PACKAGE
VDD
1, 15
Q1
Q2
UGA
Q3
UGB
3
2
8
OUTA
Q4
14
OUTB
Q5
LGA
NOTES: A.
B.
C.
D.
UG
C
5
13
OUTC
Q6
LGB
LGC
4
11
13 k
13 k
12
13 k
6, 10
SUB/TAB/GND
7, 9
SOURCE
Terminals 1 and 15 must be externally connected.
Terminals 6 and 10 must be connected to GND.
Terminals 7 and 9 must be connected to the sense resistor or GND.
No terminal may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerFLEX is a trademark of Texas Instruments Inc.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SOURCE-to-SUB/GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V
Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V
Continuous output current, each output, all outputs on, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Pulsed output current, each output, Imax, TC = 25°C (see Note 1 and Figure 14) . . . . . . . . . . . . . . . . . . . 12 A
Continuous VDD and SOURCE current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Pulsed VDD and SOURCE current, TC = 25°C (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 A
Continuous total dissipation, TC = 25°C (see Note 2 and Figure 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
NOTES: 1. Pulse duration = 10 µs, duty cycle ≤ 2%
2. Package is mounted in intimate contact with an infinite heat sink.
2
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• DALLAS, TEXAS 75265
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)GS
Gate-to-source breakdown voltage
ID = 250 µA,
ID = 1 mA,
See Figure 4
Low-side
Low-side
VGS = 0
VDS = VGS,
IGS = 250 µA
ISG = 250 µA
VDS(on)
Drain-to-source on-state voltage
VF(SD)
Forward on-state voltage, source-to-drain
IS = 3 A,
VGS = 0,
See Notes 3 and 4 and Figure 11
IDSS
Drain current-gate
current gate shorted to source
VDS = 28 V,,
VGS = 0
IGSSF
Forward-gate current, drain short
circuited to source
IGSSR
Reverse-gate current, drain short circuited to source
Ilk
lkg
rDS(on)
DS( )
Low-side
High-side
Leakage
g current,, drain-to-GND g
gate shorted to
source
drain to source on-state
on state resistance
Static drain-to-source
Forward transconductance
Ciss
Short-circuit input capacitance, low-side
Coss
Short-circuit output capacitance, low-side
0.9
VGS = 14 V,
TC = 25°C
TC = 125°C
UNIT
V
1.2
1.7
V
V
V
20
0.66
0.9
V
1.1
1.4
V
0.05
1
0.5
10
2
4
mA
VDS = 0
20
200
nA
VDS = 0
TC = 25°C
20
200
nA
0.05
1
TC = 125°C
0.5
10
VGS = 10 V,
ID = 3 A,,
See Notes 3 and 4
and Figures 5 and 6
TC = 25°C
0.27
0.37
TC = 125°C
0.45
0.55
VGS = 14 V,
ID = 3 A,,
See Notes 3 and 4
and Figures 5 and 6
TC = 25°C
0.22
0.32
TC = 125°C
0.32
0.47
VSG = 16 V,
VDS = 0,
Internal 13 kΩ from gate to source
VSG = 16 V,
VSG = 0.3 V,
VDGND = 28 V
VDS = 10 V,
ID = 3 A,
See Notes 3 and 4 and Figure 8
gfs
MAX
20
Source to gate breakdown voltage
Source-to-gate
ISG = 250 µA
ID = 3 A,
See Notes 3 and 4
TYP
30
0.3
V(BR)SG
High-side
MIN
µA
µA
Ω
0.5
0.85
S
110
V
VDS = 25 V,
f = 1 MHz,
0
VGS = 0,
See Figure 10
pF
120
Crss
Short-circuit reverse transfer capacitance, low-side
60
† Engineering estimate
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
trr
Reverse-recovery time
TEST CONDITIONS
High side
High-side
Low side
Low-side
QRR
Total diode charge
IS = 3 A,
VGS = 0,
0
See Figures 1 and 13
VDS = 28 V,
di/dt = 100 A/µs
A/µs,
IS = 3 A,
VGS = 0,
See Figure 13,
VDS = 28 V,
di/dt = 100 A/µs,
µ
SUB/GND connected to
SOURCE
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MIN
TYP
MAX
UNIT
30
ns
30
nC
70
ns
350
nC
3
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
5
Internal source inductance
5
Rg
Internal gate resistance
MAX
UNIT
70
VDD = 28 V,
ten = 10 ns
ns,
See Figure 2
Turn-off delay time
RL = 9.3 Ω,
tdi
ns,
dis = 10 ns
200
ns
140
Fall time
55
VDS = 12 V,
ID = 3 A,
A
VGS = 10 V,
See Figure 3 and Figure 12
1.6
2
0.5
0.62
0.25
0.31
nC
nH
Ω
500
thermal resistance
PARAMETER
RθJC
TEST CONDITIONS
Junction-to-case thermal resistance, one output on
RθJC Junction-to-case thermal resistance, two outputs on
NOTES: 5. Package mounted in intimate contact with infinite heatsink.
6. Two outputs with equal power
4
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TYP
MAX
UNIT
See Note 5
7.5
9
°C/W
See Notes 5 and 6
4.5
5.5
°C/W
• DALLAS, TEXAS 75265
MIN
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
4
I S – Source-to-Drain Diode Current – A
3
2
trr (SD)
1
Reverse di/dt = 100 A/µs
0
25% of IRM†
–1
Shaded Area = QRR
IRM†
–2
–3
–4
0
25
50
75
100
125
150
175
200
225
250
Time – ns
† IRM = maximum recovery current
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
VDD = 28 V
RL
Pulse Generator
ten
14 V
VDS
VGS
0V
VGS
50 Ω
50 Ω
td(off)
td(on)
DUT
Rgen
tdis
tr
tf
CL 30 pF
(see Note A)
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
5
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
TYPICAL CHARACTERISTICS
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
0.3 µF
Qgs(th)
VDD
VDS
0
VGS
DUT
IG = 100 µA
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.45
1.6
ID = 3 A
VDS = VGS
ID = 10 mA
1.2
ID = 1 mA
1.0
0.8
0.6
0.4
0.2
– 40 – 20
On-State Resistance – Ω
1.4
0.4
r DS(on) – Static Drain-to-Source
VGS(th) – Gate-to-Source Threshold Voltage – V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
0.35
VGS = 15 V
0.3
0.25
VGS = 12 V
0.2
0.15
0.1
0.05
0
20
40
60
80 100 120 140 160
0
–40 –20
TJ – Junction Temperature – °C
0 20 40 60 80 100 120 140 160
TJ – Junction Temperature – °C
Figure 5
Figure 4
6
VGS = 10 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
12
VGS = 15 V
TJ = 25°C
VGS = 12 V
VGS = 10 V
10
∆VGS = 1 V
TJ = 25°C
ÁÁ
ÁÁ
ÁÁ
ÁÁ
I D – Drain Current – A
0.6
On-State Resistance – Ω
rDS(on) – Static Drain-to-Source
1
0.9
0.8
0.7
0.5
0.4
0.3
VGS = 7 V
6
ÁÁ
ÁÁ
VGS = 10 V
VGS = 15 V
0.2
8
VGS = 12 V
4
2
VGS = 3 V
0
0.1
0.1
1
ID – Drain Current – A
0
10
1
2
3
4
5
6
7
8
VDS – Drain-to-Source Voltage – V
Figure 6
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE (FOR LOW SIDE)
12
Total
Number of
Units = 300
VDS = 10 V
ID = 3 A
TJ = 25°C
TJ = – 40°C
10
I D – Drain Current – A
TJ = 25°C
15
10
8
TJ = 150°C
6
4
5
1
0.97
0.94
0.91
0.88
0.85
0.82
0.79
0.76
0
0.73
2
0.7
Percentage of Units – %
20
10
Figure 7
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
25
9
gfs – Forward Transconductance – S
0
0
2
4
6
8
10
12
14
16
VGS – Gate-to-Source Voltage – V
Figure 9
Figure 8
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7
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
100
400
360
Capacitance – pF
320
I SD – Source-to-Drain Diode Current – A
VGS = 0
f = 1 MHz
TJ = 25°C
280
240
160
Coss
Ciss
120
Crss
80
VGS = 0
10
TJ = 25°C
1
TJ = –40°C
TJ = 150°C
40
.01
0.1
0
0
2
4
6
8
10
12
14
16
26
1
Figure 10
Figure 11
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
16
110
VDD = 12 V
12
10
VDD = 10 V
8
8
ID = 3A
TJ = 25°C
See Figure 3
6
6
4
4
2
2
VGS – Gate-to-Source Voltage – V
14
10
0
120
0
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
trr – Reverse Recovery Time – ns
VDD = 14 V
14
VDS – Drain-to-Source Voltage – V
REVERSE RECOVERY TIME
vs
REVERSE di/dt
16
12
Q4, Q5, Q6
100
90
VDS = 28 V
VGS = 0
IS = 3 A
TJ = 25°C
See Figure 1
80
70
60
50
40
Q1, Q2, Q3
30
20
0
20
Qg – Gate Charge – nC
40
60
80 100 120 140 160 180 200
Reverse di/dt – A/µs
Figure 12
8
10
VSD – Source-to-Drain Voltage – V
VDS – Drain-to-Source Voltage – V
Figure 13
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• DALLAS, TEXAS 75265
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
I D – Maximum Drain Current – A
TC = 25°C
ÁÁ
ÁÁ
1 µs†
10
θJC‡
10 ms†
1 ms†
500 µs†
1
10 µs†
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
† Less than 2% duty cycle
‡ Device mounted in intimate contact with infinite heatsink.
Figure 14
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• DALLAS, TEXAS 75265
9
TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY
SLIS071 – DECEMBER 1997
THERMAL INFORMATION
JUNCTION-TO-CASE THERMAL RESISTANCE
vs
PULSE DURATION
1
DC Conditions
RθJC – Junction-to-Case Thermal Resistance – °C/W
TC = 25°C
d = 0.5
d = 0.2
d = 0.1
d = 0.05
Single Pulse
tc
tw
ID
0
0.1
0.0001
0.001
0.01
0.1
tw – Pulse Duration – s
† Package mounted in intimate contact with infinite heat sink.
NOTE E: ZθJC(t) = r(t) RθJC
tw = pulse duration
tc = cycle time
d = duty cycle = tw / tc
Figure 15
10
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1
10
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