MC74HC541A D

MC74HC541A
Octal 3-State Noninverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
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The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
MARKING DIAGRAMS
20
20
HC
541A
ALYWG
G
HC541A
AWLYYWWG
1
1
A1
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
Output OE1 1
Enables OE2
19
SOIC−20
Y1
A
WL, L
YY, Y
WW, W
G or G
Y2
Y3
Y4
Noninverting
Outputs
TSSOP−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Y5
FUNCTION TABLE
Y6
Inputs
Y7
Y8
PIN 20 = VCC
PIN 10 = GND
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
X = Don’t Care
Z = High Impedance
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9
1
Publication Order Number:
MC74HC541A/D
MC74HC541A
MAXIMUM RATINGS
Symbol
VCC
Parameter
DC Supply Voltage
Value
Unit
−0.5 to +7.0
V
VI
DC Input Voltage
−0.5 ≤ VI ≤ VCC + 0.5
V
VO
DC Output Voltage (Note 1)
−0.5 ≤ VO ≤ VCC + 0.5
V
IIK
DC Input Diode Current
±20
mA
IOK
DC Output Diode Current
±35
mA
IO
DC Output Sink Current
±35
mA
ICC
DC Supply Current per Supply Pin
±75
mA
IGND
DC Ground Current per Ground Pin
±75
mA
TSTG
Storage Temperature Range
−65 to +150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
_C
TJ
Junction Temperature under Bias
+150
_C
qJA
Thermal Resistance
SOIC
TSSOP
96
128
_C/W
PD
Power Dissipation in Still Air at 85_C
SOIC
TSSOP
500
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
Level 1
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Latchup Performance
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above VCC and Below GND at 85_C (Note 5)
> 4000
> 300
> 1000
V
±300
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
(Referenced to GND)
2.0
6.0
V
VIN,
VOUT
DC Input Voltage, Output Voltage
(Referenced to GND)
0
VCC
V
−55
+125
_C
0
0
0
1000
500
400
ns
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Figure 2)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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2
MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
−55 to
25_C
≤85_C
≤125_C
Unit
VIH
Minimum High−Level Input Voltage
VOUT = 0.1 V
|IOUT| ≤ 20 mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low−Level Input Voltage
VOUT = VCC − 0.1 V
|IOUT| ≤ 20 mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High−Level Output Voltage
VIN = VIL
|IOUT| ≤ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Symbol
Parameter
Condition
|IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
VIN = VIL
VOL
Maximum Low−Level Output Voltage
VIN = VIH
|IOUT| ≤ 20 mA
|IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
VIN = VIH
V
IIN
Maximum Input Leakage Current
VIN = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
IOZ
Maximum 3−State Leakage Current
Output in High Impedance State
VIN = VIL or VIH
VOUT = VCC or GND
6.0
±0.5
±5.0
±10.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
VIN = VCC or GND
IOUT = 0 mA
6.0
4
40
160
mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
−55 to
25_C
≤85_C
≤125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
CIN
Maximum Input Capacitance
10
10
10
pF
Maximum 3−State Output Capacitance (High Impedance State Output)
15
15
15
pF
COUT
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Per Buffer) (Note 7)
35
7. Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
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3
pF
MC74HC541A
tf
tr
VCC
90%
INPUT A
50%
10%
GND
tPHL
tPLH
90%
OUTPUT Y
50%
10%
tTHL
tTLH
Figure 2. Switching Waveform
VCC
OE1 or OE2
50%
50%
GND
tPZL
OUTPUT Y
tPLZ
HIGH
IMPEDANCE
50%
10%
tPZH
OUTPUT Y
VOL
tPHZ
90%
VOH
50%
HIGH
IMPEDANCE
Figure 3. Switching Waveform
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL *
*Includes all probe and jig capacitance
Figure 4. Test Circuit
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
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MC74HC541A
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
device functions as an non−inverting buffer. When a high
voltage is applied to either input, the outputs assume the high
impedance state.
Data input pins. Data on these pins appear in non−inverted
form on the corresponding Y outputs, when the outputs are
enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
CONTROLS
OE1, OE2 (PINS 1, 19)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either non−inverting outputs
or high−impedance outputs.
Output enables (active−low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
To 7 Other Buffers
VCC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
Figure 6. Logic Detail
ORDERING INFORMATION
Package
Shipping†
MC74HC541ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC541ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
NLV74HC541ADWR2G*
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HC541ADTG
TSSOP−20
(Pb−Free)
75 Units / Rail
MC74HC541ADTR2G
TSSOP−20
(Pb−Free)
2500 Tape & Reel
NLV74HC541ADTR2G*
TSSOP−20
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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5
MC74HC541A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
N
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HC541A
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
SEATING
PLANE
C
T
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MC74HC541A/D