MC74HCT541A D

MC74HCT541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs
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High−Performance Silicon−Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non−inverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
A2
A3
Data
Inputs
A4
A5
2
Y2
17
Y3
16
Y4
15
Y5
14
3
17
4
16
5
15
6
14
7
13
8
12
Y1
3
4
5
6
7
8
9
10
A3
A4
A5
A6
A7
A8
GND
MARKING DIAGRAMS
20
20
HCT
541A
ALYWG
G
1
SOIC−20
Y3
Y4
Non-Inverting
Outputs
Y8
11
A2
1
Y2
Y7
12
2
1
HCT541A
AWLYYWWG
18
Y6
13
OE1 A1
LOGIC DIAGRAM
A1
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
VCC OE2 Y1
20 19 18
Features
•
•
•
•
•
•
•
•
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
Y5
FUNCTION TABLE
A6
A7
A8
Output
Enables
OE1
OE2
9
11
Y6
Inputs
Y7
Y8
1
19
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
Z = High Impedance
X = Don’t Care
PIN 20 = VCC
PIN 10 = GND
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 7
1
Publication Order Number:
MC74HCT541A/D
MC74HCT541A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air
500
mW
Tstg
Storage Temperature Range
–65 to +150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC Package)
260
_C
SOIC Package†
This device contains protection
circuitry to guard against damage due
to high static voltages or electric
fields. However, precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be tied
to an appropriate logic voltage level
(e.g., either GND or VCC). Unused
outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
–55
+125
_C
0
500
ns
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time (Figure 1)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input Voltage
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL
|Iout| ≤ 20mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
3.98
3.84
3.70
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.40
|Iout| ≤ 6.0mA
Vin = VIH or VIL
VOL
Maximum Low−Level Output Voltage
Vin = VIH or VIL
|Iout| ≤ 20mA
|Iout| ≤ 6.0mA
Vin = VIH or VIL
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
IOZ
Maximum 3−State Leakage Current
Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND
5.5
±0.5
±5.0
±10.0
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
Iout = 0mA
5.5
4
40
160
mA
DICC
Additional Quiescent Supply Current
Vin = 2.4V, Any One Input
Vin = VCC or GND, Other Inputs
Iout = 0mA
1. Total Supply Current = ICC + ΣDICC.
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2
5.5
≥ −55°C
25 to 125°C
2.9
2.4
mA
MC74HCT541A
AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
23
28
32
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30
34
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30
34
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
12
15
18
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum 3−State Output Capacitance (Output in High Impedance State)
15
15
15
pF
Typical @ 25°C, VCC = 5.0 V
CPD
55
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
2f
pF
+ ICC VCC .
SWITCHING WAVEFORMS
tf
tr
3.0V
3.0V
90%
INPUT A
OE1 or OE2
1.3V
1.3V
GND
1.3V
tPZL
10%
tPLZ
HIGH
IMPEDANCE
GND
tPLH
tPHL
OUTPUT Y
1.3V
10%
90%
1.3V
OUTPUT Y
tPZH
10%
tTHL
tTLH
90%
OUTPUT Y
VOL
tPHZ
VOH
1.3V
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
CL*
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
1kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
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3
MC74HCT541A
PIN DESCRIPTIONS
INPUTS
outputs are enabled and the device functions as a
non−inverting buffer. When a high voltage is applied to
either input, the outputs assume the high impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in
non−inverted form on the corresponding Y outputs, when
the outputs are enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either
non−inverting outputs or high−impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active−low).
When a low voltage is applied to both of these pins, the
LOGIC DETAIL
To 7 Other Buf­
fers
VCC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
ORDERING INFORMATION
Package
Shipping†
MC74HCT541ADWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC74HCT541ADWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
MC74HCT541ADTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74HCT541A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
A
−V−
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
1.20
--0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
0.047
--0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HCT541A
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
SEATING
PLANE
C
T
ON Semiconductor and the
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For additional information, please contact your local
Sales Representative
MC74HCT541A/D