MC74VHC125 D

MC74VHC125
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 3.8ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
Active−Low Output Enables
A1
OE1
A2
OE2
A3
OE3
A4
OE4
2
3
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14−LEAD SOIC
D SUFFIX
CASE 751A
14−LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
OE1
1
14
VCC
A1
2
13
OE4
Y1
3
12
A4
OE2
4
11
Y4
A2
5
10
OE3
Y2
6
9
A3
GND
7
8
Y3
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
Y1
1
ORDERING INFORMATION
5
6
Y2
4
9
8
Y3
10
12
11
Package
Shipping†
MC74VHC125DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74VHC125DR2G
SOIC−14
(Pb−Free)
2500 / Tape &
Reel
Device
MC74VHC125DTR2G TSSOP−14 2500 / Tape &
(Pb−Free)
Reel
Y4
13
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
FUNCTION TABLE
VHC125
Inputs
Output
A
OE
Y
H
L
X
L
L
H
H
L
Z
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 7
1
Publication Order Number:
MC74VHC125/D
MC74VHC125
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎ
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
$ 20
mA
Iout
DC Output Current, per Pin
$ 25
mA
ICC
DC Supply Current, VCC and GND Pins
$ 50
mA
PD
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
mW
Tstg
Storage Temperature
–65 to +150
°C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric fields. However, precautions
must be taken to avoid applications
of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin
or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎ
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ÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−55
+125
°C
0
0
100
20
ns/V
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
VCC = 3.3 V $0.3 V
VCC =5.0 V $0.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74VHC125
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
Min
1.5
2.1
3.15
3.85
VIH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA ≤ 85°C
TA = 25°C
(V)
Typ
Max
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
VIN = VIH or VIL
IOH = −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Max
2.0
3.0
4.5
TA ≤ 125°C
Min
Max
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
V
0.5
0.9
1.35
1.65
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IOZ
Maximum 3−State
Leakage Current
VIN = VIH or VIL
VOUT = VCC or GND
5.5
$0.2
5
$2.5
$2.5
mA
IIN
Maximum Input
Leakage Current
VIN = 5.5V or GND
0 to
5.5
$0.1
$1.0
$1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
4.0
40
40
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
MC74VHC125
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Parameter
Test Conditions
Maximum Propagation Delay,
A to Y
Maximum Output Enable TIme,
OE to Y
Maximum Output Disable Time,
OE to Y
Output−to−Output Skew
Min
TA = ≤
125°C
TA = ≤ 85°C
TA = 25°C
Typ
Max
Min
Max
Min
Max
Unit
ns
VCC = 3.3 $ 0.3V
CL = 15 pF
CL = 50 pF
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
12.0
16.0
VCC = 5.0 $ 0.5V
CL = 15 pF
CL = 50 pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
8.5
10.5
VCC = 3.3 $ 0.3V
RL = 1 kW
CL = 15 pF
CL = 50 pF
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
1.0
1.0
11.5
15.0
VCC = 5.0 $ 0.5V
RL = 1 kW
CL = 15 pF
CL = 50 pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
1.0
1.0
7.5
9.5
VCC = 3.3 $ 0.3V
RL = 1 kW
CL = 50 pF
9.5
13.2
1.0
15.0
1.0
18.0
VCC = 5.0 $ 0.5V
RL = 1 kW
CL = 50 pF
6.1
8.8
1.0
10.0
1.0
12.0
VCC = 3.3 $ 0.3V
(Note 1)
CL = 50 pF
1.5
1.5
1.5
VCC = 5.0 $ 0.5V
(Note 1)
CL = 50 pF
1.0
1.0
1.0
10
10
10
Cin
Maximum Input Capacitance
4
Cout
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
6
ns
ns
ns
pF
pF
Typical @ 25°C, VCC = 5.0 V
CPD
14
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.3
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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4
MC74VHC125
SWITCHING WAVEFORMS
VCC
OE
50%
VCC
GND
50%
A
tPZL
GND
tPHL
tPLH
tPLZ
HIGH
IMPEDANCE
50% VCC
Y
50% VCC
tPZH
VOL + 0.3V
tPHZ
Y
VOH - 0.3V
50% VCC
Y
Figure 1.
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
OUTPUT
1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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5
MC74VHC125
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
14 13 12 11 10
8
9
8
6
7
VHC
VHC125
125
AWLYWW*
1
2
3
4
ALYW*
5
6
7
1
2
14−LEAD SOIC
D SUFFIX
CASE 751A
3
4
5
14−LEAD TSSOP
DT SUFFIX
CASE 948G
14
13
12
11
10
9
8
6
7
VHC125
AWLYWW*
1
2
3
4
5
14−LEAD SOIC EIAJ
M SUFFIX
CASE 965
*See Applications Note AND8004/D for date code and traceability information.
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6
MC74VHC125
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
0.25
M
C A
S
B
S
DETAIL A
h
A
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
b
X 45 _
M
A1
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC74VHC125
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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MC74VHC125/D