MC74VHC1G125 D

MC74VHC1G125
Noninverting 3-State Buffer
Features
•
•
•
•
•
•
•
•
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 58; Equivalent Gates = 15
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
OE
1
IN A
2
GND
http://onsemi.com
MARKING
DIAGRAMS
5
5
1
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
M
The MC74VHC1G125 is an advanced high speed CMOS
noninverting 3−state buffer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The MC74VHC1G125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G125 to be used to interface 5 V circuits to 3 V
circuits.
W0 M G
G
1
5
5
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
W0 M G
G
1
W0 = Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
VCC
5
PIN ASSIGNMENT
1
4
3
OUT Y
Figure 1. Pinout (Top View)
OE
2
IN A
3
GND
4
OUT Y
5
VCC
FUNCTION TABLE
OE
EN
IN A
OUT Y
A Input
OE Input
Y Output
L
H
X
L
L
H
L
H
Z
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
December, 2012 − Rev. 17
1
Publication Order Number:
MC74VHC1G125/D
MC74VHC1G125
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Characteristics
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
−0.5 to 7.0
−0.5 to VCC + 0.5
V
−20
mA
+20
mA
+25
mA
VOUT
DC Output Voltage
IIK
Input Diode Current
IOK
Output Diode Current
IOUT
DC Output Current, per Pin
ICC
DC Supply Current, VCC and GND
PD
Power Dissipation in Still Air
qJA
Thermal Resistance
TL
Lead Temperature, 1 mm from Case for 10 secs
TJ
Junction Temperature Under Bias
Tstg
Storage Temperature
VESD
VCC = 0
High or Low State
VOUT < GND; VOUT > VCC
+50
mA
SC−88A, TSOP−5
200
mW
SC−88A, TSOP−5
333
°C/W
260
°C
+150
°C
−65 to +150
°C
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
Above VCC and Below GND at 125°C (Note 4)
$500
mA
ESD Withstand Voltage
ILatchup
Latchup Performance
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
5.5
V
VCC
DC Supply Voltage
2.0
VIN
DC Input Voltage
0.0
5.5
V
DC Output Voltage
0.0
VCC
V
Operating Temperature Range
−55
+125
°C
0
0
100
20
ns/V
VOUT
TA
tr , tf
Input Rise and Fall Time
VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110 ° C
Time, Years
TJ = 120 ° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
http://onsemi.com
2
MC74VHC1G125
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
1.5
2.1
3.15
3.85
VIH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA = 25°C
VCC
(V)
Typ
TA ≤ 85°C
Max
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
VIN = VIH or VIL
IOH = −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Max
2.0
3.0
4.5
0.0
0.0
0.0
−55 ≤ TA ≤ 125°C
Min
Max
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
V
0.5
0.9
1.35
1.65
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IOZ
Maximum 3−State
Leakage Current
VIN = VIH or VIL
VOUT = VCC or GND
5.5
±0.2
5
$2.5
$2.5
mA
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
$1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
CIN
COUT
Typ
Max
Max
Unit
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
4.5
6.4
8.0
11.5
9.5
13.0
12.0
16.0
ns
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
3.5
4.5
5.5
7.5
6.5
8.5
8.5
10.5
Maximum Output
Enable Time,
Input OE to Y
(Figures 4 and 5)
VCC = 3.3 ± 0.3 V
RL = 1000 W
CL = 15 pF
CL = 50 pF
4.5
6.4
8.0
11.5
9.5
13.0
11.5
15.0
VCC = 5.0 ± 0.5 V
RL = 1000 W
CL = 15 pF
CL = 50 pF
3.5
4.5
5.1
7.1
6.0
8.0
8.5
10.5
Maximum Output
Disable Time,
Input OE to Y
(Figures 4 and 5)
VCC = 3.3 ± 0.3 V
RL 1000 W
CL = 15 pF
CL = 50 pF
6.5
8.0
9.7
13.2
11.5
15.0
14.5
18.0
VCC = 5.0 ± 0.5 V
RL = 1000 W
CL = 15 pF
CL = 50 pF
4.8
7.0
6.8
8.8
8.0
10.0
10.0
12.0
Maximum Input
Capacitance
4.0
10
10
10
Maximum 3−State Output
Capacitance (Output in
High Impedance State)
6.0
Test Conditions
Min
Max
−55 ≤ TA ≤ 125°C
Maximum Propagation
Delay, Input A to Y
(Figures 3 and 4)
Parameter
Min
TA ≤ 85°C
Min
ns
ns
pF
pF
Typical @ 25°C, VCC = 5.0 V
CPD
8.0
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
http://onsemi.com
3
MC74VHC1G125
SWITCHING WAVEFORMS
VCC
OE
50%
GND
tPZL
VCC
50%
GND
tPZH
tPHL
tPLH
HIGH
IMPEDANCE
50% VCC
Y
A
tPLZ
VOL + 0.3V
tPHZ
VOH - 0.3V
50% VCC
50% VCC
Y
HIGH
IMPEDANCE
Y
Figure 4. Switching Wave Forms
Figure 5.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
OUTPUT
1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
ORDERING INFORMATION
Device
Package
Shipping†
M74VHC1G125DFT1G
M74VHC1G125DFT2G
SC−88A/SOT−353/SC−70
(Pb−Free)
NLVVHC1G125DFT1G*
M74VHC1G125DTT1G
3000 Units / Tape & Reel
TSOP−5/SOT−23/SC−59
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
4
MC74VHC1G125
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
G
5
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
4
−B−
S
1
2
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
H
K
http://onsemi.com
5
DIM
A
B
C
D
G
H
J
K
N
S
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G125
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
D
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
5X
0.20 C A B
M
5
1
4
2
L
3
B
S
K
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74VHC1G125/D