NL17SZ16 D

NL17SZ16
Single Input Buffer
The NL17SZ16 is a single input Buffer in two tiny footprint
packages. The device performs much as LCX multi−gate products in
speed and drive.
Features
•
•
•
•
•
•
Tiny SOT−353 and SOT−553 Packages
Source/Sink 24 mA at 3.0 Volts
Over−Voltage Tolerant Inputs and Outputs
Chip Complexity: FETs = 20
Designed for 1.65 V to 5.5 V VCC Operation
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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MARKING
DIAGRAMS
5
1
SC−88A
(SC−70−5/SOT−353)
DF SUFFIX
CASE 419A
LR MG
G
5
NC
1
A
2
GND
3
5
5
LR M G
G
1
SOT−553
XV5 SUFFIX
CASE 463B
VCC
1
LR = Device Code
M = Date Code*
G
= Pb−Free Package
4
(Note: Microdot may be in either location)
Y
*Date Code orientation and/or position may vary
depending upon manufacturing location.
Figure 1. Pinout (Top View)
PIN ASSIGNMENT
A
1
Y
Figure 2. Logic Symbol
Pin
Function
1
NC
2
IN A
3
GND
4
OUT Y
5
VCC
FUNCTION TABLE
A Input
Y Output
L
L
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 11
1
Publication Order Number:
NL17SZ16/D
NL17SZ16
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Units
−0.5 to +7.0
V
Output in High or Low State (Note 2)
−0.5 ≤ VI ≤ +7.0
V
VI < GND
−0.5 ≤ VO ≤ +7.0
V
VO < GND
−50
mA
−50
mA
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IOUT
DC Output Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground per Supply Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
qJA
Thermal Resistance
SOT−353
SOT−553
350
360
°C/W
PD
Power Dissipation in Still Air at 85°C
SOT−353
SOT−553
150
180
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
ESD
ESD Classification
ILatchup
Latchup Performance
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
2000
200
N/A
V
Above VCC and Below GND at 85°C (Note 6)
$100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. IO Absolute Maximum Rating Must be Obtained.
3. Tested to EIA/JESD22−A114−A, rated to EIA/JESD22−A114−B.
4. Tested to EIA/JESD22−A115−A, rated to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
Operations Only
Data Retention
DC Output Voltage
TA
Operating Temperature Range
tr, tf
Input Rise and Fall Time
VCC = 2.5 V ±0.2 V
VCC = 3.0 V ±0.3 V
VCC = 5.0 V ±0.5 V
Min
Max
Units
1.65
1.5
5.5
5.5
V
0
5.5
V
0
5.5
V
−55
+125
°C
0
0
0
20
10
5
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
NL17SZ16
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80°C
117.8
TJ = 90°C
1,032,200
TJ = 100°C
80
TJ = 110°C
Time, Years
TJ = 120°C
Time, Hours
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 130°C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
DC ELECTRICAL CHARACTERISTICS
Min
0.75 VCC
0.7 VCC
Symbol
Parameter
VIH
High−Level Input Voltage
1.65 to 1.95
2.3 to 5.5
VIL
Low−Level Input Voltage
1.65 to 1.95
2.3 to 5.5
VOH
High−Level Output Voltage
VIN = VIL or VIH
IOH = −100 mA
IOH = −3 mA
IOH = −8 mA
IOH = −12 mA
IOH = −16 mA
IOH = −24 mA
IOH = −32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
VOL
Low−Level Output Voltage
VIN = VIH or VOH
IOL = 100 mA
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
Input Leakage Current
VIN = 5.5 V or GND
IOFF
Power Off Leakage
Current
VIN = 5.5 V or
VOUT = 5.5 V
ICC
Quiescent Supply Current
VIN = 5.5 V or GND
IIN
Condition
−555C 3 TA 3 1255C
TA = 255C
VCC
(V)
Typ
Max
Min
0.75 VCC
0.7 VCC
0.25 VCC
0.3 VCC
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
Max
VCC
1.52
2.1
2.4
2.7
2.5
4.0
0.0
0.08
0.20
0.22
0.28
0.38
0.42
Units
V
0.25 VCC
0.3 VCC
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
V
0.1
0.24
0.3
0.4
0.4
0.55
0.55
0.1
0.24
0.3
0.4
0.4
0.55
0.55
V
0 to 5.5
±0.1
±1.0
mA
0
1
10
mA
5.5
1
10
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS tR = tF = 3.0 ns
Symbol
tPLH
tPHL
Parameter
Propagation Delay
(Figure 4 and 5)
−555C 3 TA 3 1255C
TA = 255C
VCC
(V)
Min
Typ
Max
Min
Max
Units
RL = 1 MW, CL = 15 pF
1.65
1.8
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
2.0
2.0
0.8
0.5
0.5
5.3
4.4
2.9
2.1
1.8
11.4
9.5
6.5
4.5
3.9
2.0
2.0
0.8
0.5
0.5
12
10
7.0
4.7
4.1
ns
RL = 500 W, CL = 50 pF
3.3 ± 0.3
5.0 ± 0.5
1.5
0.8
2.9
2.4
5.0
4.3
1.5
0.8
5.2
4.5
Condition
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3
NL17SZ16
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Units
CIN
Input Capacitance
VCC = 5.5 V, VI = 0 V or VCC
u4
pF
CPD
Power Dissipation Capacitance
(Note 7)
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
10 MHz, VCC = 5.5 V, VI = 0 V or VCC
25
30
pF
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
tf = 3 ns
tf = 3 ns
90%
INPUT
A and B
50%
VCC
90%
50%
INPUT
10%
10%
OUTPUT
GND
RL
tPHL
CL
tPLH
VOL
OUTPUT Y
50%
50%
A 1−MHz square input wave is recommended for
propagation delay tests.
VOH
Figure 4. Switching Waveform
Figure 5. Test Circuit
ORDERING INFORMATION
Package
Shipping†
NL17SZ16DFT2G
SC−88A/SC−70−5/SOT−353
(Pb−Free)
3000/Tape & Reel
NL17SZ16XV5T2G
SOT−553
(Pb−Free)
4000/Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SZ16
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDER FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
NL17SZ16
PACKAGE DIMENSIONS
SOT−553
XV5 SUFFIX
CASE 463B
ISSUE C
D
−X−
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
A
L
4
1
2
E
−Y−
3
b
e
HE
c
5 PL
0.08 (0.003)
DIM
A
b
c
D
E
e
L
HE
M
X Y
MILLIMETERS
NOM
MAX
0.55
0.60
0.22
0.27
0.13
0.18
1.60
1.65
1.20
1.25
0.50 BSC
0.10
0.20
0.30
1.55
1.60
1.65
MIN
0.50
0.17
0.08
1.55
1.15
INCHES
NOM
0.022
0.009
0.005
0.063
0.047
0.020 BSC
0.004
0.008
0.061
0.063
MIN
0.020
0.007
0.003
0.061
0.045
MAX
0.024
0.011
0.007
0.065
0.049
0.012
0.065
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.35
0.0531
1.0
0.0394
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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PUBLICATION ORDERING INFORMATION
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6
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NL17SZ16/D