MC74HCT138A 1-of-8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS www.onsemi.com The MC74HCT138A is identical in pinout to the LS138. The HCT138A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The HCT138A decodes a three−bit Address to one−of−eight active−lot outputs. This device features three Chip Select inputs, two active−low and one active−high to facilitate the demultiplexing, cascading, and chip−selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. Features • • • • • • • • Output Drive Capability: 10 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 122 FETs or 30.5 Equivalent Gates These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant SOIC−16 D SUFFIX CASE 751B PIN ASSIGNMENT A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 CS2 4 13 Y2 CS3 5 12 Y3 CS1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 MARKING DIAGRAMS 16 HCT138AG AWLYWW LOGIC DIAGRAM A0 ADDRESS INPUTS A1 A2 1 15 2 14 3 13 12 11 10 9 7 CHIPSELECT INPUTS CS1 CS2 CS3 1 SOIC−16 Y0 Y1 16 Y2 Y3 Y4 5 HCT 138A ALYWG G ACTIVE-LOW OUTPUTS 1 Y5 TSSOP−16 Y6 A WL, L YY, Y WW, W G or G Y7 6 4 TSSOP−16 DT SUFFIX CASE 948F PIN 16 = VCC PIN 8 = GND = = = = = Assembly Location Wafer Lot Year Work Week Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2015 June, 2015 − Rev. 11 1 Publication Order Number: MC74HCT138A/D MC74HCT138A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria Value Units Internal Gate Count* 30.5 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW .0075 pJ Speed Power Product *Equivalent to a two−input NAND gate. FUNCTION TABLE Inputs Outputs CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X H X H X X X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L H H L H L H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L L H H L H L H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H = high level (steady state) L = low level (steady state) X = don’t care MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air 500 450 mW Tstg Storage Temperature –65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (TSSOP or SOIC Package) SOIC Package† TSSOP Package† _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C www.onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HCT138A RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 500 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V −55 to 25_C ≤ 85_C ≤ 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20 mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V Vin = VIH or VIL |Iout| ≤ 4.0 mA 4.5 3.98 3.84 3.7 Vin = VIH or VIL |Iout| ≤ 20 mA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| ≤ 4.0 mA VOL Maximum Low−Level Output Voltage V 4.5 0.26 0.33 0.4 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 5.5 4.0 40 160 mA Vin = 2.4 V, Any One Input ≥ −55_C 25_C to 125_C Vin = VCC or GND, Other Inputs 2.9 2.4 lout = 0 mA 5.5 mA DICC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Additional Quiescent Supply Current AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter −55 to 25_C ≤ 85_C ≤ 125_C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 4) 30 38 45 ns tPLH, tPHL Maximum Propagation Delay, CS1 to Output Y (Figures 2 and 4) 27 34 41 ns tPLH, tPHL Maximum Output Transition Time, CS2 or CS3 to Output Y (Figures 3 and 4) 30 38 45 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 2 and 4) 15 19 22 ns tr, tf Maximum Input Rise and Fall Time 500 500 500 ns Cin Maximum Input Capacitance 10 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD 51 Power Dissipation Capacitance (Per Enabled Output)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC www.onsemi.com 3 2f + ICC VCC . pF MC74HCT138A EXPANDED LOGIC DIAGRAM 15 14 A0 A1 13 1 12 2 11 A2 3 10 CS3 CS2 Y1 Y2 Y3 Y4 Y5 5 4 9 7 CS1 Y0 Y6 Y7 6 SWITCHING WAVEFORMS VALID tr VALID INPUT CS1 1.3 V GND OUTPUT Y 90% 1.3 V 10% OUTPUT Y 1.3 V tTLH tTHL Figure 1. Figure 2. tf tr 3V 2.7 V 1.3 V 0.3 V INPUT CS2, CS3 GND tPHL tPLH 90% 1.3 V 10% OUTPUT Y tTHL tTLH Figure 3. www.onsemi.com 4 GND tPLH tPHL tPHL tPLH 3V 2.7 V 1.3 V 0.3 V 3V INPUT A tf MC74HCT138A TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 4. ORDERING INFORMATION Package Shipping† MC74HCT138ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HCT138ADR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel MC74HCT138ADTR2G TSSOP−16 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MC74HCT138A PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT138A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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