MC100E310 D

MC100E310
5V ECL Low Voltage 2:8
Differential Fanout Buffer
Description
The MC100E310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The E310 offers two selectable clock inputs to allow for
redundant or test clocks to be incorporated into the system clock trees.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10 − 20 ps increase in TPD, so the
relative skew between any two output pairs remains about 25 ns.
For more information on using PECL, designers should refer to
ON Semiconductor Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series Contains Temperature Compensation
•
•
•
•
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MC100E310FNG
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Features
•
•
•
•
•
•
http://onsemi.com
Dual Differential Fanout Buffers
200 ps Part−to−Part Skew
50 ps Output−to−Output Skew
28−lead PLCC Packaging
Q Output will Default LOW with Inputs Open or at VEE
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; >2 kV,
Machine Model; >200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
•
•
•
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 212 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 6
1
Publication Order Number:
MC100E310/D
MC100E310
Q0
Q0
25
24
Q1 VCCO Q1
23
22
21
Q2
Q2
20
19
Q0
Q0
Q1
VEE
26
18
Q3
Q1
CLK_SEL
27
17
Q3
Q2
CLKa
28
16
Q4
VCC
Pinout: 28−Lead PLCC
(Top View)
1
15
VCCO
CLKa
2
14
Q4
VBB
3
13
Q5
CLKb
4
12
Q5
5
6
7
8
9
10
11
Q7
Q6
Q6
Q2
CLKa
Q3
CLKa
Q3
CLKb
Q4
CLKb
Q4
Q5
CLK_SEL
Q5
Q6
Q6
CLKb
NC
Q7 VCCO
Q7
* All VCC and VCCO pins are tied together on the die.
Q7
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
VBB
Figure 1. Logic Diagram and Pinout Assignment
Figure 2. Logic Symbol
Table 1. PIN DESCRIPTION
PIN
CLKa, CLKb;
CLKa, CLKb
Q0:7; Q0:7
CLK_SEL
VBB
VCC, VCCO
VEE
NC
Table 2. FUNCTION TABLE
Function
PIN
ECL Differential Input Pairs
ECL Differential Input Pairs
ECL Differential Outputs
ECL Input Clock Select
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
0
1
http://onsemi.com
2
Function
CLKa Selected
CLKb Selected
MC100E310
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Rating
Unit
8
V
6
−6
V
V
50
100
mA
mA
± 0.5
mA
Operating Temperature Range
−40 to +85
°C
Storage Temperature Range
−65 to +150
°C
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
PLCC−28
22 to 26
°C/W
265
265
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Tstg
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
Tsol
Wave Solder
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
3
MC100E310
Table 4. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0 V (Note 1)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
60
Min
85°C
Typ
Max
55
60
Min
Typ
Max
Unit
65
70
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3915
3995
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 2)
3170
3305
3445
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage (Single−Ended)
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
VBB
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
2.7
4.6
2.7
4.6
2.7
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0 V; VEE = −5.0 V (Note 4)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
60
Min
85°C
Typ
Max
55
60
Min
Typ
Max
Unit
65
70
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1085
−1005
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 5)
−1830
−1695
−1555
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
−2.3
−0.4
−2.3
−0.4
−2.3
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
http://onsemi.com
4
MC100E310
Table 6. AC CHARACTERISTICS VCCx = 5.0 V; VEE= 0 V or VCCx = 0 V; VEE = −5.0 V (Note 7)
−40°C
Symbol
Characteristic
Min
Typ
900
fMAX
Maximum Toggle Frequency
700
tPLH
tPHL
Propagation Delay to Output
IN (differential) (Note 8)
IN (single−ended) (Note 9)
525
500
tskew
Within−Device Skew (Note 10)
Part−to−Part Skew (Diff)
tJITTER
Random Clock Jitter (RMS)
VPP
Input Voltage Swing
(Differential Configuration)
500
tr/tf
Output Rise/Fall Time
(20%−80%)
200
25°C
Max
725
750
Min
Typ
700
900
550
550
85°C
Max
750
800
75
250
Min
Typ
700
900
575
600
50
200
<1
<1
500
600
200
200
ps
ps
ps
500
600
Unit
MHz
775
850
50
200
<1
Max
mV
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary −0.46 V / +0.8 V.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1−12) of the ON Semiconductor
High Performance ECL Data Book (DL140/D).
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10. The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
http://onsemi.com
5
MC100E310
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
MC100E310FN
PLCC−28
37 Units / Rail
MC100E310FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E310FNR2
PLCC−28
500 / Tape & Reel
MC100E310FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
http://onsemi.com
6
MC100E310
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
-N-
0.007 (0.180)
B
Y BRK
U
T L -M
M
0.007 (0.180)
M
S
N
T L -M
S
S
N
S
D
-L-
Z
-M-
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L -M
S
N
S
VIEW D-D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
M
T L -M
T L -M
S
S
N
N
S
H
0.007 (0.180)
M
T L -M
N
S
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
-T-
T L -M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS ‐L‐, ‐M‐, AND ‐N‐ DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM ‐T‐, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
http://onsemi.com
7
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
—
0.025
—
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
—
0.020
2°
10°
0.410 0.430
0.040
—
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
10.42 10.92
1.02
—
M
T L -M
S
N
S
S
MC100E310
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
8
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100E310/D