MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage 2:8 Differential MC100LVE310 Fanout Buffer MC100E310 ECL/PECL Compatible The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The MC100E310 is pin compatible to the National 100310 device. The MC100LVE310 works from a –3.3V supply while the MC100E310 provides identical function and performance from a standard –4.5V 100E voltage supply. • • • • • LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER Dual Differential Fanout Buffers 200ps Part–to–Part Skew 50ps Output–to–Output Skew Low Voltage ECL/PECL Compatible 28–lead PLCC Packaging For applications which require a single–ended input, the VBB reference voltage is supplied. For single–ended input applications the VBB reference should be connected to the CLK input and bypassed to ground FN SUFFIX via a 0.01µf capacitor. The input signal is then driven into the CLK input. PLASTIC PACKAGE To ensure that the tight skew specification is met it is necessary that CASE 776–02 both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10–20ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE310, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE310 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note AN1406/D. 7/95 Motorola, Inc. 1996 4–1 REV 0.1 MC100LVE310 MC100E310 Q0 Q0 25 24 Q1 VCCO Q1 23 22 21 Q2 Q2 20 19 VEE 26 18 Q3 CLK_SEL 27 17 Q3 CLKa 28 16 Q4 15 VCCO PIN NAMES Pins VCC Pinout: 28–Lead PLCC (Top View) 1 CLKa, CLKb Q0:7 VBB CLK_SEL CLKa 2 14 Q4 VBB 3 13 Q5 CLK_SEL CLKb 4 12 Q5 0 1 5 6 CLKb NC 7 8 9 10 11 Q7 VCCO Q7 Q6 Q6 Function Differential Input Pairs Differential Outputs VBB Output Input Clock Select Input Clock CLKa Selected CLKb Selected LOGIC SYMBOL Q0 Q0 Q1 Q1 Q2 Q2 CLKa Q3 CLKa Q3 CLKb Q4 CLKb Q4 Q5 CLK_SEL Q5 Q6 Q6 Q7 Q7 VBB MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVE310 MC100E310 MC100LVE310 ECL DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V VOL Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V VIH Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V VIL Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V VBB Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V VEE Power Supply Voltage –3.0 –3.8 –3.0 –3.8 –3.0 –3.8 –3.0 –3.8 V IIH Input HIGH Current IEE Power Supply Current 150 55 150 60 55 150 60 55 60 65 150 µA 70 mA MC100LVE310 PECL DC CHARACTERISTICS –40°C Symbol Characteristic 0°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage1 2.215 2.295 2.42 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 V VOL Output LOW Voltage1 1.47 1.605 1.745 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 V VIH Input HIGH Voltage1 2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V VIL Input LOW Voltage1 1.490 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V VBB Output Reference Voltage1 1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V VCC Power Supply Voltage 3.0 3.8 3.0 3.8 3.0 3.8 3.0 IIH Input HIGH Current IEE Power Supply Current 150 55 150 60 55 150 60 55 60 65 3.8 V 150 µA 70 mA 1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC. MC100LVE310 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) –40°C Symbol Typ 0°C Max Min 725 750 550 525 Typ 25°C Max Min 750 775 550 550 Typ 85°C Characteristic Min Max Min 750 800 575 600 Typ Max tPLH tPHL Propagation Delay to Output IN (differential) IN (single–ended) 525 500 tskew Within–Device Skew Part–to–Part Skew (Diff) VPP Minimum Input Swing 500 VCMR Common Mode Range –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 tr/tf Output Rise/Fall Time 200 600 200 600 200 600 200 600 Unit Condition ps 75 250 75 200 500 50 200 500 775 850 50 200 500 Note 1 Note 2 ps Note 3 mV Note 4 V Note 5 ps 20%–80% 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVE310 MC100E310 MC100E310 ECL DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V VOL Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V VIH Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V VIL Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V VBB Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V VEE Power Supply Voltage –5.25 –4.2 –5.25 –4.2 –5.25 –4.2 –5.25 –4.2 V IIH Input HIGH Current IEE Power Supply Current 150 55 150 60 55 150 60 55 60 65 150 µA 70 mA MC100E310 PECL DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage1 3.915 3.995 4.12 3.975 4.045 4.12 3.975 4.045 4.12 3.975 4.045 4.12 V VOL Output LOW Voltage1 3.170 3.305 3.445 3.19 3.295 3.38 3.19 3.295 3.38 3.19 3.295 3.38 V VIH Input HIGH Voltage1 3.835 4.12 3.835 4.12 3.835 4.12 3.835 4.12 V VIL Input LOW Voltage1 3.190 3.525 3.190 3.525 3.190 3.525 3.190 3.525 V VBB Output Reference Voltage1 3.62 3.74 3.62 3.74 3.62 3.74 3.62 3.74 V VCC Power Supply Voltage 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 V IIH Input HIGH Current 150 µA IEE Power Supply Current 70 mA 150 55 150 60 55 150 60 55 60 65 1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC. MC100E310 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) –40°C Symbol Typ 0°C Max Min 725 750 550 525 Typ 25°C Max Min 750 775 550 550 Typ 85°C Characteristic Min Max Min 750 800 575 600 Typ Max tPLH tPHL Propagation Delay to Output IN (differential) IN (single–ended) 525 500 tskew Within–Device Skew Part–to–Part Skew (Diff) VPP Minimum Input Swing 500 VCMR Common Mode Range –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 tr/tf Output Rise/Fall Time 200 600 200 600 200 600 200 600 Unit Condition ps 75 250 75 200 500 50 200 500 775 850 50 200 500 Note 1 Note 2 ps Note 3 mV Note 4 V note 5 ps 20%–80% 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E310 as a differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). MOTOROLA 4–4 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVE310 MC100E310 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). ECLinPS and ECLinPS Lite DL140 — Rev 3 T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) 4–5 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.57 4.20 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.58 11.43 11.43 11.58 1.07 1.21 1.07 1.21 1.42 1.07 — 0.50 2° 10° 10.42 10.92 1.02 — MOTOROLA MC100LVE310 MC100E310 Motorola reserves the right to make changes without further notice to any products herein. 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