MC100EP16VC D

MC100EP16VC
3.3V/5V ECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
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MARKING DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
1
TSSOP−8
DT SUFFIX
CASE 948R
8
KEP66
ALYW
G
1
8
8
1
KP66
ALYWG
G
DFN8
MN SUFFIX
CASE 506AA
3G MG
G
The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
EN goes HIGH, it will force the QHG LOW and the QHG HIGH on the
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
and QHG remains LOW and QHG remains HIGH. The next positive
transition of the data input is not passed on to the data outputs under
these conditions. The QHG and QHG outputs remain in their disabled
state as long as the EN input is held HIGH. The EN input has no
influence on the Q output and the data input is passed on (inverted) to
this output whether EN is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
The VBB/D pin is internally dedicated and available for differential
interconnect. VBB/D may rebias AC coupled inputs. When used,
decouple VBB/D and VCC via a 0.01 mF capacitor and limit current
sourcing or sinking to 1.5 mA. When not used, VBB/D should be left
open.
The 100 Series contains temperature compensation.
1
A
L
Y
W
M
G
4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
Features
*For additional marking information, refer to
Application Note AND8002/D.
• 310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
• Gain > 200
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
•
•
•
•
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
QHG Output Will Default LOW with D Inputs Open or at VEE
VBB Output
Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 7
1
Publication Order Number:
MC10EP16VC/D
MC100EP16VC
Table 1. PIN DESCRIPTION
Q
D
VBB/D
1
8
2
7
6
3
LEN
VBB
EN
4
Q
VCC
Pin
QHG
QHG
OE
LATCH
5
D
Function
D*
ECL Data Input
Q
ECL Data Output
QHG, QHG
ECL High Gain Data Outputs
EN*
ECL Enable Input
VBB/D
Reference Voltage Output / ECL Data Input
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit. Electrically connect to the most negative supply
(GND) or leave unconnected, floating open.
VEE
*Pins will default LOW when left open.
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EP16VC
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 TSSOP
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
VI v VCC
VI w VEE
Pb
Pb−Free
(Note 2)
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
27
37
47
32
42
52
34
44
54
mA
VOH
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 4)
1305
1400
1555
1305
1400
1555
1305
1400
1555
mV
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
2045
1775
2045
1775
2045
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1890
2.0
150
D
0.5
1890
150
0.5
0.5
1890
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
4. All loading with 50 W to VCC − 2.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP16VC
Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
27
37
47
32
42
52
34
44
54
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 7)
3005
3100
3255
3005
3100
3255
3005
3100
3255
mV
VIH
Input HIGH Voltage (Single−Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3705
3475
3705
3475
3705
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
3490
2.0
3490
150
D
3490
150
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
7. All loading with 50 W to VCC − 2.0 V.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 9)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
27
37
47
32
42
52
34
44
54
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 10)
−1995
−1900
−1745
−1995
−1900
−1745
−1995
−1900
−1745
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625
−1945
−1625
−1945
−1625
mV
VBB
Output Voltage Reference
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 11)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1425
VEE + 2.0
0.0
VEE + 2.0
150
0.5
−1425
0.0
VEE + 2.0
150
0.5
−1425
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 W to VCC − 2.0 V.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC100EP16VC
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
>3
85°C
Typ
Max
Min
>3
Typ
Max
fmax
Maximum Frequency (Figure 2)
tPLH,
tPHL
Propagation Delay
(Differential) Q
(Differential) QHG, QHG
(Single−Ended) Q
(Single−Ended) QHG, QHG
200
250
250
300
280
360
330
410
tS
Setup Time
EN = L to D
EN =H to D
50
100
tH
Hold Time
EN = L to D
EN =H to D
100
50
tSKEW
Duty Cycle Skew (Note 13)
5.0
20
5.0
20
5.0
20
ps
tJITTER
RMS Random Clock Jitter (Figure 2)
0.2
<1
0.2
<1
0.2
<1
ps
VPP
Input Voltage Swing
(Differential Configuration)
tr
tf
Output Rise/Fall Times
(20% − 80%)
350
450
400
500
250
300
300
350
310
380
360
430
15
60
50
100
50
15
100
50
>3
Unit
400
500
450
550
GHz
275
325
325
375
340
430
390
480
425
525
475
575
ps
5
40
50
100
18
10
ps
40
20
100
50
5
20
ps
HG
Q
25
150
800
800
1200
1200
25
150
800
800
1200
1200
25
150
800
800
1200
1200
mV
Q
QHG, QHG
200
70
300
130
400
220
250
80
350
150
450
240
250
100
350
170
500
270
ps
900
9
800
8
700
7
600
6
500
5
JITTEROUT ps (RMS)
VOUTpp (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
ÉÉ
ÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
2500
3000
3500
FREQUENCY (MHz)
Figure 2. Fmax/Jitter for QHG, QHG Output
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5
4000
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
0
0
500
1000
1500
2000
2500
3000
3500
JITTEROUT ps (RMS)
VOUTpp (mV)
MC100EP16VC
ÉÉ
ÉÉ
4000
FREQUENCY (MHz)
900
9
800
8
700
7
600
6
500
5
400
4
300
3
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
200
2
100
1
0
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
Figure 4. Fmax/Jitter for QHG, QHG Output
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6
3000
JITTEROUT ps (RMS)
VOUTpp (mV)
Figure 3. Fmax/Jitter for Q Output
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
JITTEROUT ps (RMS)
VOUTpp (mV)
MC100EP16VC
ÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
0
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 5. Fmax/Jitter for Q Output
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC100EP16VC
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC100EP16VCDG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EP16VCDR2
SOIC−8
2500 / Tape & Reel
MC100EP16VCDR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EP16VCDT
TSSOP−8
100 Units / Rail
MC100EP16VCDTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EP16VCDTR2
TSSOP−8
2500 / Rail
MC100EP16VCDTR2G
TSSOP−8
(Pb−Free)
2500 / Rail
MC100EP16VCMNR4
DFN8
1000 / Tape & Reel
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC100EP16VCD
MC100EP16VCMNR4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100EP16VC
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100EP16VC
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
V
S
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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10
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EP16VC
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
2X
0.10 C
2X
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
TOP VIEW
0.10 C
0.08 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
(A3)
SIDE VIEW
A1
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
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MC100EP16VC/D