MC100EP16VC 3.3V / 5VECL Differential Receiver/Driver with High Gain and Enable Output The EP16VC is a differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output. The EP16VC provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and QHG outputs. When the EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and EN goes HIGH, it will force the QHG LOW and the QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and QHG outputs remain in their disabled state as long as the EN input is held HIGH. The EN input has no influence on the Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output. The VBB/D pin is internally dedicated and available for differential interconnect. VBB/D may rebias AC coupled inputs. When used, decouple VBB/D and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 1.5 mA. When not used, VBB/D should be left open. The 100 Series contains temperature compensation. • • • • • 310 ps Typical Prop Delay Q, 380 ps Typical Prop Delay QHG, QHG Gain > 200 Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State • • QHG Output Will Default LOW with D Inputs Open or at VEE • VBB Output http://onsemi.com MARKING DIAGRAMS* 8 8 KEP66 ALYW 1 SO−8 D SUFFIX CASE 751 1 8 8 KP66 ALYW 1 TSSOP−8 DT SUFFIX CASE 948R 1 K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Package Shipping MC100EP16VCD SO−8 98 Units/Rail MC100EP16VCDR2 SO−8 2500 Tape & Reel MC100EP16VCDT TSSOP−8 100 Units/Rail MC100EP16VCDTR2 TSSOP−8 2500 Tape & Reel Semiconductor Components Industries, LLC, 2003 September, 2003− Rev. 2 1 Publication Order Number: MC100EP16VC/D MC100EP16VC Q D VBB/D 1 8 2 7 6 3 LEN VBB EN Q PIN DESCRIPTION QHG QHG OE LATCH 4 VCC 5 D VEE PIN FUNCTION D* ECL Data Input Q ECL Data Output QHG, QHG ECL High Gain Data Outputs EN* ECL Enable Input VBB/D Reference Voltage Output / ECL Data Input VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. Figure 1. 8−Lead Pinout (Top View) and Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Parameter Symbol Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 8 SOIC 8 SOIC 190 130 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 8 SOIC 41 to 44 °C/W JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 8 TSSOP 8 TSSOP 185 140 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 8 TSSOP 41 to 44 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 VI VCC VI VEE MC100EP16VC 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) Symbol IEE Characteristic Power Supply Current Min −40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 25 36 45 30 40 50 32 42 52 Unit mA VOH Output HIGH Voltage (Note 4) 2105 2230 2355 2105 2230 2355 2105 2230 2355 mV VOL Output LOW Voltage (Note 4) 1305 1430 1555 1305 1430 1555 1305 1430 1555 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1725 1925 1700 1900 1675 1875 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1825 2.0 1800 150 D 1775 150 0.5 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 4. All loading with 50 to VCC−2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) −40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max Symbol IEE Characteristic Power Supply Current Min 25 36 45 30 40 50 32 42 52 Unit mA VOH Output HIGH Voltage (Note 7) 3805 3930 4055 3805 3930 4055 3805 3930 4055 mV VOL Output LOW Voltage (Note 7) 3005 3130 3255 3005 3130 3255 3005 3130 3255 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VBB Output Voltage Reference 3425 3625 3400 3600 3375 3575 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current 3525 2.0 3500 150 D 3475 150 0.5 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 7. All loading with 50 to VCC−2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 9) Min −40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 25 36 45 30 40 50 32 42 52 Unit mA Output HIGH Voltage (Note 10) −1195 −1070 −945 −1195 −1070 −945 −1195 −1070 −945 mV Output LOW Voltage (Note 10) −1995 −1870 −1745 −1995 −1870 −1745 −1995 −1870 −1745 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VBB Output Voltage Reference −1575 −1375 −1600 −1400 −1625 −1425 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 11) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current Symbol IEE Characteristic Power Supply Current VOH VOL −1475 VEE+2.0 0.0 VEE+2.0 150 D 0.5 −1500 0.0 VEE+2.0 150 0.50 −1525 0.5 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 to VCC−2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100EP16VC AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 12) −40°C Symbol Min Characteristic Typ 25°C Max Min >3 Typ 85°C Max Min >3 Typ Max fmax Maximum Frequency (See Figure 2 Fmax/JITTER) tPLH, tPHL Propagation Delay (Differential) Q (Differential) QHG, QHG (Single−Ended) Q (Single−Ended) QHG, QHG 200 250 250 300 280 360 330 410 tS Setup Time EN = L to D EN =H to D 50 100 tH Hold Time EN = L to D EN =H to D 100 50 tSKEW Duty Cycle Skew (Note 13) 5.0 20 5.0 20 5.0 20 ps tJITTER RMS Random Clock Jitter (See Figure 2 Fmax/JITTER) 0.2 <1 0.2 <1 0.2 <1 ps VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Times (20% − 80%) 350 450 400 500 250 300 300 350 310 380 360 430 15 60 50 100 50 15 100 50 >3 Unit 400 500 450 550 GHz 275 325 325 375 340 430 390 480 425 525 475 575 ps 5 40 50 100 18 10 ps 40 20 100 50 5 20 ps HG Q 25 150 800 800 1200 1200 25 150 800 800 1200 1200 25 150 800 800 1200 1200 mV Q QHG, QHG 200 70 300 130 400 220 250 80 350 150 450 240 250 100 350 170 500 270 ps 12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. 13. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. http://onsemi.com 4 MC100EP16VC 900 9 800 8 700 7 600 6 500 5 JITTEROUT ps (RMS) VOUTpp (mV) Single−Ended Input ÉÉ ÉÉÉÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉ 400 4 300 3 200 2 100 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) 900 9 800 8 700 7 600 6 500 5 JITTEROUT ps (RMS) VOUTpp (mV) Figure 2. Fmax/Jitter for QHG, QHG Output ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ 400 4 300 3 200 2 100 1 0 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) Figure 3. Fmax/Jitter for Q Output http://onsemi.com 5 3500 4000 MC100EP16VC 900 9 800 8 700 7 600 6 500 5 JITTEROUT ps (RMS) VOUTpp (mV) Differential Inputs ÉÉ ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 400 4 300 3 200 2 100 1 0 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 900 9 800 8 700 7 600 6 500 5 JITTEROUT ps (RMS) VOUTpp (mV) Figure 4. Fmax/Jitter for QHG, QHG Output ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ 400 4 300 3 200 2 100 1 0 0 500 1000 1500 2000 FREQUENCY (MHz) Figure 5. Fmax/Jitter for Q Output http://onsemi.com 6 2500 3000 MC100EP16VC Q D Receiver Device Driver Device Q D 50 50 V TT V TT = V CC − 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1504 − Metastability and the ECLinPS Family AN1568 − Interfacing Between LVDS and ECL AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8009 − ECLinPS Plus Spice I/O Model Kit AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 7 MC100EP16VC PACKAGE DIMENSIONS SO−8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751−07 ISSUE AA −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07 A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 8 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC100EP16VC PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S 5 0.25 (0.010) B −U− L 0.15 (0.006) T U M M 4 A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 9 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0 6 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0 6 MC100EP16VC ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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